JP2001313307A - Flip chip having multistage bump and flip-chip assembly using the same - Google Patents

Flip chip having multistage bump and flip-chip assembly using the same

Info

Publication number
JP2001313307A
JP2001313307A JP2000129183A JP2000129183A JP2001313307A JP 2001313307 A JP2001313307 A JP 2001313307A JP 2000129183 A JP2000129183 A JP 2000129183A JP 2000129183 A JP2000129183 A JP 2000129183A JP 2001313307 A JP2001313307 A JP 2001313307A
Authority
JP
Japan
Prior art keywords
chip
bump
circuit board
flip
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000129183A
Other languages
Japanese (ja)
Inventor
Kazuo Uchiyama
一男 内山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Avionics Co Ltd
Original Assignee
Nippon Avionics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Avionics Co Ltd filed Critical Nippon Avionics Co Ltd
Priority to JP2000129183A priority Critical patent/JP2001313307A/en
Publication of JP2001313307A publication Critical patent/JP2001313307A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which the connection reliability of flip chips and a flip-chip assembly, in which the flip chips are mounted on a circuit board is improved. SOLUTION: On the electrodes 11 of an IC chip 1, the flip chips having multistage bumps 13 each of which is composed of a bump skeleton section 13a, and a bump buffer connecting section 13b are formed by the ball-bonding method. At formation of the flip-chip assembly 3 in which the flip chips are mounted on the circuit board 2, the bumps 13 are aligned with and jointed to the pads 21 of the circuit board 2 by applying a thermosetting insulating adhesive 22 to the circuit board 2 and pressing the chip 1 and board 2 against each other, while the adhesive 22 is being heated. The connection reliability between the bumps 13 and pads 12 is improved, by correcting the uneven heights of the bumps 13 and the insufficient flatness of the board 1 through the deformation of the connection sections 13b caused, when the chip 1 and board 2 are pressed against each other.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、金属細線を用いボ
ールボンディング法等によりICチップの電極上にバン
プを形成する技術と、フリップチップを回路基板に実装
する技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for forming a bump on an electrode of an IC chip by a ball bonding method using a thin metal wire and a technique for mounting a flip chip on a circuit board.

【0002】[0002]

【従来の技術】ICチップの電極にバンプを形成する方
法の一つにワイヤボンダを用いたボールボンディング法
がある。この方法は半導体の生産設備を持たない電子機
器の製造業者等が対応できるバンプ形成の簡便な方法と
して広く知られている。はじめにボールボンディング法
によるバンプの形成について、図3の模式図を用いて説
明する。次にボールボンディング法によるバンプを備え
たフリップチップを回路基板に実装しフリップチップア
センブリを形成する従来の技術について、図4の模式図
を用いて概観する。
2. Description of the Related Art One of the methods for forming bumps on electrodes of an IC chip is a ball bonding method using a wire bonder. This method is widely known as a simple method of forming bumps that can be handled by manufacturers of electronic devices without semiconductor production facilities. First, formation of a bump by a ball bonding method will be described with reference to the schematic diagram of FIG. Next, a conventional technique of forming a flip chip assembly by mounting a flip chip provided with a bump by a ball bonding method on a circuit board will be outlined with reference to a schematic diagram of FIG.

【0003】図3−aに示すように、ワイヤボンダ4の
キャピラリ41と呼ばれるガラス等でできた細管の中に
金属細線44を通す。次にワイヤボンダ4の放電電極4
2に高電圧を印加する。この高電圧により放電電極42
とキャピラリ41の先端から突き出た金属細線44の間
に放電電流が流れ、金属細線44のキャピラリ41先端
から突き出た部分が溶融し、図3−bに示す球形の溶融
部分44aが形成される。
As shown in FIG. 3A, a thin metal wire 44 is passed through a thin tube called a capillary 41 of a wire bonder 4 made of glass or the like. Next, the discharge electrode 4 of the wire bonder 4
2 is applied with a high voltage. This high voltage causes the discharge electrode 42
A discharge current flows between the thin metal wire 44 protruding from the tip of the capillary 41 and the portion of the fine metal wire 44 protruding from the tip of the capillary 41 is melted to form a spherical molten portion 44a shown in FIG.

【0004】次に図3−cの如くキャピラリ41を降下
し、キャピラリ41先端に位置する金属細線44の溶融
部分44aをICチップ1の電極11に押圧する。同時
にキャピラリ41を加振し、図示しないホットプレート
等を用いてICチップ1を下面から加熱する。これによ
って金属細線44の溶融部分44aはICチップ1の電
極11に接合される。
Next, as shown in FIG. 3C, the capillary 41 is lowered, and the molten portion 44a of the thin metal wire 44 located at the tip of the capillary 41 is pressed against the electrode 11 of the IC chip 1. At the same time, the capillary 41 is vibrated, and the IC chip 1 is heated from below using a hot plate or the like (not shown). As a result, the molten portion 44a of the thin metal wire 44 is joined to the electrode 11 of the IC chip 1.

【0005】つづいて、図3−dに示す如くワイヤボン
ダ3のクランパ43によって金属細線44を挟み込みキ
ャピラリ41を上方に引き揚げる。この操作により金属
細線44は、溶融部分44aの頂部付近で切り離され
る。以上に記したワイヤボンダ4の一連の操作によって
ICチップ1の電極11上にバンプ12が形成される。
Subsequently, as shown in FIG. 3D, the capillary 41 is pulled upward by sandwiching the thin metal wire 44 by the clamper 43 of the wire bonder 3. By this operation, the thin metal wire 44 is cut off near the top of the molten portion 44a. The bumps 12 are formed on the electrodes 11 of the IC chip 1 by a series of operations of the wire bonder 4 described above.

【0006】フリップチップは回路基板に実装すること
で電気回路として機能する。つぎに上述したボールボン
ディング法で形成したバンプをもつICチップを回路基
板に実装する方法の一つを述べる。
A flip chip functions as an electric circuit when mounted on a circuit board. Next, one method of mounting an IC chip having bumps formed by the above-described ball bonding method on a circuit board will be described.

【0007】図4は絶縁性の接着剤を用いた実装方法を
示し、回路基板2にICチップ1のバンプ12と接合す
る為の電極(以下、パッド21という)を備え、バンプ
12をパッド21の上に載置し押圧する(図4−a)。
バンプ12とパッド21が接触することにより電気的に
接続し、ICチップ1と回路基板2の間隙部分に塗布し
た絶縁性の接着剤22により上記の電気接続を機械的に
保持する(図4−b)。
FIG. 4 shows a mounting method using an insulating adhesive. The circuit board 2 is provided with electrodes (hereinafter referred to as pads 21) for bonding to the bumps 12 of the IC chip 1, and the bumps 12 are connected to the pads 21. And press it (FIG. 4-a).
The bumps 12 and the pads 21 are electrically connected by contact with each other, and the electrical connection is mechanically held by an insulating adhesive 22 applied to a gap between the IC chip 1 and the circuit board 2 (FIG. 4). b).

【0008】[0008]

【発明が解決しようとする課題】ここで図4に示した絶
縁性の接着剤を用いてフリップチップを回路基板に実装
する方法を仔細に観察すると、ボールボンディング法に
よるバンプ12の頂部は従来の技術として前述したとお
り金属細線44を引きちぎった端末部分であり、高さが
不揃いで先端の細く尖ったものになる。
Here, a detailed observation of the method of mounting the flip chip on the circuit board using the insulating adhesive shown in FIG. 4 shows that the top of the bump 12 by the ball bonding method is a conventional one. As described above as a technique, it is a terminal portion where the thin metal wire 44 is torn off, and the tip is thin and sharp at an irregular height.

【0009】このような形状をしたバンプ12の頂部と
回路基板2のパッド21の点接触によって電気的な接続
が果たされるため、高さの不揃いなバンプ12の接続は
不確実なものになる。このため、バンプの頂部を金属板
等で押さえバンプの高さを平準化する方法が採られてい
る。
Since electrical connection is achieved by the point contact between the top of the bump 12 having such a shape and the pad 21 of the circuit board 2, the connection of the bumps 12 having irregular heights is uncertain. For this reason, a method has been adopted in which the tops of the bumps are pressed with a metal plate or the like to level the height of the bumps.

【0010】然しながら、接続の相手方である回路基板
にも反り等があり、回路基板の平面度も十分に確保され
ていなければ接続は不確実になり、フリップチップ実装
の信頼性に懸念が生じることになる。
[0010] However, the circuit board to be connected also has a warp or the like, and if the flatness of the circuit board is not sufficiently ensured, the connection becomes unreliable and there is a concern about the reliability of flip-chip mounting. become.

【0011】本発明はこのような電気接続の問題点を解
決するためになされたもので、不揃いなバンプの高さと
回路基板の平面度を補正するバンプを備えたフリップチ
ップと、該フリップチップを回路基板に実装したフリッ
プチップアセンブリにより、接続信頼性の高い半導体装
置の提供を課題とする。
The present invention has been made in order to solve such a problem of the electric connection, and a flip chip having bumps for correcting irregular bump heights and flatness of a circuit board, and a flip chip having the same structure. It is an object to provide a semiconductor device with high connection reliability by a flip chip assembly mounted on a circuit board.

【0012】[0012]

【課題を解決するための手段】接続信頼性の高い半導体
装置を提供するICチップは、フリップチップ構造のI
Cチップであって、ICチップの電極に接合したバンプ
枢体部分と該バンプ枢体部分から続く逆L字型のバンプ
緩衝接続部分からなることを特徴とした多段構造のバン
プを有するフリップチップであり、前記バンプ緩衝接続
部分を回路基板の電極に接触する電気回路の形成におい
て、該バンプの高さの不揃いと回路基板の平面度の精度
不足を補正する作用を有する。
An IC chip for providing a semiconductor device with high connection reliability is an IC chip having a flip-chip structure.
A flip chip having a multi-staged bump, which is a C chip, comprising a bump pivot portion joined to an electrode of an IC chip and an inverted L-shaped bump buffer connection portion following the bump pivot portion. In forming an electric circuit in which the bump buffer connection portion is brought into contact with an electrode of a circuit board, the bumper has an effect of correcting unevenness in the height of the bumps and insufficient precision in flatness of the circuit board.

【0013】さらに高い接合信頼性を提供するフリップ
チップアセンブリは、前記フリップチップを回路基板に
実装したアセンブリであって、前記フリップチップと回
路基板を熱硬化性絶縁性接着剤を用いて接合し、該フリ
ップチップのバンプと回路基板の電極の接触を前記熱硬
化性絶縁性接着剤により保持したことを特徴とする。
[0013] A flip chip assembly that provides higher bonding reliability is an assembly in which the flip chip is mounted on a circuit board, wherein the flip chip and the circuit board are bonded using a thermosetting insulating adhesive. The contact between the bump of the flip chip and the electrode of the circuit board is held by the thermosetting insulating adhesive.

【0014】[0014]

【発明の実施の形態】本発明による多段構造のバンプを
有するフリップチップ、及び該フリップチップを回路基
板に実装したフリップチップアセンブリの一実施形態に
ついて、図を用いて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a flip chip having bumps of a multi-stage structure according to the present invention and a flip chip assembly in which the flip chip is mounted on a circuit board will be described with reference to the drawings.

【0015】図1は本発明による多段構造のバンプを有
するフリップチップの断面(図1−a)と、該フリップ
チップを用いて本発明のフリップチップアセンブリを形
成する過程の要部の断面(図1−b乃至図1−c)とを模
式的に示している。図2は多段構造のバンプを形成する
過程の要部を示した模式図である。
FIG. 1 is a cross-sectional view of a flip chip having a bump having a multi-stage structure according to the present invention (FIG. 1A), and a cross-sectional view (FIG. 1-b to 1-c) are schematically shown. FIG. 2 is a schematic view showing a main part of a process of forming a bump having a multi-stage structure.

【0016】図3は従来のボールボンディング法による
バンプ形成の過程を示した模式図である。図4は従来の
ボールボンディング法により形成されたICチップを絶
縁性の接着剤を用いて回路基板に実装した、従来のフリ
ップチップアセンブリの形成過程の要部を模式的に示し
ている。なお、図1乃至図2において図3乃至図4に示
したものと対応する部分については同一の参照符号を付
している。
FIG. 3 is a schematic view showing a process of forming a bump by a conventional ball bonding method. FIG. 4 schematically shows a main part of a conventional flip chip assembly in which an IC chip formed by a conventional ball bonding method is mounted on a circuit board using an insulating adhesive. In FIGS. 1 and 2, parts corresponding to those shown in FIGS. 3 and 4 are denoted by the same reference numerals.

【0017】最初に第一の発明である多段構造のバンプ
有するフリップチップについて、該バンプ形成の過程を
説明する。工程の第1は、図3を用いて先述した従来の
ボールボンディング法を踏襲するものであり、図3−a
乃至図3−bにおいて、キャピラリ41の中に金属細線
44を通し、次に放電電極42に高電圧を印加する。
First, the process of forming the bumps of the flip chip having the bumps of the multistage structure according to the first invention will be described. The first of the steps follows the conventional ball bonding method described above with reference to FIG.
3B, a thin metal wire 44 is passed through the capillary 41, and then a high voltage is applied to the discharge electrode 42.

【0018】放電電極42とキャピラリ41の先端から
突き出た金属細線44に生じる放電により、金属細線4
4の先端部分を溶融する。放電電極42と金属細線44
先端部分の間隔、及び放電電極42に印加する電圧と印
加時間を加減する事により、金属細線44の溶融を制御
することができる。
The discharge generated in the discharge electrode 42 and the thin metal wire 44 protruding from the tip of the capillary 41 causes the thin metal wire 4
4 is melted. Discharge electrode 42 and thin metal wire 44
The melting of the thin metal wire 44 can be controlled by adjusting the interval between the tips and the voltage and application time applied to the discharge electrode 42.

【0019】金属細線44の溶融部分44aの形状は印
加する電圧と時間の積によって変化する。金属細線44
に直径20μmのAu細線を用い、放電電極42とAu
細線先端の間隔を所定の値に設定し、印加電圧を2k
v、印加時間を5msとする実施例において、Au細線
の先端は直径約60μmの球状に溶融している。
The shape of the molten portion 44a of the thin metal wire 44 changes depending on the product of the applied voltage and time. Metal wire 44
A 20 μm diameter Au thin wire is used for the discharge electrode 42 and the Au
Set the interval between the tips of the fine wires to a predetermined value and set the applied voltage to 2k.
In the embodiment in which the application time is 5 ms, the tip of the Au thin wire is melted into a spherical shape having a diameter of about 60 μm.

【0020】工程の第2において、前述した金属細線4
4の球形をした溶融部分44aとICチップ1の電極1
1を接合し、同時に多段構造のバンプ13の下部構造で
あるバンプ枢体部分13aを形成する。図2−aに示す
如く、溶融部分44aの直下にICチップ1の電極11
を配置し、キャピラリ41を下降して溶融部分44aを
電極11に押圧する。
In the second step, the fine metal wire 4 described above is used.
4 of the spherical molten portion 44a and the electrode 1 of the IC chip 1
1 and, at the same time, a bump pivot portion 13a which is a lower structure of the bump 13 having a multi-stage structure is formed. As shown in FIG. 2A, the electrode 11 of the IC chip 1 is located immediately below the molten portion 44a.
Is arranged, and the molten portion 44 a is pressed against the electrode 11 by descending the capillary 41.

【0021】さらにキャピラリ41を超音波により加振
し、同時にICチップ1を加熱することで金属細線44
の溶融部分44aとICチップ1の電極11は接合され
る。この溶融部分44aは、図1−aに示す多段構造の
バンプ13を構成するバンプ枢体部分13aとなる。
Further, the capillary 41 is vibrated by ultrasonic waves, and at the same time, the IC chip 1 is heated, so that the thin metal wires 44 are formed.
Is fused to the electrode 11 of the IC chip 1. This fused portion 44a becomes the bump pivot portion 13a that constitutes the bump 13 having the multi-stage structure shown in FIG.

【0022】300gの押圧と60KHzの超音波振動
によって、前述した直径約60μmの溶融部分は、直径
約80μmのバンプの枢体部分に整形され、ICチップ
の一般的な電極である一辺100μmの四辺形電極に適
合したものになる。
By the pressing of 300 g and the ultrasonic vibration of 60 KHz, the above-mentioned melted portion having a diameter of about 60 μm is shaped into a pivot portion of a bump having a diameter of about 80 μm, and the four sides of 100 μm as a general electrode of an IC chip. It will be suitable for shaped electrodes.

【0023】工程の第3において、バンプ枢体部分13
aの頂部から続く金属細線44を逆L字形に端末処理
し、多段構造のバンプ13を構成するバンプ緩衝接続部
分13bを形成する。これはキャピラリ41の微動操作
によって形成され、図2−bにこの様子を示す。
In a third step, the bump pivot 13
A thin metal wire 44 continuing from the top of a is terminated into an inverted L-shape to form a bump buffer connection portion 13b constituting the multi-stage bump 13. This is formed by the fine movement operation of the capillary 41, and this is shown in FIG.

【0024】まずキャピラリ41を垂直方向に所定の位
置まで引き揚げ、これ続いて水平方向に所定の距離だけ
移動し停止する。この操作により金属細線44は、キャ
ピラリ41の垂直方向から水平方向への移動に伴う応分
の長さだけ引き出される。
First, the capillary 41 is pulled up to a predetermined position in the vertical direction, and then moves horizontally and stops at a predetermined distance. By this operation, the thin metal wire 44 is drawn out by a length corresponding to the movement of the capillary 41 from the vertical direction to the horizontal direction.

【0025】次にクランパ43によって金属細線44を
挟み込み、再度キャピラリ41を前記の延長方向(水平
方向)に移動する。この移動によりキャピラリ41の先
端内面は金属細線44を捉えて切断し、バンプ緩衝接続
部分13bが形成される。
Next, the thin metal wire 44 is sandwiched by the clamper 43, and the capillary 41 is moved again in the extending direction (horizontal direction). By this movement, the inner surface of the tip end of the capillary 41 catches and cuts the thin metal wire 44 to form the bump buffer connection portion 13b.

【0026】前記したキャピラリ41の移動量は微細な
ものであり、垂直方向と水平方向の移動量を金属細線4
4の直径の各々略2倍とした場合、金属細線44の切断
位置はバンプ枢体部分13aの外縁上部付近13zにな
る。このため隣接したバンプと接触する懸念はない。
The amount of movement of the capillary 41 is minute, and the amount of movement in the vertical and horizontal directions is
In the case where the diameter of each of the metal wires 4 is approximately twice as large, the cutting position of the thin metal wire 44 is near the upper portion 13z of the outer edge of the bump pivot 13a. Therefore, there is no fear of contact with the adjacent bump.

【0027】斯くして、バンプ枢体部分13aとバンプ
緩衝接続部分13bからなる多段構造のバンプ13が形
成される。直径20μmのAu細線を用いた実施例で
は、直径80μmのバンプ枢体部分の上に、40μmの
垂直部位と40μmの水平部位をもつバンプ緩衝接続部
分13bが形成されている。
In this manner, the bump 13 having a multi-stage structure including the bump pivot portion 13a and the bump buffer connection portion 13b is formed. In the embodiment using a thin Au wire having a diameter of 20 μm, a bump buffer connection portion 13 b having a vertical portion of 40 μm and a horizontal portion of 40 μm is formed on a bump pivot portion having a diameter of 80 μm.

【0028】第2の発明である多段構造のバンプを用い
たフリップチップアセンブリの形成について図1により
説明する。組立工程の第1において、回路基板2に熱硬
化性絶縁性接着剤22(以下、接着剤22という)を塗
布する。塗布は、図1−bに示す如くICチップを載置
する部分の中央付近にパッド21を避けて所定量塗布す
る。また、ICチップのサイズとバンプの数によっては
多点塗布してもよい。
The formation of the flip chip assembly using the multi-stage bumps according to the second invention will be described with reference to FIG. In the first of the assembling steps, a thermosetting insulating adhesive 22 (hereinafter referred to as an adhesive 22) is applied to the circuit board 2. As shown in FIG. 1B, a predetermined amount is applied near the center of the portion where the IC chip is mounted, avoiding the pad 21. Further, multi-point coating may be performed depending on the size of the IC chip and the number of bumps.

【0029】組立工程の第2において、組立工程の第1
による回路基板1の直上に多段構造のバンプ13を備え
たICチップ1(図1−a)をフェースダウンに配置す
る。然るのち、ICチップ1の電極11と回路基板2の
パッド21の位置を合わせ、図1−cの如くICチップ
1を回路基板2に載置し、押圧する。この押圧によっ
て、組立工程の第1で塗布した接着剤22はICチップ
1と回路基板2の間隙の略全面に回り込む。
In the second part of the assembling step, the first part of the assembling step is performed.
The IC chip 1 (FIG. 1-a) provided with the bumps 13 having a multi-stage structure is disposed face-down directly on the circuit board 1 according to (1). Thereafter, the positions of the electrodes 11 of the IC chip 1 and the pads 21 of the circuit board 2 are aligned, and the IC chip 1 is placed on the circuit board 2 as shown in FIG. Due to this pressing, the adhesive 22 applied in the first step of the assembly process wraps around substantially the entire gap between the IC chip 1 and the circuit board 2.

【0030】組立工程の第3において、組立工程の第2
によるICチップ1と回路基板2の組立体を加熱する。
接着剤22の硬化によって、ICチップ1と回路基板2
は固着し、ICチップ1の多段構造のバンプ13と回路
基板2のパッド21の電気接触は保持される。
In the third part of the assembling step, the second part of the assembling step is performed.
To heat the assembly of the IC chip 1 and the circuit board 2.
By curing the adhesive 22, the IC chip 1 and the circuit board 2
Are fixed, and the electrical contact between the bumps 13 of the multi-stage structure of the IC chip 1 and the pads 21 of the circuit board 2 is maintained.

【0031】斯くして形成された多段構造のバンプ13
を有するフリップチップを用いたフリップチップアセン
ブリ3は、ICチップ1の該バンプ13に高さの不揃い
若しくは回路基板2の平面度に歪みが存在するものであ
っても、バンプ緩衝接続部分13bの垂直部位13yが
押圧により塑性変形して補正し、ICチップ1の電極1
1と回路基板2のパッド21の電気接続を確実にする。
図1−cは、垂直部位13yの変形による回路基板2の
歪み2zの補正を模式的に示したものである。
The bump 13 having a multi-stage structure thus formed
The flip-chip assembly 3 using the flip-chip having the above-mentioned structure has a structure in which the bumps 13 of the IC chip 1 are irregular in height or the flatness of the circuit board 2 is distorted. The portion 13y is plastically deformed by pressing and corrected, and the electrode 1 of the IC chip 1 is corrected.
1 and the electrical connection between the pads 21 of the circuit board 2 are ensured.
FIG. 1C schematically shows the correction of the distortion 2z of the circuit board 2 due to the deformation of the vertical portion 13y.

【0032】さらに、バンプ緩衝接続部分13bの水平
部位13xが回路基板2のパッド21に面接触するた
め、接触抵抗の低い安定した電気接続を得ることができ
る。
Further, since the horizontal portion 13x of the bump buffer connection portion 13b makes surface contact with the pad 21 of the circuit board 2, a stable electrical connection with low contact resistance can be obtained.

【0033】[0033]

【発明の効果】以上詳述したように本発明によれば、フ
リップチップと回路基板における従来技術の不完全性の
一面を示すバンプ高さの不揃いと回路基板の平面度の不
足を補い、接続信頼性の高い半導体装置を生産すること
ができる。また電気接続においても接触抵抗の低く安定
したものを得ることができる。さらに、本発明によるバ
ンプ高さの不揃いと回路基板の平面度を補う作用は、製
品の歩留まりを高めコストの低減に寄与することができ
る。本発明の特徴である多段構造のバンプは、従来のボ
ールボンディング法の工程を引き継いだ簡便な方法で形
成することができ、また本発明によるフリップチップア
センブリは接着剤を用いた簡便な方法で形成するもので
あり、特段の技術と設備を用いることなく本発明による
半導体装置を提供することができる。
As described above in detail, according to the present invention, the unevenness of bump height and the lack of flatness of the circuit board, which is one of the imperfections of the prior art, between the flip chip and the circuit board, are compensated for and the connection is made. A highly reliable semiconductor device can be manufactured. In addition, a stable connection with low contact resistance can be obtained in electrical connection. Furthermore, the effect of compensating for the uneven bump height and the flatness of the circuit board according to the present invention can contribute to increasing the yield of products and reducing costs. The bump having a multi-stage structure, which is a feature of the present invention, can be formed by a simple method that inherits the steps of the conventional ball bonding method, and the flip chip assembly according to the present invention can be formed by a simple method using an adhesive. Therefore, the semiconductor device according to the present invention can be provided without using any particular technology and equipment.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1は、多段構造のバンプを有するフリップチ
ップと、これを用いたフリップチップアセンブリの一実
施の形態を示した断面の模式図である。
FIG. 1 is a schematic cross-sectional view showing one embodiment of a flip chip having bumps of a multi-stage structure and a flip chip assembly using the flip chip.

【図2】図2は、多段構造のバンプを形成する過程の要
部を一実施の形態として示した断面の模式図である。
FIG. 2 is a schematic cross-sectional view showing, as an embodiment, a main part of a process of forming a bump having a multi-stage structure.

【図3】図3は、従来のボールボンディング法によるバ
ンプの形成を示した断面の模式図である。
FIG. 3 is a schematic cross-sectional view showing the formation of a bump by a conventional ball bonding method.

【図4】図4は、熱硬化性絶縁性の接着剤を用いたフリ
ップチップアセンブリの従来の組立方法を示した断面の
模式図である。
FIG. 4 is a schematic cross-sectional view showing a conventional method of assembling a flip chip assembly using a thermosetting insulating adhesive.

【符号の説明】[Explanation of symbols]

1 ICチップ 11 電極 12 バンプ 13 多層構造のバンプ 13a バンプ枢体部分 13b バンプ緩衝接続部分 13x バンプ緩衝接続部分13bの水平部位 13y バンプ緩衝接続部分13bの垂直部位 13z バンプ枢体部分13aの外縁上部付近 2 回路基板 2z 回路基板の歪み 21 パッド 22 熱硬化性絶縁性の接着剤 3 多段構造のバンプを有するフリップチップアセン
ブリ 4 ワイヤボンダ 41 キャピラリ 42 放電電極 43 クランパ 44 金属細線 44a 溶融部分
DESCRIPTION OF SYMBOLS 1 IC chip 11 Electrode 12 Bump 13 Multi-layer structure bump 13a Bump central part 13b Bump buffer connection part 13x Horizontal part of bump buffer connection part 13b 13y Vertical part of bump buffer connection part 13b 13z Near upper part of outer edge of bump central part 13a 2 Circuit Board 2z Distortion of Circuit Board 21 Pad 22 Thermosetting Insulating Adhesive 3 Flip Chip Assembly with Multi-Stage Bump 4 Wire Bonder 41 Capillary 42 Discharge Electrode 43 Clamper 44 Fine Metal Wire 44a Melted Part

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】フリップチップ構造のICチップであっ
て、ICチップの電極に接合したバンプ枢体部分と該バ
ンプ枢体部分から続く逆L字型のバンプ緩衝接続部分か
らなることを特徴とした多段構造のバンプを有するフリ
ップチップ。
1. An IC chip having a flip chip structure, comprising: a bump pivot portion joined to an electrode of the IC chip; and an inverted L-shaped bump buffer connection portion continuing from the bump pivot portion. Flip chip with multi-stage bumps.
【請求項2】請求項1記載のフリップチップを回路基板
に実装したアセンブリであって、前記フリップチップと
回路基板を熱硬化性絶縁性接着剤を用いて接合し、該フ
リップチップのバンプと回路基板の電極の接触を前記熱
硬化性絶縁性接着剤により保持したことを特徴とするフ
リップチップアセンブリ。
2. The assembly according to claim 1, wherein the flip chip is mounted on a circuit board, wherein the flip chip and the circuit board are joined using a thermosetting insulating adhesive. A flip chip assembly, wherein contact of electrodes on a substrate is held by the thermosetting insulating adhesive.
JP2000129183A 2000-04-28 2000-04-28 Flip chip having multistage bump and flip-chip assembly using the same Pending JP2001313307A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000129183A JP2001313307A (en) 2000-04-28 2000-04-28 Flip chip having multistage bump and flip-chip assembly using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000129183A JP2001313307A (en) 2000-04-28 2000-04-28 Flip chip having multistage bump and flip-chip assembly using the same

Publications (1)

Publication Number Publication Date
JP2001313307A true JP2001313307A (en) 2001-11-09

Family

ID=18638496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000129183A Pending JP2001313307A (en) 2000-04-28 2000-04-28 Flip chip having multistage bump and flip-chip assembly using the same

Country Status (1)

Country Link
JP (1) JP2001313307A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235887B2 (en) 2003-08-22 2007-06-26 Samsung Electronics Co., Ltd. Semiconductor package with improved chip attachment and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235887B2 (en) 2003-08-22 2007-06-26 Samsung Electronics Co., Ltd. Semiconductor package with improved chip attachment and manufacturing method thereof

Similar Documents

Publication Publication Date Title
US7064425B2 (en) Semiconductor device circuit board, and electronic equipment
US5960262A (en) Stitch bond enhancement for hard-to-bond materials
JP5366674B2 (en) Mounting structure and mounting method
US6921016B2 (en) Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
JP2003243436A (en) Bump forming method, bump attached semiconductor element and manufacturing method thereof, semiconductor device and manufacturing method thereof, substrate and electronic device
KR960006967B1 (en) Method for bonding lead with electrode of electronic device
JP2002280414A (en) Semiconductor device and its manufacturing method
JPH08264540A (en) Bump structure, method for forming bump and capillary being employed therein
WO2014077044A1 (en) Flip-chip bonding method and solid-state image pickup device manufacturing method characterized in including flip-chip bonding method
JPH09162230A (en) Electronic circuit device and its manufacturing method
JP2001313307A (en) Flip chip having multistage bump and flip-chip assembly using the same
JPH0799202A (en) Capillary for wire bonding device and method for forming electric connection bump using the same
JP3746719B2 (en) Flip chip mounting method
JP2001007155A (en) Flip chip connection structure body
JP2002016168A (en) Substrate for mounting and semiconductor module using the same
JPH06151440A (en) Semiconductor device, its manufacture, and its packaging body
JP2013093483A (en) Semiconductor device and manufacturing method of the same
JP2008091650A (en) Flip-chip packaging method and semiconductor package
JP2009032948A (en) Ic chip, and method of mounting ic chip
JPH08236575A (en) Semiconductor device and manufacturing method thereof
JP2002299374A (en) Semiconductor device and its manufacturing method
JP3389712B2 (en) IC chip bump forming method
JPH08186117A (en) Method for capillary and bump forming of wire bonding apparatus
JP2005150441A (en) Chip laminated semiconductor device and its manufacturing method
KR100237177B1 (en) Metal ball contact point of semiconductor chip and formation method thereof