JP4723312B2 - Semiconductor chip and semiconductor device - Google Patents

Semiconductor chip and semiconductor device Download PDF

Info

Publication number
JP4723312B2
JP4723312B2 JP2005241521A JP2005241521A JP4723312B2 JP 4723312 B2 JP4723312 B2 JP 4723312B2 JP 2005241521 A JP2005241521 A JP 2005241521A JP 2005241521 A JP2005241521 A JP 2005241521A JP 4723312 B2 JP4723312 B2 JP 4723312B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
bump
connection confirmation
bumps
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2005241521A
Other languages
Japanese (ja)
Other versions
JP2007059548A (en
Inventor
修 宮田
忠洋 森藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2005241521A priority Critical patent/JP4723312B2/en
Priority to KR1020087004282A priority patent/KR20080037681A/en
Priority to US11/990,875 priority patent/US8653657B2/en
Priority to PCT/JP2006/316264 priority patent/WO2007023747A1/en
Priority to TW095130993A priority patent/TW200721438A/en
Publication of JP2007059548A publication Critical patent/JP2007059548A/en
Application granted granted Critical
Publication of JP4723312B2 publication Critical patent/JP4723312B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)

Description

この発明は、チップ・オン・チップ構造やフリップ・チップ・ボンディング構造の半導体装置およびそのような半導体装置に用いられる半導体チップに関する。   The present invention relates to a semiconductor device having a chip-on-chip structure or a flip-chip bonding structure, and a semiconductor chip used in such a semiconductor device.

半導体装置の小型化および高集積化を図るための構造として、たとえば、半導体チップの表面を他の半導体チップの表面に対向させて接合するチップ・オン・チップ構造が知られている。
チップ・オン・チップ構造の半導体装置では、各半導体チップの表面に、多数の機能バンプおよび接続確認用バンプが設けられる。たとえば、各半導体チップの表面において、その中央部に多数の機能バンプが格子状に配列され、４つの角部に接続確認用バンプが配置される。 As a structure for reducing the size and integration of a semiconductor device, for example, a chip-on-chip structure in which a surface of a semiconductor chip is bonded to a surface of another semiconductor chip is known.
In a semiconductor device having a chip-on-chip structure, a large number of functional bumps and connection confirmation bumps are provided on the surface of each semiconductor chip. For example, on the surface of each semiconductor chip, a large number of functional bumps are arranged in a grid at the center, and connection confirmation bumps are arranged at four corners.

各半導体チップにおいて、機能バンプは、銅（Ｃｕ）などの金属材料を用いて、すべて同じ高さ（半導体チップの表面からの突出量）に形成されている。また、一方の半導体チップの各機能バンプの先端部には、機能バンプの材料と合金化をなし得るはんだ接合材が形成されている。このはんだ接合材を介して、一方の半導体チップの各機能バンプと他方の半導体チップの各機能バンプとが接続されることにより、半導体チップ間における電気的および機械的な接続が達成される。   In each semiconductor chip, the functional bumps are all formed at the same height (amount of protrusion from the surface of the semiconductor chip) using a metal material such as copper (Cu). Also, a solder bonding material that can be alloyed with the material of the functional bump is formed at the tip of each functional bump of one semiconductor chip. By connecting each functional bump of one semiconductor chip and each functional bump of the other semiconductor chip via this solder bonding material, electrical and mechanical connection between the semiconductor chips is achieved.

一方、各半導体チップにおいて、接続確認用バンプは、機能バンプと同じ金属材料を用いて、機能バンプと同じ高さ（半導体チップの表面からの突出量）に形成されている。また、一方の半導体チップの各接続確認用バンプの先端部には、はんだ接合材が形成されている。これにより、両半導体チップが互いに平行に接合された場合には、一方の半導体チップの各接続確認用バンプと他方の半導体チップの各接続確認用バンプとがはんだ接合材を介して接続される。したがって、それらの接続確認用バンプ間の接続状態を調べることにより、両半導体チップが互いに平行に接合されているか否かを判定することができる。すなわち、すべての接続確認用バンプ間の接続状態が良好であれば、両半導体チップは互いに平行に接合されていると判定することができる。一方、接続確認用バンプの接続状態が１つでも不良であれば、両半導体チップが互いに平行に接合されていない（一方の半導体チップが他方の半導体チップに対して傾いて接合されている）と判定することができる。
特開平８−１５３７４７号公報 On the other hand, in each semiconductor chip, the connection confirmation bumps are formed using the same metal material as that of the functional bumps and have the same height as the functional bumps (a protruding amount from the surface of the semiconductor chip). Also, a solder bonding material is formed at the tip of each connection confirmation bump of one semiconductor chip. Thereby, when both semiconductor chips are bonded in parallel to each other, each connection confirmation bump of one semiconductor chip and each connection confirmation bump of the other semiconductor chip are connected via the solder bonding material. Therefore, it is possible to determine whether or not both semiconductor chips are joined in parallel by examining the connection state between these connection confirmation bumps. That is, if the connection state between all the connection confirmation bumps is good, it can be determined that the two semiconductor chips are bonded in parallel to each other. On the other hand, if even one connection confirmation bump is in a poor connection state, the two semiconductor chips are not bonded in parallel to each other (one semiconductor chip is inclined and bonded to the other semiconductor chip). Can be determined.
JP-A-8-153747

ところが、従来の構成では、一方の半導体チップが他方の半導体チップに対して多少傾いた状態で接合されても、接続確認用バンプの先端部のはんだ接合材が熱処理時に溶融して膨張することにより、両半導体チップのすべての接続確認用バンプが接続されるという不具合を生じることがあった。この場合、一方の半導体チップが他方の半導体チップに対して傾いて接合されているにもかかわらず、両半導体チップが互いに平行に接合されていると判断されてしまう。   However, in the conventional configuration, even when one semiconductor chip is bonded to the other semiconductor chip in a slightly inclined state, the solder bonding material at the tip of the connection confirmation bump melts and expands during heat treatment. In some cases, all the connection confirmation bumps of both semiconductor chips are connected. In this case, it is determined that both semiconductor chips are bonded in parallel to each other even though one semiconductor chip is inclined and bonded to the other semiconductor chip.

そこで、この発明の目的は、半導体チップが他の半導体チップなどの固体装置に対して平行に接合されているか否かを正確に判定することができる半導体チップおよび半導体装置を提供することである。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor chip and a semiconductor device that can accurately determine whether or not a semiconductor chip is bonded in parallel to a solid-state device such as another semiconductor chip.

上記の目的を達成するための請求項１記載の発明は、固体装置にその表面を対向させた状態で接合される半導体チップであって、前記表面から突出して形成されて、前記固体装置との電気接続のための機能バンプと、前記機能バンプによる電気接続の状態を確認するための複数の接続確認用バンプと、前記半導体チップに設けられた前記機能バンプと前記固体装置に設けられた固体装置側機能バンプとの間、および前記半導体チップに設けられた前記複数の接続確認用バンプの各々と前記固体装置に設けられた対応する固体装置側接続確認用バンプとの間にそれぞれ介在され、それらの間の接続を達成するための接続金属層とを含み、前記半導体チップに設けられた前記機能バンプおよび前記接続確認用バンプは、同じ金属材料を用いて形成されており、前記半導体チップに設けられた前記接続確認用バンプの前記表面からの突出量は、前記機能バンプの前記表面からの突出量よりも小さく、前記接続確認用バンプの前記突出量は、前記固体装置と前記半導体チップとを接続する熱処理時に、前記固体装置と前記半導体チップとが平行である場合に、前記複数の接続確認用バンプのすべてについて、対応する前記接続金属層が溶融膨張して対応する前記固体装置側接続確認用バンプに接続される突出量であることを特徴とする。 In order to achieve the above object, the invention according to claim 1 is a semiconductor chip bonded to a solid state device in a state where the surface of the solid state device is opposed to the solid state device. a function bumps for electrical connection, before Symbol function and a plurality of connection confirmation bumps for confirming the state of the electrical connection by the bumps, the provided and the functional bump formed on the semiconductor chip to the solid state device solid Between the device-side functional bumps and between each of the plurality of connection confirmation bumps provided on the semiconductor chip and the corresponding solid device-side connection confirmation bumps provided on the solid device, respectively. A connection metal layer for achieving a connection between them, and the functional bump and the connection confirmation bump provided on the semiconductor chip are formed using the same metal material. The amount of protrusion of the connection confirmation bump provided on the semiconductor chip from the surface is smaller than the amount of protrusion of the functional bump from the surface, and the amount of protrusion of the connection confirmation bump is: When the solid state device and the semiconductor chip are parallel during the heat treatment for connecting the solid state device and the semiconductor chip, the corresponding connection metal layer is melted and expanded for all of the plurality of connection confirmation bumps. The protrusion amount connected to the corresponding solid device side connection confirmation bump .

この構成では、接続確認用バンプが機能バンプよりも低く形成されているので、半導体チップの表面が固体装置に対して少しでも傾いていると、固体装置と半導体チップの表面との間隔が広い部分において、固体装置において接続確認用バンプが接続される部分（たとえば、固体装置の表面に配置されたパッドまたはバンプ）と接続確認用バンプの先端部との間に広い隙間が生じる。そのため、接続確認用バンプと固体装置とが接続確認用バンプに形成された接合材を介して接合される場合に、接合材が膨張しても、その接合材は固体装置に届かず、接続確認用バンプと固体装置との接続が達成されない。よって、接続確認用バンプと固体装置との接続状態に基づいて、半導体チップが固体装置に対して平行に接合されているか否かを正確に判定することができる。   In this configuration, since the connection confirmation bump is formed lower than the functional bump, if the surface of the semiconductor chip is slightly inclined with respect to the solid-state device, the portion where the distance between the solid-state device and the surface of the semiconductor chip is wide In the solid state device, a wide gap is formed between a portion (for example, a pad or a bump disposed on the surface of the solid state device) to which the connection confirmation bump is connected and the tip of the connection confirmation bump. Therefore, when the connection confirmation bump and the solid device are bonded via the bonding material formed on the connection confirmation bump, even if the bonding material expands, the bonding material does not reach the solid device, and the connection confirmation The connection between the industrial bump and the solid state device is not achieved. Therefore, based on the connection state between the connection confirmation bump and the solid state device, it can be accurately determined whether or not the semiconductor chip is bonded in parallel to the solid state device.

請求項２記載の発明は、第１の半導体チップと第２の半導体チップとを前記第１の半導体チップの表面に前記第２の半導体チップの表面を対向させた状態で接合した、チップ・オン・チップ構造を有する半導体装置であって、前記第１の半導体チップの表面から突出して形成された第１半導体チップ側機能バンプと、前記第１の半導体チップの表面から突出して形成された複数の第１半導体チップ側接続確認用バンプと、前記第２の半導体チップの表面から突出して形成され、前記第１半導体チップ側機能バンプに接続されて、前記第１の半導体チップと前記第２の半導体チップとの電気接続を達成するための第２半導体チップ側機能バンプと、前記第２の半導体チップの表面からの前記第２半導体チップ側機能バンプの突出量よりも小さい突出量で、前記第２の半導体チップの表面から突出して形成され、前記複数の第１半導体チップ側接続確認用バンプとそれぞれ接続されて、前記第１の半導体チップと前記第２の半導体チップとの電気接続の状態を確認するための複数の第２半導体チップ側接続確認用バンプと、前記第１半導体チップ側機能バンプと前記第２半導体チップ側機能バンプとの間、および前記第１半導体チップ側接続確認用バンプと前記第２半導体チップ側接続確認用バンプとの間にそれぞれ介在され、それらの間の接続を達成するための接続金属層とを含み、前記第１半導体チップ側機能バンプ、前記第２半導体チップ側機能バンプ、前記第１半導体チップ側接続確認用バンプおよび前記第２半導体チップ側接続確認用バンプは、同じ金属材料を用いて形成されており、前記第２半導体チップ側接続確認用バンプの前記突出量は、前記第１の半導体チップと前記第２の半導体チップとを接続する熱処理時に、前記第１の半導体チップと前記第２の半導体チップとが平行である場合に、前記複数の第２半導体チップ側接続確認用バンプのすべてについて、対応する前記接続金属層が溶融膨張して対応する前記第１半導体チップ側接続確認用バンプに接続される突出量であることを特徴とする。 According to a second aspect of the present invention, there is provided a chip-on device in which the first semiconductor chip and the second semiconductor chip are joined to the surface of the first semiconductor chip with the surface of the second semiconductor chip facing each other. A semiconductor device having a chip structure, the first semiconductor chip-side functional bumps protruding from the surface of the first semiconductor chip, and a plurality of protrusions formed protruding from the surface of the first semiconductor chip; A first semiconductor chip side connection confirmation bump and a bump protruding from the surface of the second semiconductor chip, connected to the first semiconductor chip side functional bump, and connected to the first semiconductor chip and the second semiconductor. a second semiconductor chip side functions bumps to achieve electrical connection between the chip smaller than the projecting amount of the second semiconductor chip side functions bumps from the surface of the second semiconductor chip In discharge amount, the formed protruding from the surface of the second semiconductor chip, respectively connected with said plurality of first semiconductor chip side connection confirmation bumps, the first semiconductor chip and said second semiconductor chip A plurality of second semiconductor chip side connection confirmation bumps for confirming the state of electrical connection of the first semiconductor chip, between the first semiconductor chip side functional bump and the second semiconductor chip side functional bump, and the first semiconductor chip are each interposed between the the side connection confirmation bumps second semiconductor chip side connection confirmation bumps, and a connection metal layer in order to achieve connection therebetween seen including, the first semiconductor chip side functions bumps The second semiconductor chip side functional bump, the first semiconductor chip side connection confirmation bump, and the second semiconductor chip side connection confirmation bump are formed using the same metal material. The protrusion amount of the second semiconductor chip side connection confirmation bump is determined by the first semiconductor chip and the second semiconductor chip during the heat treatment for connecting the first semiconductor chip and the second semiconductor chip. When the semiconductor chip is parallel to all of the plurality of second semiconductor chip side connection confirmation bumps, the corresponding connection metal layer melts and expands to correspond to the first semiconductor chip side connection confirmation bumps. It is the amount of protrusions to be connected .

この構成では、第２半導体チップ側接続確認用バンプが第２半導体チップ側機能バンプよりも低く形成されているので、第２の半導体チップの表面が第１の半導体チップの表面に対して少しでも傾いていると、第１の半導体チップの表面と第２の半導体チップの表面との間隔が広い部分において、互いに対向する第１半導体チップ側接続確認用バンプと第２半導体チップ側接続確認用バンプとの間に広い隙間が生じる。そのため、それらの接続確認用バンプが一方の接続確認用バンプに形成された接合材を介して接合される場合に、接合材が膨張しても、その接合材は他方の接続確認用バンプに届かず、第１半導体チップ側接続確認用バンプと第２半導体チップ側接続確認用バンプとの間の接続が達成されない。よって、第１半導体チップ側接続確認用バンプと第２半導体チップ側接続確認用バンプとの間の接続状態に基づいて、第２の半導体チップが第１の半導体チップに対して平行に接合されているか否かを正確に判定することができる。   In this configuration, the second semiconductor chip-side connection confirmation bump is formed lower than the second semiconductor chip-side functional bump, so that the surface of the second semiconductor chip is slightly above the surface of the first semiconductor chip. If it is inclined, the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump that face each other in a portion where the distance between the surface of the first semiconductor chip and the surface of the second semiconductor chip is wide. A wide gap is formed between the two. Therefore, when these connection confirmation bumps are bonded via the bonding material formed on one connection confirmation bump, even if the bonding material expands, the bonding material reaches the other connection confirmation bump. Therefore, the connection between the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump is not achieved. Therefore, the second semiconductor chip is bonded in parallel to the first semiconductor chip based on the connection state between the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump. It can be accurately determined whether or not.

前記第１半導体チップ側機能バンプ、前記第２半導体チップ側機能バンプ、前記第１半導体チップ側接続確認用バンプおよび前記第２半導体チップ側接続確認用バンプが銅または金からなる場合、前記接続金属層は、前記第１半導体チップ側機能バンプおよび前記第１半導体チップ側接続確認用バンプ、ならびに／または、前記第２半導体チップ側機能バンプおよび前記第２半導体チップ側接続確認用バンプの頂面に設けられたはんだ接合材により形成されてもよい。 When the first semiconductor chip side functional bump, the second semiconductor chip side functional bump, the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump are made of copper or gold, the connection metal The layer is formed on the top surface of the first semiconductor chip side functional bump and the first semiconductor chip side connection confirmation bump, and / or the second semiconductor chip side functional bump and the second semiconductor chip side connection confirmation bump. it may be formed by solder joint material provided.

請求項３記載の発明は、請求項２記載の半導体装置において、前記第２の半導体チップは、その表面を垂直に見下ろしたときの形状が略矩形状をなしており、前記第２半導体チップ側機能バンプは、前記第２の半導体チップの表面の中央部に配置され、前記第２半導体チップ側接続確認用バンプは、前記第２の半導体チップの表面の各角部に配置されていることを特徴とする。 According to a third aspect of the invention, in the semiconductor device according to claim 2 Symbol placement, the second semiconductor chip has a substantially rectangular shape when viewed down the surface perpendicularly, the second semiconductor chip The side function bumps are arranged at the center of the surface of the second semiconductor chip, and the second semiconductor chip side connection confirmation bumps are arranged at each corner of the surface of the second semiconductor chip. It is characterized by.

この構成によれば、第２の半導体チップの表面の各角部に、第２半導体チップ側接続確認用バンプが配置されている。そのため、第２の半導体チップの表面が第１の半導体チップの表面に対して傾いていると、少なくとも１組の第１半導体チップ側接続確認用バンプと第２半導体チップ側接続確認用バンプとの間に広い隙間が生じる。よって、第１半導体チップ側接続確認用バンプと第２半導体チップ側接続確認用バンプとの間の接続状態に基づいて、第２の半導体チップが第１の半導体チップに対して平行に接合されているか否かをより正確に判定することができる。   According to this configuration, the second semiconductor chip side connection confirmation bumps are arranged at each corner of the surface of the second semiconductor chip. Therefore, when the surface of the second semiconductor chip is inclined with respect to the surface of the first semiconductor chip, at least one set of the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump is formed. A wide gap is created between them. Therefore, the second semiconductor chip is bonded in parallel to the first semiconductor chip based on the connection state between the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump. It can be determined more accurately whether or not.

なお、第２半導体チップ側接続確認用バンプが第２半導体チップ側機能バンプよりも低く形成されているだけでなく、請求項４に記載のように、前記第１半導体チップ側接続確認用バンプも、前記第１の半導体チップの表面からの前記第１半導体チップ側機能バンプの突出量よりも小さい突出量で、前記第１の半導体チップの表面から突出して形成されていてもよい。 Note that the second semiconductor chip side connection confirmation bumps well is formed lower than the second semiconductor chip side functions bumps, as claimed in claim 4, wherein the first semiconductor chip side connection confirmation bumps Alternatively, the protrusion may be formed so as to protrude from the surface of the first semiconductor chip with a protrusion amount smaller than the protrusion amount of the first semiconductor chip-side functional bump from the surface of the first semiconductor chip.

以下では、この発明の実施の形態を、添付図面を参照して詳細に説明する。
図１は、この発明の一実施形態に係る半導体装置の構成を示す図解的な断面図である。
この半導体装置は、第１の半導体チップとしての親チップ１と第２の半導体チップとしての子チップ２とを重ね合わせて接合したチップ・オン・チップ構造を有している。
親チップ１は、平面視略矩形状に形成されており、その表面（デバイスが形成された活性領域側表面）３を上方に向けたフェイスアップ姿勢で、リードフレーム４のアイランド部５にダイボンディングされている。この親チップ１の表面３には、その中央部に、子チップ２が接合される略矩形状のチップ接合領域が設定されている。そして、チップ接合領域内に、複数の機能バンプ６が突出（隆起）して形成されている。また、チップ接合領域内の各角部には、接続確認用バンプ７が突出して形成されている。さらに、親チップ１の表面３には、チップ接合領域を取り囲む周縁部に、複数の外部接続用パッド８が設けられている。この外部接続用パッド８は、ボンディングワイヤ９を介して、リードフレーム４のリード部１０に電気的に接続（ワイヤボンディング）されている。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.
This semiconductor device has a chip-on-chip structure in which a parent chip 1 as a first semiconductor chip and a child chip 2 as a second semiconductor chip are overlapped and joined.
The parent chip 1 is formed in a substantially rectangular shape in plan view, and is die-bonded to the island portion 5 of the lead frame 4 in a face-up posture with its surface (active region side surface on which the device is formed) 3 facing upward. Has been. On the surface 3 of the parent chip 1, a substantially rectangular chip bonding area to which the child chip 2 is bonded is set at the center. A plurality of functional bumps 6 are formed to protrude (protrude) in the chip bonding region. In addition, connection confirmation bumps 7 are formed to protrude at each corner in the chip bonding region. Furthermore, a plurality of external connection pads 8 are provided on the surface 3 of the parent chip 1 at the peripheral edge surrounding the chip bonding region. The external connection pads 8 are electrically connected (wire bonded) to the lead portions 10 of the lead frame 4 via bonding wires 9.

子チップ２は、平面視において親チップ１よりも小さな略矩形状に形成されており、その表面（デバイスが形成された活性領域側表面）１１を下方に向けたフェイスダウン姿勢で、親チップ１の表面３のチップ接合領域に接合されている。この子チップ２の表面１１には、親チップ１の機能バンプ６とそれぞれ接続される機能バンプ１２が突出して形成されている。また、子チップ２の表面１１の各角部には、親チップ１の接続確認用バンプ７とそれぞれ接続される接続確認用バンプ１３が突出して形成されている。   The child chip 2 is formed in a substantially rectangular shape smaller than the parent chip 1 in a plan view, and in a face-down posture with its surface (active region side surface on which a device is formed) 11 facing downward, Are bonded to the chip bonding region of the surface 3 of the substrate. On the surface 11 of the child chip 2, functional bumps 12 connected to the functional bumps 6 of the parent chip 1 are formed so as to protrude. Further, connection confirmation bumps 13 respectively connected to the connection confirmation bumps 7 of the parent chip 1 protrude from the corners of the surface 11 of the child chip 2.

親チップ１と子チップ２とが接合された状態で、親チップ１の機能バンプ６および接続確認用バンプ７とこれらにそれぞれ対応する子チップ２の機能バンプ１２および接続確認用バンプ１３とは、互いに頂面を突き合わせて対向し、それらの間に介在される接続金属層１４を挟んで接続されている。これにより、親チップ１および子チップ２は、機能バンプ６，１２を介して、電気的に接続され、かつ、互いの間に所定間隔を保った状態で機械的に接続されている。また、親チップ１および子チップ２は、リードフレーム４およびボンディングワイヤ９とともに、封止樹脂１５により封止されている。リードフレーム４のリード部１０の一部は、封止樹脂１５から露出し、外部接続部（アウターリード部）として機能する。   In a state where the parent chip 1 and the child chip 2 are joined, the functional bump 6 and the connection confirmation bump 7 of the parent chip 1 and the functional bump 12 and the connection confirmation bump 13 of the child chip 2 corresponding to these, respectively, The top faces are opposed to each other and are opposed to each other, and are connected via a connection metal layer 14 interposed therebetween. Thereby, the parent chip 1 and the child chip 2 are electrically connected via the functional bumps 6 and 12 and mechanically connected with a predetermined interval between them. The parent chip 1 and the child chip 2 are sealed with a sealing resin 15 together with the lead frame 4 and the bonding wires 9. A part of the lead part 10 of the lead frame 4 is exposed from the sealing resin 15 and functions as an external connection part (outer lead part).

図２は、機能バンプ６，１２の接続部分および接続確認用バンプ７，１３の接続部分を図解的に示す断面図である。
親チップ１において、機能バンプ６は、銅（Ｃｕ）または金（Ａｕ）などの金属材料を用いて、すべて同じ高さ（親チップ１の表面３からの突出量）に形成されている。また、接続確認用バンプ７は、機能バンプ６と同じ材料を用いて、機能バンプ６と同じ高さに形成されている。 FIG. 2 is a cross-sectional view schematically showing the connection portions of the functional bumps 6 and 12 and the connection portions of the connection confirmation bumps 7 and 13.
In the parent chip 1, the functional bumps 6 are all formed at the same height (a protruding amount from the surface 3 of the parent chip 1) using a metal material such as copper (Cu) or gold (Au). Further, the connection confirmation bump 7 is formed at the same height as the functional bump 6 by using the same material as that of the functional bump 6.

一方、子チップ２において、機能バンプ１２は、親チップ１の機能バンプ６と同じ材料を用いて、すべて同じ高さ（子チップ２の表面１１からの突出量）に形成されている。また、接続確認用バンプ１３は、機能バンプ１２と同じ材料（親チップ１の機能バンプ６と同じ材料）を用いて、機能バンプ１２よりも１〜５μｍ（好ましくは、１〜２μｍ）だけ低く（子チップ２の表面１１からの突出量が小さく）形成されている。   On the other hand, in the child chip 2, the functional bumps 12 are all formed at the same height (the protruding amount from the surface 11 of the child chip 2) using the same material as the functional bumps 6 of the parent chip 1. Further, the connection confirmation bump 13 is made of the same material as the functional bump 12 (the same material as the functional bump 6 of the parent chip 1), and is 1-5 μm (preferably 1-2 μm) lower than the functional bump 12 ( The protrusion amount from the surface 11 of the child chip 2 is small).

図２（ａ）に示すように、親チップ１と子チップ２との接合前の状態において、子チップ２の機能バンプ１２および接続確認用バンプ１３の先端部には、はんだ接合材１６が形成されている。
機能バンプ１２と接続確認用バンプ１３との高さの違いにより、親チップ１と子チップ２とが接合される過程において、機能バンプ１２の先端部のはんだ接合材１６が親チップ１の機能バンプ６の頂面に接触した時点で、接続確認用バンプ１３の先端部のはんだ接合材１６と親チップ１の接続確認用バンプ７の頂面との間に隙間Ｄが生じる。 As shown in FIG. 2A, in a state before the parent chip 1 and the child chip 2 are joined, the solder bonding material 16 is formed at the tip ends of the functional bumps 12 and the connection confirmation bumps 13 of the child chip 2. Has been.
Due to the difference in height between the functional bump 12 and the connection confirmation bump 13, the solder bonding material 16 at the tip of the functional bump 12 is bonded to the functional bump of the parent chip 1 in the process of bonding the parent chip 1 and the child chip 2. 6, a gap D is formed between the solder bonding material 16 at the tip of the connection confirmation bump 13 and the top surface of the connection confirmation bump 7 of the parent chip 1.

親チップ１の表面３と子チップ２の表面１１とが互いに平行であれば、すべての接続確認用バンプ１３の先端部のはんだ接合材１６と接続確認用バンプ７の頂面との間の隙間Ｄは、機能バンプ１２と接続確認用バンプ１３との高さの差に相当する間隔となる。したがって、その後に熱処理が行われると、接続確認用バンプ１３の先端部のはんだ接合材１６が溶融して膨張し、そのはんだ接合材１６により、すべての接続確認用バンプ７，１３間が接続される。そして、図２（ｂ）に示すように、互いに対向する各機能バンプ６，１２間および各接続確認用バンプ７，１３間のはんだ接合材１６が接続金属層１４となって、それらの各間の良好な接続（導通）が達成される。   If the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 are parallel to each other, the gap between the solder bonding material 16 at the tip of all the connection confirmation bumps 13 and the top surfaces of the connection confirmation bumps 7 D is an interval corresponding to the difference in height between the functional bump 12 and the connection confirmation bump 13. Therefore, when heat treatment is subsequently performed, the solder joint material 16 at the tip of the connection confirmation bump 13 melts and expands, and the connection joint bumps 7 and 13 are connected by the solder joint material 16. The Then, as shown in FIG. 2B, the solder bonding material 16 between the functional bumps 6 and 12 facing each other and between the bumps 7 and 13 for connection confirmation becomes the connection metal layer 14, Good connection (conduction) is achieved.

一方、子チップ２の表面１１が親チップ１の表面３に対して傾いていると、親チップ１の表面３と子チップ２の表面１１との間隔が広い部分と狭い部分とが生じ、接続確認用バンプ１３の先端部のはんだ接合材１６と接続確認用バンプ７の頂面との間の隙間Ｄに広狭が生じる。そして、親チップ１の表面３と子チップ２の表面１１との間隔が広い部分では、接続確認用バンプ１３の先端部のはんだ接合材１６と接続確認用バンプ７の頂面との間の隙間Ｄの間隔が、機能バンプ１２と接続確認用バンプ１３との高さの差よりも広くなる。そのため、はんだ接合材１６の量が適当な一定量であれば、親チップ１の表面３と子チップ２の表面１１との間隔が広い部分において、熱処理時に接続確認用バンプ１３の先端部のはんだ接合材１６が膨張しても、そのはんだ接合材１６が接続確認用バンプ７の頂面に届かず、接続確認用バンプ７，１３間の接続が達成されない。   On the other hand, if the surface 11 of the child chip 2 is tilted with respect to the surface 3 of the parent chip 1, a portion where the distance between the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 is wide and a portion narrow are generated. The gap D between the solder bonding material 16 at the tip of the confirmation bump 13 and the top surface of the connection confirmation bump 7 is wide or narrow. In a portion where the distance between the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 is wide, a gap between the solder bonding material 16 at the tip of the connection confirmation bump 13 and the top surface of the connection confirmation bump 7. The interval of D becomes wider than the difference in height between the functional bump 12 and the connection confirmation bump 13. Therefore, if the amount of the solder bonding material 16 is an appropriate fixed amount, the solder at the tip of the connection confirmation bump 13 during heat treatment in a portion where the distance between the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 is wide. Even if the bonding material 16 expands, the solder bonding material 16 does not reach the top surface of the connection confirmation bump 7 and the connection between the connection confirmation bumps 7 and 13 is not achieved.

したがって、すべての接続確認用バンプ７，１３間の接続が達成されていれば、子チップ２が親チップ１に対して平行に接合されていると判定することができ、いずれか１組の接続確認用バンプ７，１３間の接続が達成されていなければ、子チップ２が親チップ１に対して傾いて接合されている（平行に接合されていない）と判定することができる。
従来の構成と同様に、親チップ１の接続確認用バンプ７が機能バンプ６と同じ高さに形成され、子チップ２の接続確認用バンプ１３が機能バンプ１２と同じ高さに形成されている場合、子チップ２が親チップ１に対して傾いて接合されても、親チップ１の表面３と子チップ２の表面１１との間隔が広い部分において、接続確認用バンプ１３の先端部のはんだ接合材１６と接続確認用バンプ７の頂面との間に生じる隙間は僅かである。そのため、はんだ接合材１６が溶融して膨張すると、そのはんだ接合材１６が接続確認用バンプ７の頂面に達し、接続確認用バンプ７，１３間の接続が達成されてしまう。 Therefore, if the connection between all the connection confirmation bumps 7 and 13 is achieved, it can be determined that the child chip 2 is bonded in parallel to the parent chip 1, and any one set of connections If the connection between the confirmation bumps 7 and 13 is not achieved, it can be determined that the child chip 2 is inclined and bonded to the parent chip 1 (not bonded in parallel).
As in the conventional configuration, the connection confirmation bump 7 of the parent chip 1 is formed at the same height as the function bump 6, and the connection confirmation bump 13 of the child chip 2 is formed at the same height as the function bump 12. In this case, even if the child chip 2 is inclined and joined to the parent chip 1, the solder at the tip of the connection confirmation bump 13 in a portion where the distance between the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 is wide There is only a small gap between the bonding material 16 and the top surface of the connection confirmation bump 7. Therefore, when the solder joint material 16 melts and expands, the solder joint material 16 reaches the top surface of the connection confirmation bump 7, and the connection between the connection confirmation bumps 7 and 13 is achieved.

これに対し、この実施形態の構成では、子チップ２の接続確認用バンプ１３が機能バンプ１２よりも低く形成されているので、子チップ２の表面１１が親チップ１の表面３に対して少しでも傾いていると、親チップ１の表面３と子チップ２の表面１１との間隔が広い部分において、接続確認用バンプ１３の先端部のはんだ接合材１６と接続確認用バンプ７の頂面との間に広い隙間が生じる。そのため、はんだ接合材１６が膨張しても、そのはんだ接合材１６が接続確認用バンプ７の頂面に届かず、接続確認用バンプ７，１３間の接続が達成されない。よって、子チップ２が親チップ１に対して平行に接合されているか否かを正確に判定することができる。   On the other hand, in the configuration of this embodiment, the connection confirmation bumps 13 of the child chip 2 are formed lower than the functional bumps 12, so that the surface 11 of the child chip 2 is slightly smaller than the surface 3 of the parent chip 1. However, if it is inclined, the solder bonding material 16 at the tip of the connection confirmation bump 13 and the top surface of the connection confirmation bump 7 are formed at a portion where the distance between the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 is wide. A wide gap is formed between the two. Therefore, even if the solder bonding material 16 expands, the solder bonding material 16 does not reach the top surface of the connection confirmation bump 7, and the connection between the connection confirmation bumps 7 and 13 is not achieved. Therefore, it can be accurately determined whether or not the child chip 2 is bonded in parallel to the parent chip 1.

なお、高さの異なる機能バンプ１２および接続確認用バンプ１３は、それぞれ別工程で形成してもよいし、２段バンプ形成法により形成してもよい。すなわち、機能バンプ１２および接続確認用バンプ１３の一方を先に形成し、他方を次に形成してもよい。また、機能バンプ１２および接続確認用バンプ１３を形成すべき各位置に、接続確認用バンプ１３の高さに応じた高さに金属材料を選択的に堆積させ、その後、機能バンプ１２を形成すべき位置のみに、さらに金属材料を選択的に堆積させることにより、機能バンプ１２および接続確認用バンプ１３を形成してもよい。   The functional bumps 12 and the connection confirmation bumps 13 having different heights may be formed in separate steps, or may be formed by a two-step bump formation method. That is, one of the functional bump 12 and the connection confirmation bump 13 may be formed first, and the other may be formed next. Further, a metal material is selectively deposited at a position corresponding to the height of the connection confirmation bump 13 at each position where the functional bump 12 and the connection confirmation bump 13 are to be formed, and then the functional bump 12 is formed. The functional bumps 12 and the connection confirmation bumps 13 may be formed by selectively depositing a metal material only at the power position.

以上、この発明の一実施形態を説明したが、この発明は他の形態で実施することもできる。たとえば、上述の実施形態では、子チップ２において、接続確認用バンプ１３が機能バンプ１２よりも低く形成されているとしたが、図３に示すように、親チップ１においても、接続確認用バンプ７が機能バンプ６よりも低く形成されてもよい。この場合、図３（ａ）に示すように、接続確認用バンプ７，１３は、親チップ１と子チップ２とが接合される過程において、機能バンプ１２の先端部のはんだ接合材１６が親チップ１の機能バンプ６の頂面に接触した時点で、接続確認用バンプ１３の先端部のはんだ接合材１６と親チップ１の接続確認用バンプ７の頂面との間に、１〜５μｍ（好ましくは、１〜２μｍ）の隙間Ｄが生じるような高さにそれぞれ形成されるとよい。このように形成すれば、図３（ｂ）に示すように、親チップ１の表面３と子チップ２の表面１１とが互いに平行であれば、互いに対向する各機能バンプ６，１２間および各接続確認用バンプ７，１３間のはんだ接合材１６が接続金属層１４となって、それらの各間の良好な接続が達成される。   Although one embodiment of the present invention has been described above, the present invention can be implemented in other forms. For example, in the above-described embodiment, the connection confirmation bump 13 is formed lower than the functional bump 12 in the child chip 2, but the connection confirmation bump is also formed in the parent chip 1 as shown in FIG. 3. 7 may be formed lower than the functional bump 6. In this case, as shown in FIG. 3 (a), the connection confirmation bumps 7 and 13 are formed so that the solder bonding material 16 at the tip of the functional bump 12 becomes the parent bump in the process in which the parent chip 1 and the child chip 2 are bonded. 1 to 5 μm (between the solder bonding material 16 at the tip of the connection confirmation bump 13 and the top surface of the connection confirmation bump 7 of the parent chip 1 when it contacts the top surface of the functional bump 6 of the chip 1. Preferably, it may be formed at a height such that a gap D of 1 to 2 μm is generated. If formed in this way, as shown in FIG. 3 (b), if the surface 3 of the parent chip 1 and the surface 11 of the child chip 2 are parallel to each other, the functional bumps 6, 12 facing each other and each The solder joint material 16 between the connection confirmation bumps 7 and 13 becomes the connection metal layer 14, and a good connection between them is achieved.

また、子チップ２において、機能バンプ１２と接続確認用バンプ１３とが同じ高さに形成され、親チップ１において、接続確認用バンプ７が機能バンプ６よりも低く形成されてもよい。すなわち、この実施形態では、親チップ１および子チップ２をそれぞれ第１の半導体チップおよび第２の半導体チップとしたが、親チップ１を第２の半導体チップとし、子チップ２を第１の半導体チップとしてもよい。   Further, in the child chip 2, the functional bump 12 and the connection confirmation bump 13 may be formed at the same height, and in the parent chip 1, the connection confirmation bump 7 may be formed lower than the functional bump 6. That is, in this embodiment, the parent chip 1 and the child chip 2 are the first semiconductor chip and the second semiconductor chip, respectively, but the parent chip 1 is the second semiconductor chip and the child chip 2 is the first semiconductor chip. A chip may be used.

さらにまた、接続確認用バンプ７，１３は、それぞれ親チップ１および子チップ２の内部回路と接続されていてもよいし、それぞれ親チップ１および子チップ２の内部回路から電気的に切り離されていてもよい。接続確認用バンプ７，１３が内部回路から切り離される場合、図４に示すように、親チップ１において、チップ接合領域の各角部に２個１組の接続確認用バンプ７が配置されるとともに、チップ接合領域外に各接続確認用バンプ７と電気的に接続された外部取出用電極１７が設けられる。一方、子チップ２において、各角部に２個１組の接続確認用バンプ１３が配置されるとともに、その２個１組の接続確認用バンプ１３が互いに電気的に接続される。これにより、親チップ１と子チップ２とが平行をなして接合されると、各組の接続確認用バンプ７，１３の間が接続されて、各組の外部取出用電極１７間が短絡されるので、これらの間の電気抵抗が小さくなる。一方、子チップ２が親チップ１に対して傾いて接合されると、それらの表面間の間隔が広い部分において、接続確認用バンプ７，１３の接続が達成されず、外部取出用電極１７間の電気的導通が得られないので、それらの間の電気抵抗が大きくなる。したがって、各組の外部取出用電極１７間の電気抵抗の測定結果に基づいて、子チップ２が親チップ１に対して平行に接合されているか否かを正確に判定することができる。   Furthermore, the connection confirmation bumps 7 and 13 may be connected to the internal circuits of the parent chip 1 and the child chip 2, respectively, or are electrically disconnected from the internal circuits of the parent chip 1 and the child chip 2, respectively. May be. When the connection confirmation bumps 7 and 13 are separated from the internal circuit, as shown in FIG. 4, in the parent chip 1, a set of two connection confirmation bumps 7 is arranged at each corner of the chip bonding area. The external extraction electrode 17 electrically connected to each connection confirmation bump 7 is provided outside the chip bonding area. On the other hand, in the child chip 2, a pair of connection confirmation bumps 13 are arranged at each corner, and the pair of connection confirmation bumps 13 are electrically connected to each other. Thus, when the parent chip 1 and the child chip 2 are joined in parallel, the connection confirmation bumps 7 and 13 are connected to each other, and the external extraction electrodes 17 of each group are short-circuited. Therefore, the electrical resistance between them becomes small. On the other hand, when the child chip 2 is joined to the parent chip 1 while being inclined, the connection of the connection confirmation bumps 7 and 13 is not achieved in the portion where the distance between the surfaces is wide, and the connection between the external extraction electrodes 17 is not achieved. Therefore, the electrical resistance between them becomes large. Therefore, it is possible to accurately determine whether or not the child chip 2 is bonded in parallel to the parent chip 1 based on the measurement result of the electrical resistance between the external extraction electrodes 17 of each group.

また、チップ・チップ・オン・チップ構造の半導体装置を例示したが、この発明は、半導体チップの表面を配線基板（固体装置）に対向させて接合するフリップ・チップ・ボンディング構造の半導体装置に適用されてもよい。
その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。 Further, the semiconductor device having a chip-chip-on-chip structure has been exemplified, but the present invention is applied to a semiconductor device having a flip-chip bonding structure in which the surface of the semiconductor chip is bonded to face the wiring substrate (solid device). May be.
In addition, various design changes can be made within the scope of matters described in the claims.

この発明の一実施形態に係る半導体装置の構成を示す図解的な断面図である。1 is an illustrative sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. 親チップおよび子チップ間における機能バンプの接続部分および接続確認用バンプの接続部分の図解的な断面図であり、（ａ）は、子チップの機能バンプの先端部のはんだ接合材が親チップの機能バンプの頂面に接触した時の状態を示し、（ｂ）は、親チップと子チップとの接合が完了した時の状態を示す。FIG. 6 is a schematic cross-sectional view of a functional bump connection portion and a connection confirmation bump connection portion between a parent chip and a child chip, and FIG. The state when contacting the top surface of the functional bump is shown, and (b) shows the state when the bonding between the parent chip and the child chip is completed. この発明の他の実施形態（親チップにおいても、接続確認用バンプが機能バンプよりも低く形成された態様）を説明するための図解的な断面図であり、（ａ）は、子チップの機能バンプの先端部のはんだ接合材が親チップの機能バンプの頂面に接触した時の状態を示し、（ｂ）は、親チップと子チップとの接合が完了した時の状態を示す。FIG. 6 is a schematic cross-sectional view for explaining another embodiment of the present invention (an aspect in which a connection confirmation bump is formed lower than a functional bump in the parent chip), and (a) is a function of a child chip. A state when the solder bonding material at the tip of the bump contacts the top surface of the functional bump of the parent chip is shown, and (b) shows a state when the bonding between the parent chip and the child chip is completed. 接続確認用バンプが親チップおよび子チップの内部回路から電気的に切り離された場合の構成を示す図解的な平面図である。It is an illustration top view which shows a structure when the bump for connection confirmation is electrically disconnected from the internal circuit of the parent chip and the child chip.

符号の説明Explanation of symbols

１ 親チップ
２ 子チップ
３ 表面
６ 機能バンプ
７ 接続確認用バンプ
１１ 表面
１２ 機能バンプ
１３ 接続確認用バンプ
１４ 接続金属層 DESCRIPTION OF SYMBOLS 1 Parent chip 2 Child chip 3 Surface 6 Functional bump 7 Connection confirmation bump 11 Surface 12 Functional bump 13 Connection confirmation bump 14 Connection metal layer

Claims (4)

固体装置にその表面を対向させた状態で接合される半導体チップであって、
前記表面から突出して形成されて、前記固体装置との電気接続のための機能バンプと、
前記機能バンプによる電気接続の状態を確認するための複数の接続確認用バンプと、
前記半導体チップに設けられた前記機能バンプと前記固体装置に設けられた固体装置側機能バンプとの間、および前記半導体チップに設けられた前記複数の接続確認用バンプの各々と前記固体装置に設けられた対応する固体装置側接続確認用バンプとの間にそれぞれ介在され、それらの間の接続を達成するための接続金属層とを含み、
前記半導体チップに設けられた前記機能バンプおよび前記接続確認用バンプは、同じ金属材料を用いて形成されており、
前記半導体チップに設けられた前記接続確認用バンプの前記表面からの突出量は、前記機能バンプの前記表面からの突出量よりも小さく、
前記接続確認用バンプの前記突出量は、前記固体装置と前記半導体チップとを接続する熱処理時に、前記固体装置と前記半導体チップとが平行である場合に、前記複数の接続確認用バンプのすべてについて、対応する前記接続金属層が溶融膨張して対応する前記固体装置側接続確認用バンプに接続される突出量であることを特徴とする、半導体チップ。 A semiconductor chip bonded to a solid state device with its surface facing,
A functional bump formed to project from the surface and for electrical connection with the solid state device;
A plurality of connection confirmation bumps for confirming the state of electrical connection by the functional bumps ;
Provided between the functional bumps provided on the semiconductor chip and the solid device side functional bumps provided on the solid-state device, and on each of the plurality of connection confirmation bumps provided on the semiconductor chip and the solid-state device. A connection metal layer interposed between the corresponding solid device side connection confirmation bumps, respectively, for achieving a connection therebetween,
The functional bumps and the connection confirmation bumps provided on the semiconductor chip are formed using the same metal material,
The amount of protrusion of the connection confirmation bump provided on the semiconductor chip from the surface is smaller than the amount of protrusion of the functional bump from the surface,
The amount of protrusion of the connection confirmation bump is determined for all of the plurality of connection confirmation bumps when the solid state device and the semiconductor chip are parallel during the heat treatment for connecting the solid state device and the semiconductor chip. The semiconductor chip is characterized in that the corresponding connection metal layer has a protruding amount connected to the corresponding solid device side connection confirmation bump by melting and expanding . 第１の半導体チップと第２の半導体チップとを前記第１の半導体チップの表面に前記第２の半導体チップの表面を対向させた状態で接合した、チップ・オン・チップ構造を有する半導体装置であって、
前記第１の半導体チップの表面から突出して形成された第１半導体チップ側機能バンプと、
前記第１の半導体チップの表面から突出して形成された複数の第１半導体チップ側接続確認用バンプと、
前記第２の半導体チップの表面から突出して形成され、前記第１半導体チップ側機能バンプに接続されて、前記第１の半導体チップと前記第２の半導体チップとの電気接続を達成するための第２半導体チップ側機能バンプと、
前記第２の半導体チップの表面からの前記第２半導体チップ側機能バンプの突出量よりも小さい突出量で、前記第２の半導体チップの表面から突出して形成され、前記複数の第１半導体チップ側接続確認用バンプとそれぞれ接続されて、前記第１の半導体チップと前記第２の半導体チップとの電気接続の状態を確認するための複数の第２半導体チップ側接続確認用バンプと、
前記第１半導体チップ側機能バンプと前記第２半導体チップ側機能バンプとの間、および前記第１半導体チップ側接続確認用バンプと前記第２半導体チップ側接続確認用バンプとの間にそれぞれ介在され、それらの間の接続を達成するための接続金属層とを含み、
前記第１半導体チップ側機能バンプ、前記第２半導体チップ側機能バンプ、前記第１半導体チップ側接続確認用バンプおよび前記第２半導体チップ側接続確認用バンプは、同じ金属材料を用いて形成されており、
前記第２半導体チップ側接続確認用バンプの前記突出量は、前記第１の半導体チップと前記第２の半導体チップとを接続する熱処理時に、前記第１の半導体チップと前記第２の半導体チップとが平行である場合に、前記複数の第２半導体チップ側接続確認用バンプのすべてについて、対応する前記接続金属層が溶融膨張して対応する前記第１半導体チップ側接続確認用バンプに接続される突出量であることを特徴とする、半導体装置。 A semiconductor device having a chip-on-chip structure in which a first semiconductor chip and a second semiconductor chip are joined to a surface of the first semiconductor chip with the surface of the second semiconductor chip facing each other. There,
A first semiconductor chip-side functional bump formed to protrude from the surface of the first semiconductor chip;
A plurality of first semiconductor chip side connection confirmation bumps formed to protrude from the surface of the first semiconductor chip;
The first semiconductor chip is formed so as to protrude from the surface of the second semiconductor chip, and is connected to the first semiconductor chip-side functional bump to achieve electrical connection between the first semiconductor chip and the second semiconductor chip. 2 semiconductor chip side functional bumps,
In smaller projecting amount than the amount of projection of the second semiconductor chip side functions bumps from the surface of the second semiconductor chip, it is formed to protrude from the surface of the second semiconductor chip, the first semiconductor chip side of the plurality A plurality of second semiconductor chip side connection confirmation bumps, each connected to a connection confirmation bump, for confirming the state of electrical connection between the first semiconductor chip and the second semiconductor chip ;
It is interposed between the first semiconductor chip side functional bump and the second semiconductor chip side functional bump, and between the first semiconductor chip side connection confirmation bump and the second semiconductor chip side connection confirmation bump, respectively. and a connecting metal layer to achieve the connection between them seen including,
The first semiconductor chip-side functional bump, the second semiconductor chip-side functional bump, the first semiconductor chip-side connection confirmation bump, and the second semiconductor chip-side connection confirmation bump are formed using the same metal material. And
The amount of protrusion of the second semiconductor chip side connection confirmation bump is determined between the first semiconductor chip and the second semiconductor chip during a heat treatment for connecting the first semiconductor chip and the second semiconductor chip. Are parallel, for all of the plurality of second semiconductor chip side connection confirmation bumps, the corresponding connection metal layer melts and expands and is connected to the corresponding first semiconductor chip side connection confirmation bump. A semiconductor device, characterized by a protruding amount . 前記第２の半導体チップは、その表面を垂直に見下ろしたときの形状が略矩形状をなしており、
前記第２半導体チップ側機能バンプは、前記第２の半導体チップの表面の中央部に配置され、
前記第２半導体チップ側接続確認用バンプは、前記第２の半導体チップの表面の各角部に配置されていることを特徴とする、請求項２記載の半導体装置。 The second semiconductor chip has a substantially rectangular shape when the surface is looked down vertically,
The second semiconductor chip side functional bump is disposed at the center of the surface of the second semiconductor chip,
It said second semiconductor chip side connection confirmation bumps is characterized in that it is arranged at each corner of the surface of the second semiconductor chip, a semiconductor device according to claim 2 Symbol placement. 前記第１半導体チップ側接続確認用バンプは、前記第１の半導体チップの表面からの前記第１半導体チップ側機能バンプの突出量よりも小さい突出量で、前記第１の半導体チップの表面から突出して形成されていることを特徴とする、請求項２または３記載の半導体装置。 The first semiconductor chip side connection confirmation bump protrudes from the surface of the first semiconductor chip with a protruding amount smaller than the protruding amount of the first semiconductor chip side functional bump from the surface of the first semiconductor chip. characterized in that it is formed Te, semiconductor device according to claim 2 or 3 wherein.
JP2005241521A 2005-08-23 2005-08-23 Semiconductor chip and semiconductor device Active JP4723312B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2005241521A JP4723312B2 (en) 2005-08-23 2005-08-23 Semiconductor chip and semiconductor device
KR1020087004282A KR20080037681A (en) 2005-08-23 2006-08-18 Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
US11/990,875 US8653657B2 (en) 2005-08-23 2006-08-18 Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
PCT/JP2006/316264 WO2007023747A1 (en) 2005-08-23 2006-08-18 Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
TW095130993A TW200721438A (en) 2005-08-23 2006-08-23 Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005241521A JP4723312B2 (en) 2005-08-23 2005-08-23 Semiconductor chip and semiconductor device

Publications (2)

Publication Number Publication Date
JP2007059548A JP2007059548A (en) 2007-03-08
JP4723312B2 true JP4723312B2 (en) 2011-07-13

Family

ID=37922788

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005241521A Active JP4723312B2 (en) 2005-08-23 2005-08-23 Semiconductor chip and semiconductor device

Country Status (1)

Country Link
JP (1) JP4723312B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102190382B1 (en) 2012-12-20 2020-12-11 삼성전자주식회사 Semiconductor package

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09181124A (en) * 1995-12-27 1997-07-11 Mitsubishi Electric Corp Semiconductor device, its mounting method and inspection method of mounting part
JP2003133508A (en) * 2001-10-23 2003-05-09 Rohm Co Ltd Semiconductor device
JP2003142649A (en) * 2001-11-05 2003-05-16 Rohm Co Ltd Semiconductor device
JP2004228202A (en) * 2003-01-21 2004-08-12 Matsushita Electric Ind Co Ltd Semiconductor apparatus and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09181124A (en) * 1995-12-27 1997-07-11 Mitsubishi Electric Corp Semiconductor device, its mounting method and inspection method of mounting part
JP2003133508A (en) * 2001-10-23 2003-05-09 Rohm Co Ltd Semiconductor device
JP2003142649A (en) * 2001-11-05 2003-05-16 Rohm Co Ltd Semiconductor device
JP2004228202A (en) * 2003-01-21 2004-08-12 Matsushita Electric Ind Co Ltd Semiconductor apparatus and its manufacturing method

Also Published As

Publication number Publication date
JP2007059548A (en) 2007-03-08

Similar Documents

Publication Publication Date Title
US6677674B2 (en) Semiconductor package having two chips internally connected together with bump electrodes and both chips externally connected to a lead frame with bond wires
US7619305B2 (en) Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking
JP3765952B2 (en) Semiconductor device
JP4074862B2 (en) Semiconductor device manufacturing method, semiconductor device, and semiconductor chip
US6316838B1 (en) Semiconductor device
JP4175197B2 (en) Flip chip mounting structure
JP5645592B2 (en) Manufacturing method of semiconductor device
JP2002222889A (en) Semiconductor device and method of manufacturing the same
JP5181261B2 (en) Contact pad for integrated circuit and method of forming contact pad
WO2007023747A1 (en) Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
JP4723312B2 (en) Semiconductor chip and semiconductor device
JP3670625B2 (en) Semiconductor device and manufacturing method thereof
JP4791104B2 (en) Semiconductor chip and method for manufacturing semiconductor chip
JP2007207805A (en) Semiconductor device and method of manufacturing same
JP2000124395A (en) Multi-chip semiconductor package structure and its manufacture
JP4606376B2 (en) Semiconductor device
JP2004363319A (en) Mount substrate and semiconductor device
JP2006066551A (en) Method for manufacturing semiconductor device
JP2001118954A (en) Semiconductor device
JP2004111695A (en) Semiconductor device and its manufacturing method
KR100507131B1 (en) Method of manufacturing MCM ball grid array package
JP2002076048A (en) Layout method of bump by flip chip connection
CN104701246B (en) Chip and forming method, encapsulation finished product, the method for improving encapsulation finished product yield
KR101133126B1 (en) Semiconductor package and manufacturing method thereof
JP2005150441A (en) Chip laminated semiconductor device and its manufacturing method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080819

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101222

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110221

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110331

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110407

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140415

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4723312

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250