JPH09181124A - Semiconductor device, its mounting method and inspection method of mounting part - Google Patents

Semiconductor device, its mounting method and inspection method of mounting part

Info

Publication number
JPH09181124A
JPH09181124A JP7340685A JP34068595A JPH09181124A JP H09181124 A JPH09181124 A JP H09181124A JP 7340685 A JP7340685 A JP 7340685A JP 34068595 A JP34068595 A JP 34068595A JP H09181124 A JPH09181124 A JP H09181124A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrodes
bonding material
height
protruding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7340685A
Other languages
Japanese (ja)
Other versions
JP3325755B2 (en
Inventor
Goro Ideta
吾朗 出田
Miho Hirota
実保 弘田
Junji Fujino
純司 藤野
Teru Adachi
照 安達
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP34068595A priority Critical patent/JP3325755B2/en
Publication of JPH09181124A publication Critical patent/JPH09181124A/en
Application granted granted Critical
Publication of JP3325755B2 publication Critical patent/JP3325755B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To enable judging the quality of a mounting junction part of a semiconductor device having a plurality of protruding electrodes which are arranged in the row and the column directions and a substratum, by using simple optical inspection. SOLUTION: When a plurality of protruding electrodes 3 are arranged in the row and the column directions, the height of low protruding electrodes 3a arranged in the most outside row or column is set and formed to be about 50μm less than the height of high protruding electrodes 3b arranged inside the electrodes 3a. After the semiconductor device is mounted on and bonded to a board, the bonding state of the low protruding electrodes 3a arranged in the most outside row or column is optically inspected. When imperfect junction which is not yet bonded is not generated, it can be estimated that imperfect junction which is not yet bonded is not generated in the high protruding electrodes 3b arranged inside the electrodes 3a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、基体上に形成され
た電極と電気的に接合される突起電極を有する例えば半
導体チップや半導体チップが収められたパッケージ等の
半導体装置の構造、及びこの半導体装置を基体に実装す
る方法、さらにこれらの半導体装置の突起電極と基体の
電極との実装接合部における検査方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device, such as a semiconductor chip or a package containing the semiconductor chip, having a protruding electrode electrically connected to an electrode formed on a substrate, and the semiconductor device. The present invention relates to a method for mounting a device on a base body, and a method for inspecting a mounting joint between a protruding electrode of these semiconductor devices and an electrode on the base body.

【0002】[0002]

【従来の技術】図6は従来の半導体装置における斜視
図、図7は図6に示した従来の半導体装置のA−A線に
よる断面図であって、図において、1はパッケージ本
体、2はパッケージ本体1の中央部に収められた半導体
チップ、3は上記パッケージ本体上に形成された突起電
極で、この突起電極3は行及び列方向に多数配された突
起電極群を構成し、パッケージ本体1における半導体チ
ップ2の周囲に形成されている。ここでは、突起電極3
が半導体チップ2を取り囲むように4列のリング状にパ
ッケージ本体1に形成されている。4は半導体チップ2
の電極とパッケージ本体1の電極とを電気的に接続する
ためのワイヤである。
2. Description of the Related Art FIG. 6 is a perspective view of a conventional semiconductor device, and FIG. 7 is a sectional view taken along line AA of the conventional semiconductor device shown in FIG. A semiconductor chip 3 housed in the center of the package body 1 is a protruding electrode formed on the package body, and the protruding electrode 3 constitutes a group of protruding electrodes arranged in the row and column directions. It is formed around the semiconductor chip 2 in FIG. Here, the protruding electrode 3
Are formed on the package body 1 in a four-row ring shape so as to surround the semiconductor chip 2. 4 is a semiconductor chip 2
Is a wire for electrically connecting the electrode of 1 to the electrode of the package body 1.

【0003】従来の半導体装置は、上述したように構成
されており、このような半導体装置の実装方法は例え
ば、1995年9月1日、工業調査会発行、電子材料、
Vol34、No.9、P27〜P32に記載されてい
る。図8は従来の半導体装置を基板に実装する方法を説
明するための断面工程図であって、この図において、5
は回路基板等の基板、6はこの基板1上に形成された電
極、7はこの電極6上に供給された接合材であるはんだ
ペーストである。
A conventional semiconductor device is constructed as described above, and a mounting method of such a semiconductor device is described in, for example, September 1, 1995, published by Industrial Research Board, electronic material,
Vol 34, No. 9, P27 to P32. FIG. 8 is a cross-sectional process diagram for explaining a conventional method for mounting a semiconductor device on a substrate. In FIG.
Is a substrate such as a circuit board, 6 is an electrode formed on the substrate 1, and 7 is a solder paste which is a bonding material supplied onto the electrode 6.

【0004】まず、図8(a)に示されるように、基板
5の電極6上にはんだペーストを印刷等の方法で供給
し、パッケージ本体1の突起電極3と基板5の電極6と
が各々相対するように位置合わせをする。次に、図8
(b)に示されるように、位置合わせをした状態で基板
5上に半導体装置を搭載した後、はんだペースト7のは
んだが溶融する温度までこの状態で加熱した後、冷却す
ることによって、はんだペースト7を介して突起電極3
と電極6とが電気的に接続されるとともに、半導体装置
が基板1に固着されることとなる。
First, as shown in FIG. 8A, a solder paste is applied onto the electrodes 6 of the substrate 5 by a method such as printing, so that the projecting electrodes 3 of the package body 1 and the electrodes 6 of the substrate 5 are separated from each other. Align so that they face each other. Next, FIG.
As shown in (b), after the semiconductor device is mounted on the substrate 5 in the aligned state, the solder paste 7 is heated to a temperature at which the solder of the solder paste 7 melts, and then cooled to obtain the solder paste. Protruding electrode 3 through 7
And the electrode 6 are electrically connected, and the semiconductor device is fixed to the substrate 1.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
た半導体装置の実装方法においては、印刷法等によっ
て、基板5の多数の電極6上に所定量のはんだペースト
7が供給されることとなるが、これらの供給されたはん
だペースト7の高さは、設定値よりばらつきが生じるこ
ととなる。このはんだペースト7の高さのばらつきによ
り、パッケージ本体1の突起電極3と基板5の電極6と
の間に接合不良が発生することとなる。つまり、はんだ
ペースト7の印刷高さが設定値より高い場合隣接する電
極と接触し短絡不良が発生する。逆に、はんだペースト
7の印刷高さが設定値より低い場合には未接合不良が発
生する。
However, in the above-described method of mounting a semiconductor device, a predetermined amount of solder paste 7 is supplied onto a large number of electrodes 6 of the substrate 5 by a printing method or the like. The height of the supplied solder paste 7 varies from the set value. Due to the variation in the height of the solder paste 7, a bonding failure will occur between the protruding electrode 3 of the package body 1 and the electrode 6 of the substrate 5. That is, when the printing height of the solder paste 7 is higher than the set value, the solder paste 7 comes into contact with an adjacent electrode and a short circuit defect occurs. On the contrary, when the print height of the solder paste 7 is lower than the set value, unbonding failure occurs.

【0006】上述したような接合不良は、パッケージ本
体1のいずれの位置に形成された突起電極3においても
発生する可能性がある。また、上述した電極の短絡不良
においては、回路を電気的に検査することによって比較
的簡単に発見できるものの電極の未接合不良は以下に示
すような理由で電気的な検査だけでは発見することがで
きない。
The above-mentioned bonding failure may occur at any of the protruding electrodes 3 formed on the package body 1. Further, in the above-described electrode short-circuit failure, it is possible to find relatively easily by electrically inspecting a circuit, but unbonded electrode failure can be found only by electrical inspection for the following reasons. Can not.

【0007】図9は、良好な接合状態と未接合不良状態
の接合部の例を示す断面図である。この図において、図
中円内で示される箇所であるAは突起電極3とはんだペ
ースト7とが濡れを生じることによってフィレットが形
成され基板5の電極6とパッケージ本体1の突起電極3
との接合状態が良好な接合部、Bは完全にパッケージ本
体1の突起電極3とはんだペースト7とが離れた完全な
未接合不良な接合部、Cは突起電極3とはんだペースト
7が接しているものの、この突起電極3とはんだペース
ト7とが濡れを生じずフィレットは形成されず、完全に
未接合不良な接合部Bとも良好な接合部Aとも判断でき
ない不完全な接合部である。
FIG. 9 is a cross-sectional view showing an example of a joined portion in a good joined state and an unjoined defective state. In this figure, a portion A indicated by a circle in the drawing forms a fillet when the protruding electrode 3 and the solder paste 7 are wetted, and the electrode 6 of the substrate 5 and the protruding electrode 3 of the package body 1 are formed.
Is a joint portion in which the protruding electrode 3 and the solder paste 7 of the package body 1 are completely separated from each other, and C is a portion where the protruding electrode 3 and the solder paste 7 are in contact with each other. However, the protrusion electrode 3 and the solder paste 7 do not wet and a fillet is not formed, and it is an incomplete joint which cannot be completely judged as a poor joint B or a good joint A.

【0008】上述した完全に未接合不良な接合部Bにお
いては上述したように電気的な検査によって未接合不良
と容易に判定できるが、不完全な接合部Cにおいては電
気的に良好と判定される場合もあり必ずしも不良と判定
されない。しかしながらこのような場合において、使用
初期においては所望の電気特性を発揮するものの、僅か
なひずみ等で突起電極3とはんだペースト7とが離れ、
簡単に回路が断たれることとなり、半導体装置としての
信頼性が低下することとなる。
In the above-mentioned completely unbonded defective joint B, it is possible to easily determine the unbonded defective by electrical inspection as described above, but in the defective joint C it is judged to be electrically good. In some cases, it is not always judged as defective. However, in such a case, although the desired electrical characteristics are exhibited in the initial stage of use, the protruding electrode 3 and the solder paste 7 are separated from each other by a slight strain or the like,
The circuit is easily broken, and the reliability of the semiconductor device is reduced.

【0009】従って、電極接合部の接合状態の良否は電
気的検査のみでは判断できず、接合部の接合形状によっ
ても判定すべきである。しかしながら、行及び列方向に
多数配された突起電極3を有するパッケージ本体1を基
板5上に実装する場合、最外周側に形成された突起電極
3のためその内側に形成された突起電極3の接合部の形
状を外部より観察することは不可能であった。
Therefore, the quality of the bonding state of the electrode bonding portion cannot be judged only by the electrical inspection, but should be judged also by the bonding shape of the bonding portion. However, when mounting the package body 1 having a large number of protruding electrodes 3 arranged in the row and column directions on the substrate 5, the protruding electrodes 3 formed on the outermost peripheral side of the package main body 1 are not formed. It was impossible to observe the shape of the joint from the outside.

【0010】またX線CT装置などを用いれば、内側に
設けられた突起電極3の接合部形状を検査することは可
能であるが、このX線CT装置は高価であり、さらに検
査時間も長時間に及ぶために検査コストの高騰の原因と
なっていた。
Although it is possible to inspect the shape of the joint of the protruding electrode 3 provided inside by using an X-ray CT apparatus or the like, this X-ray CT apparatus is expensive and the inspection time is long. It took a long time, which caused a high inspection cost.

【0011】本発明は係る課題を解決するためなされた
もので、行及び列方向に複数個配された突起電極を有す
る半導体装置と基体との実装接合部の良否を簡単な光学
的検査によって判定できる半導体装置の構造を提供する
とともに、その実装方法及びその半導体装置と基体との
実装接合部における検査方法を提供することを目的とす
る。
The present invention has been made to solve the above problems, and determines the quality of a mounting joint between a semiconductor device having a plurality of protruding electrodes arranged in the row and column directions and a substrate by a simple optical inspection. It is an object of the present invention to provide a structure of a semiconductor device that can be manufactured, and a method of mounting the semiconductor device and a method of inspecting a mounting joint portion between the semiconductor device and a substrate.

【0012】[0012]

【課題を解決するための手段】本発明の請求項1記載の
半導体装置は、基体上に形成された電極と接合材を介し
て電気的に接合される突起電極が、行及び列方向に複数
個配されて構成された突起電極群を有する半導体装置に
おいて、上記突起電極群の最外側の行又は列に配された
上記突起電極の高さが、その内側に配された上記突起電
極の高さより低いことを特徴とするものである。
According to a first aspect of the present invention, a semiconductor device has a plurality of protruding electrodes electrically connected to electrodes formed on a substrate through a bonding material in the row and column directions. In a semiconductor device having a group of protruding electrodes arranged individually, the height of the protruding electrodes arranged in the outermost row or column of the protruding electrode group is higher than the height of the protruding electrodes arranged inside thereof. It is characterized by being lower than that.

【0013】また、本発明の請求項2記載の半導体装置
は、基体上に形成された電極上に供給される接合材を介
して電気的に接合される突起電極が、行及び列方向に複
数個配されて構成された突起電極群を有する半導体装置
において、上記突起電極群の最外側の行又は列に配され
た上記突起電極の高さが、その内側に配された上記突起
電極の高さより低く、その高さの差が上記供給される接
合材の高さのばらつき量より大きいことを特徴とするも
のである。
In the semiconductor device according to the second aspect of the present invention, a plurality of projecting electrodes electrically connected to each other through the bonding material supplied on the electrodes formed on the base are arranged in the row and column directions. In a semiconductor device having a group of protruding electrodes arranged individually, the height of the protruding electrodes arranged in the outermost row or column of the protruding electrode group is higher than the height of the protruding electrodes arranged inside thereof. And the difference in height is larger than the variation in the height of the supplied bonding material.

【0014】さらに、本発明の請求項3記載の半導体装
置は、基体上に形成された電極上にめっき法により供給
される接合材を介して電気的に接合される突起電極が、
行及び列方向に複数個配されて構成された突起電極群を
有する半導体装置において、上記突起電極群の最外側の
行又は列に配された上記突起電極の高さが、その内側に
配された上記突起電極の高さより低く、その高さの差が
2μmより大きいことを特徴とするものである。
Further, in the semiconductor device according to claim 3 of the present invention, the protruding electrode electrically connected to the electrode formed on the substrate through the bonding material supplied by the plating method,
In a semiconductor device having a plurality of protruding electrode groups arranged in the row and column directions, the height of the protruding electrodes arranged in the outermost row or column of the protruding electrode group is arranged inside thereof. Further, it is characterized in that it is lower than the height of the above-mentioned projection electrode and the difference in height is larger than 2 μm.

【0015】本発明の請求項4記載の半導体装置の実装
方法は、電極が行及び列方向に複数個配されて構成され
た電極群が形成された基体の上記電極群の最外側の行又
は列に配された電極上に供給される接合材の高さが、そ
の内側に配された電極上に供給される接合材の高さより
低くなるように接合材を上記電極群へ供給する工程と、
上記接合材が配された上記基体の電極と、突起電極が行
及び列方向に複数個配されて構成された突起電極群を有
する半導体装置の突起電極とがそれぞれ対向するように
位置合わせをした後、上記電極群の最外側の行又は列に
配された電極上の高さの低い接合材が上記突起電極と接
触するまで上記半導体装置と上記基体とを接近させ、上
記接合材を介して上記基体上の電極群と上記半導体装置
の突起電極群とを接触させ、上記基体に上記半導体装置
を接合する工程とを備えたものである。
According to a fourth aspect of the present invention, there is provided a method of mounting a semiconductor device, wherein an outermost row of the electrode group of a base body on which an electrode group formed by arranging a plurality of electrodes in the row and column directions is formed or Supplying the bonding material to the electrode group so that the height of the bonding material supplied on the electrodes arranged in rows is lower than the height of the bonding material supplied on the electrodes arranged inside thereof; ,
The electrodes of the substrate on which the bonding material is arranged are aligned with the projection electrodes of the semiconductor device having the projection electrode group formed by arranging a plurality of projection electrodes in the row and column directions, respectively. After that, the semiconductor device and the base body are brought close to each other until the low-height bonding material on the electrodes arranged in the outermost row or column of the electrode group comes into contact with the protruding electrodes, and the bonding material is interposed. And a step of bringing the electrode group on the base body into contact with the protruding electrode group of the semiconductor device and joining the semiconductor device to the base body.

【0016】さらに、本発明の請求項5記載の半導体装
置の実装方法は、基体の電極群の最外側の行又は列に配
された電極上に供給される接合材の高さと、その内側に
配された電極上に供給される接合材の高さとの差が、接
合材を供給する際に生じる接合材の高さのばらつき量よ
り大きくなるように接合材を供給することを特徴とする
ものである。
Further, according to a fifth aspect of the present invention, in the method for mounting a semiconductor device, the height of the bonding material supplied on the electrodes arranged in the outermost row or column of the electrode group of the base body and the height of the inside thereof are set. Characteristically, the bonding material is supplied such that the difference from the height of the bonding material supplied on the arranged electrodes is larger than the variation amount of the height of the bonding material generated when the bonding material is supplied. Is.

【0017】また、本発明の請求項6記載の半導体装置
の実装方法は、接合材をめっき法によって電極上に供給
し、基体の電極群の最外側の行又は列に配された電極上
に供給される接合材の高さと、その内側に配された電極
上に供給される接合材の高さとの差が2μmより大きく
なるように接合材をめっき法にて供給することを特徴と
するものである。
According to a sixth aspect of the present invention, there is provided a method of mounting a semiconductor device, wherein a bonding material is supplied onto the electrodes by a plating method and the electrodes are arranged on the outermost row or column of the electrode group of the base. Characteristically, the bonding material is supplied by a plating method so that the difference between the height of the bonding material supplied and the height of the bonding material supplied on the electrode arranged inside is larger than 2 μm. Is.

【0018】本発明の請求項7記載の半導体装置は、基
体上に形成された電極と接合材を介して電気的に接合さ
れる突起電極が、行及び列方向に複数個配されて構成さ
れた突起電極群を有する半導体装置において、この突起
電極群が配された面内で、かつ上記突起電極群の最外側
に配された突起電極の整列方向に対して鉛直方向から観
察するときに、その内側に配されたすべての突起電極そ
れぞれの少なくとも一部分が観察可能なように上記突起
電極を配した突起電極群を有することを特徴とするもの
である。
A semiconductor device according to a seventh aspect of the present invention is formed by arranging a plurality of protruding electrodes electrically connected to the electrodes formed on the base body through a bonding material in the row and column directions. In a semiconductor device having a protruding electrode group, when observing from a vertical direction with respect to an alignment direction of the protruding electrodes arranged on the outermost side of the protruding electrode group in the plane in which the protruding electrode group is arranged, It is characterized in that it has a projection electrode group in which the projection electrodes are arranged so that at least a part of all the projection electrodes arranged inside thereof can be observed.

【0019】本発明の請求項8記載の半導体装置の実装
方法は、電極が行及び列方向に複数個配されて構成され
た電極群が形成された基体の上記それぞれの電極上に接
合材を供給する工程と、接合材が供給された上記基体の
電極と、請求項1〜3のいずれかに記載の半導体装置の
突起電極とがそれぞれ対向するように位置合わせをした
後、上記突起電極群の最外側の行又は列に配された高さ
の低い突起電極が上記接合材と接触するまで上記半導体
装置と上記基体とを接近させ、上記接合材を介して上記
基体上の電極群と上記半導体装置の突起電極群とを接触
させ、上記基体に上記半導体装置を接合する工程とを備
えたことを特徴とするものである。
According to an eighth aspect of the present invention, there is provided a method for mounting a semiconductor device, wherein a bonding material is provided on each of the electrodes of a substrate having an electrode group formed by arranging a plurality of electrodes in the row and column directions. The step of supplying, the electrode of the base body to which the bonding material is supplied, and the projection electrode of the semiconductor device according to claim 1, are aligned so as to face each other, and then the projection electrode group. The semiconductor device and the base body are brought close to each other until the protruding electrodes having a low height arranged in the outermost row or column of contact with the joint material, and the electrode group on the base body and the above-mentioned electrode group through the joint material. And a step of bringing the semiconductor device into contact with a projection electrode group of the semiconductor device and joining the semiconductor device to the base body.

【0020】本発明の請求項9記載の半導体装置の実装
方法は、電極が行及び列方向に複数個配されて構成され
た電極群が形成された基体の上記それぞれの電極上に接
合材を供給する工程と、接合材が供給された上記基体の
電極と、請求項7記載の半導体装置の突起電極とがそれ
ぞれ対向するように位置合わせをした後、上記突起電極
群の最外側の行又は列に配された高さの低い突起電極が
上記接合材と接触するまで上記半導体装置と上記基体と
を接近させ、上記接合材を介して上記基体上の電極群と
上記半導体装置の突起電極群とを接触させ、上記基体に
上記半導体装置を接合する工程とを備えたことを特徴と
するものである。
According to a ninth aspect of the present invention, there is provided a method of mounting a semiconductor device, wherein a bonding material is provided on each of the electrodes of a substrate on which an electrode group formed by arranging a plurality of electrodes in the row and column directions is formed. The step of supplying, the electrode of the base body to which the bonding material is supplied, and the projection electrode of the semiconductor device according to claim 7 are aligned so as to face each other, and then the outermost row of the projection electrode group or The semiconductor device and the base body are brought close to each other until the low-height protruding electrodes arranged in rows come into contact with the bonding material, and the electrode group on the base body and the protruding electrode group of the semiconductor device are interposed via the bonding material. And a step of joining the semiconductor device to the base body.

【0021】本発明の請求項10記載の半導体装置実装
部の検査方法は、請求項4〜6、8、9のいずれかに記
載の半導体装置の実装方法によって、上記半導体装置が
基体へ実装された後の半導体装置実装部の検査方法にお
いて、突起電極と電極との接合状態の電気的検査と、突
起電極群及び電極群の最外側に配された突起電極と電極
との接合状態の光学的検査とを行うことによって実装部
の評価を行うことを特徴とするものである。
According to a tenth aspect of the present invention, there is provided a semiconductor device mounting portion inspection method, wherein the semiconductor device is mounted on a substrate by the semiconductor device mounting method according to any one of the fourth to sixth, eighth and ninth aspects. In the method for inspecting the semiconductor device mounting portion after the exposure, an electrical inspection of the bonding state between the protruding electrode and the electrode and an optical inspection of the bonding state between the protruding electrode group and the protruding electrode arranged on the outermost side of the electrode group and the electrode are performed. It is characterized in that the mounting portion is evaluated by performing inspection.

【0022】[0022]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

実施の形態1.以下、本発明の実施の形態1である半導
体装置について説明する。図1は、本発明の実施の形態
1である半導体装置の断面図である。この図において、
1は内部に半導体チップ2(図6記載)が収められるパ
ッケージ本体、3はこのパッケージ本体1上に形成され
た、例えばはんだからなる突起電極でこの突起電極3は
行及び列方向に複数個配されて突起電極群を構成しパッ
ケージ本体1における半導体チップ2の外周囲に形成さ
れている。ここでは突起電極群が半導体チップ2を取り
囲むように4列のリング状にパッケージ本体1に形成さ
れている。
Embodiment 1 FIG. The semiconductor device according to the first embodiment of the present invention will be described below. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. In this figure,
Reference numeral 1 denotes a package body in which a semiconductor chip 2 (shown in FIG. 6) is housed. Reference numeral 3 denotes a protruding electrode formed on the package body 1 and made of, for example, solder. The protruding electrodes 3 are arranged in a plurality of rows and columns. Thus, a projecting electrode group is formed and is formed around the outer periphery of the semiconductor chip 2 in the package body 1. Here, the protruding electrode group is formed on the package body 1 in a four-row ring shape so as to surround the semiconductor chip 2.

【0023】また、3aはこの突起電極群の最外周の列
及び行に配され、径約500μm、高さ約200μmに
設定されて形成された低い突起電極で、3bはこの低い
突起電極3aより内側の列及び行に配され、この低い突
起電極3aより約50μm高く、つまり約250μmの
高さに設定されて形成された高い突起電極である。高さ
の低い突起電極3a及び高い突起電極3b同士は基本的
に全て同じ大きさ、高さに設定して形成されている。
3a is a low protruding electrode formed in the outermost column and row of this protruding electrode group and having a diameter of about 500 μm and a height of about 200 μm, and 3b is lower than this lower protruding electrode 3a. The high protruding electrodes are arranged in the inner columns and rows and are formed to have a height higher than the low protruding electrodes 3a by about 50 μm, that is, about 250 μm. The protruding electrodes 3a having a low height and the protruding electrodes 3b having a high height are basically formed to have the same size and height.

【0024】このように構成された半導体装置におい
て、パッケージ本体1上の突起電極3の配置は従来の技
術にて説明した図6とほぼ同じであり、突起電極群の最
外周の行及び列には低い突起電極3aが、その内側の行
及び列には高い突起電極3bが配されていることとな
る。
In the semiconductor device configured as described above, the arrangement of the protruding electrodes 3 on the package body 1 is almost the same as that shown in FIG. 6 described in the prior art, and the outermost rows and columns of the protruding electrode group are arranged. Means that the low protruding electrodes 3a are arranged, and the high protruding electrodes 3b are arranged in rows and columns inside thereof.

【0025】次に、図2に基づいて、上述した半導体装
置を基板に実装する方法について説明する。図2は半導
体装置の基板への実装工程を順次示す製造工程断面図で
ある。この図において、5は基体である例えば回路基板
等の基板、6はこの基板1上に形成された例えば銅から
なる電極で、この電極6は各々突起電極3と相対するよ
うに行及び列方向に複数個配された電極群を構成する。
7はこの電極6上に供給され、基板5の電極6とパッケ
ージ本体1の突起電極3とを電気的に接続し、固着する
ための接合材である例えばはんだペーストである。
Next, a method of mounting the above-described semiconductor device on a substrate will be described with reference to FIG. 2A to 2D are cross-sectional views of manufacturing steps sequentially showing the steps of mounting a semiconductor device on a substrate. In this figure, 5 is a substrate, for example, a substrate such as a circuit board, 6 is an electrode made of, for example, copper formed on the substrate 1, and the electrodes 6 are arranged in the row and column directions so as to face the protruding electrodes 3. A plurality of electrode groups are arranged in each.
Reference numeral 7 is a solder paste, which is a bonding material that is supplied onto the electrode 6 to electrically connect and fix the electrode 6 of the substrate 5 and the protruding electrode 3 of the package body 1.

【0026】まず、図2(a)に示されるように、基板
5の電極6上に例えば印刷法によってはんだペースト7
を供給し、パッケージ本体1の突起電極3と基板5の電
極6とが各々相対するように位置合わせをする。次に図
2(b)に示されるように、位置合わせをした状態で、
基板5上に半導体装置を搭載し、パッケージ本体1の低
い突起電極3aとはんだペースト7が接触するまで押し
込み、はんだペースト7のはんだが溶融する温度、例え
ば200℃までこの状態で加熱した後、冷却することに
よって、はんだペースト7を介して突起電極3と電極6
とが電気的に接続されるとともに半導体装置が基板1に
固着されることとなる。次に、パッケージ本体1の突起
電極3とはんだペースト7との接合状態を電気的な検
査、及び外部より目視又は画像認識等の簡単な光学的検
査によって評価する。
First, as shown in FIG. 2A, the solder paste 7 is formed on the electrodes 6 of the substrate 5 by, for example, a printing method.
Are supplied to align the protruding electrodes 3 of the package body 1 and the electrodes 6 of the substrate 5 with each other. Next, as shown in FIG. 2 (b), in a state where the alignment is performed,
The semiconductor device is mounted on the substrate 5, and is pushed until the low protruding electrode 3a of the package body 1 and the solder paste 7 come into contact with each other, and is heated to a temperature at which the solder of the solder paste 7 melts, for example, 200 ° C., and then cooled. By doing so, the protruding electrode 3 and the electrode 6 are connected via the solder paste 7.
And are electrically connected, and the semiconductor device is fixed to the substrate 1. Next, the bonding state between the protruding electrode 3 of the package body 1 and the solder paste 7 is evaluated by an electrical inspection and a simple optical inspection such as visual observation or image recognition from the outside.

【0027】上述した半導体装置の実装方法では、印刷
法によってはんだペースト7を供給する工程において、
印刷法によって供給されるはんだペースト7の印刷高さ
の設計値を例えば150μmとしたとき、実際供給され
たはんだペースト7の印刷高さは約135μmから約1
65μmの範囲でばらつくことがわかっている。即ち、
供給されたはんだペースト7の印刷高さの最高と最低の
部分とでは約30μmの差異が生じる。また、パッケー
ジ本体1を基板5に搭載する工程においては、この搭載
荷重によって印刷されたはんだペースト7中にパッケー
ジ本体1の突起電極3が押し込まれることとなるが、パ
ッケージ本体1の突起電極群の最外周に配された低い突
起電極3aはその内側に配された高い突起電極3bより
50μm低いため、全てのはんだペースト7と突起電極
3とが接触する状態となるためには、この高さの差異で
ある約50μmはさらに押し込まなければならない。
In the mounting method of the semiconductor device described above, in the step of supplying the solder paste 7 by the printing method,
When the design value of the printing height of the solder paste 7 supplied by the printing method is 150 μm, the printing height of the solder paste 7 actually supplied is about 135 μm to about 1 μm.
It is known that there are variations in the range of 65 μm. That is,
A difference of about 30 μm occurs between the highest and lowest printing heights of the supplied solder paste 7. Further, in the step of mounting the package body 1 on the substrate 5, the protruding electrodes 3 of the package body 1 are pushed into the printed solder paste 7 by the mounting load. Since the low protruding electrode 3a arranged on the outermost periphery is lower than the high protruding electrode 3b arranged inside by 50 μm, in order to bring all the solder paste 7 and the protruding electrode 3 into contact with each other, The difference of about 50 μm must be pushed in further.

【0028】従って、最外周に配された約50μm低い
突起電極3aがはんだペースト7と全て接触していれ
ば、はんだペースト7の印刷高さのばらつき量は約30
μmであるため、その内側に配された高い突起電極3b
は、供給されたはんだペースト7の高さのバラツキにか
かわらず接合されていることとなる。すなわち、基板5
上に半導体装置が搭載された状態において、この半導体
装置の外部つまり側面方向より目視又は画像認識等の光
学的検査によって突起電極群の最外周に配された低い突
起電極3aに未接合不良が発生していなければ、その内
側に配された、観察ができない高い突起電極3bにおい
ても未接合不良が発生することはないので未接合不良の
判定が簡単な光学的な検査によって容易に行うことがで
きる。さらに電気的検査によって短絡不良は容易に検査
できる。従って、X線CT装置を用いなくとも外部から
の光学的検査及び電気的な検査によって、全ての電極の
接合状態が判定できるため、検査時間が短縮できるとと
もに検査コストを抑制することができる。
Therefore, if the protruding electrodes 3a of about 50 μm lower arranged on the outermost periphery are all in contact with the solder paste 7, the variation in the printing height of the solder paste 7 is about 30.
Since it is μm, the high protruding electrode 3b arranged inside thereof is
Will be joined regardless of the height variation of the supplied solder paste 7. That is, the substrate 5
In the state where the semiconductor device is mounted on the semiconductor device, unbonded defects occur in the low protruding electrodes 3a arranged on the outermost periphery of the protruding electrode group by optical inspection such as visual observation or image recognition from the outside of the semiconductor device, that is, the side direction. If not, no unbonded defect is generated even in the high protrusion electrode 3b which is arranged inside and is not observable. Therefore, the unbonded defect can be easily determined by a simple optical inspection. . Furthermore, a short circuit defect can be easily inspected by an electrical inspection. Therefore, the bonding state of all the electrodes can be determined by an optical inspection and an electrical inspection from the outside without using the X-ray CT apparatus, so that the inspection time can be shortened and the inspection cost can be suppressed.

【0029】また、この実施の形態においては、高い突
起電極3bと低い突起電極3aとの高さの差異は約50
μmとしたが、この高さの差異は印刷によるはんだペー
スト7のばらつき量より大きくすればよく、最外周に配
された低い突起電極3aが全てはんだペースト7と接合
していればその内側に配された高い突起電極3bにおい
ては、はんだペースト7のばらつき量より高く設定して
いるのではんだペースト7の高さがばらついたとしても
全て接合していることとなる。また、この実施の形態の
ように、低い突起電極3aと高い突起電極3bとの差異
をはんだペースト7のばらつき量+αとするのは、突起
電極3の形成時のこの突起電極の高さのばらつき量も考
慮し、より確実に接合状態を判定するためである。
In this embodiment, the height difference between the high protruding electrode 3b and the low protruding electrode 3a is about 50.
Although the difference in height is set to be larger than the variation amount of the solder paste 7 due to printing, if all the low protruding electrodes 3a arranged on the outermost periphery are joined to the solder paste 7, the height difference is set to the inside. The height of the bump electrode 3b is set higher than the variation amount of the solder paste 7. Therefore, even if the height of the solder paste 7 varies, they are all bonded. Further, as in this embodiment, the difference between the low protruding electrode 3a and the high protruding electrode 3b is set to the variation amount + α of the solder paste 7 because the variation in the height of the protruding electrode 3 when the protruding electrode 3 is formed. This is because the bonding state can be determined more reliably in consideration of the amount.

【0030】さらに、低い突起電極3aと高い突起電極
3bとの高さの差がはんだペースト7の印刷高さのばら
つき量より小さくともわずかでも差異を生じさせること
によって最外周に配された低い突起電極3aは、他の内
側に配された高い突起電極より接合しにくくなる。つま
り、はんだペースト7の印刷の高さのばらつきは、どの
箇所においても、同様の確率で生じるとすれば、最外周
の多数の低い突起電極3aにおいて、未接合不良が確率
的に最も発生しやすくなり、未接合不良は最外周に配さ
れた低い突起電極3aに集中することとなる。従って、
この最外周に配された多数の低い突起電極3aに未接合
不良が発生していなければ、その内側に配された高い突
起電極3bにおいて、ほぼ未接合不良が発生していない
と判定できることとなる。
Further, even if the difference in height between the low protrusion electrodes 3a and the high protrusion electrodes 3b is smaller than the variation amount of the printing height of the solder paste 7, even a slight difference is generated, so that the low protrusions arranged on the outermost periphery are formed. The electrode 3a is more difficult to join than the other high protruding electrodes arranged inside. That is, if the variation in the printing height of the solder paste 7 occurs at the same probability in any place, unbonded defects are most likely to occur in many low protruding electrodes 3a on the outermost periphery. Therefore, the unbonded defects are concentrated on the low protruding electrodes 3a arranged on the outermost periphery. Therefore,
If no unbonded defect has occurred in the large number of low protruding electrodes 3a arranged on the outermost periphery, it can be determined that almost no unbonded defect has occurred in the high protruding electrode 3b arranged inside thereof. .

【0031】なお、ここでは接合材としてはんだペース
ト7を印刷法にて供給する場合について説明したが、こ
れに限るものでなくはんだ材をめっき法によって供給し
ても良い。この場合、例えば設計値としてはんだめっき
の高さを30μmとしたとき、実際のはんだめっきの高
さは1パッケージ内で、±1μmの範囲でばらつくか
ら、最外周に配した低い突起電極3aとその内側の高い
突起電極3bとの高さの差を2μmより大きくすれば、
上述したように確実に未接合不良の発生を防ぐことがで
きる。またはんだめっき法は現在の技術において、ばら
つき量は2μmが限界なので、低い突起電極3aと高い
突起電極3bとの高さの差を2μmより大きくすれば、
確実に未接合不良の発生を防ぐことができる。
Although the case where the solder paste 7 is supplied as the bonding material by the printing method has been described here, the present invention is not limited to this, and the solder material may be supplied by the plating method. In this case, for example, when the solder plating height is set to 30 μm as a design value, the actual solder plating height varies within a range of ± 1 μm within one package. If the height difference from the inner high protruding electrode 3b is made larger than 2 μm,
As described above, it is possible to reliably prevent the occurrence of unbonded defects. In the current technology, the solder plating method has a limit of variation of 2 μm. Therefore, if the height difference between the low protruding electrode 3a and the high protruding electrode 3b is set to be larger than 2 μm,
It is possible to reliably prevent the occurrence of unbonded defects.

【0032】実施の形態2.図3は本発明の実施の形態
2である半導体装置の基板への実装工程を順次示す製造
工程断面図である。この図において、8は基板5の電極
群に供給されたはんだめっきで8aは基板5の電極群の
最外周列及び行に配された電極6上にめっき高さが設計
値として約27μmとして供給された低いはんだめっ
き、8bは低いはんだめっき8aが供給される電極6よ
り内側に配された電極6上にめっき高さが設計値として
低いはんだめっき8aより約3μm高い約30μmで供
給された高いはんだめっきである。
Embodiment 2 FIG. 3A to 3D are sectional views of a manufacturing process sequentially showing the steps of mounting a semiconductor device on a substrate according to the second embodiment of the present invention. In this figure, 8 is solder plating supplied to the electrode group of the board 5, and 8a is a plating height of about 27 μm as a designed value on the electrodes 6 arranged in the outermost row and row of the electrode group of the board 5. The low solder plating 8b is provided on the electrode 6 disposed inside the electrode 6 to which the low solder plating 8a is supplied. The plating height is about 3 μm higher than the low solder plating 8a as a design value and is high at about 30 μm. Solder plating.

【0033】上述したように構成された半導体装置にお
いては、次のように基板5に実装される。まず、図3
(a)に示されたように、めっき法にて電極6上にはん
だめっき8を供給し、このはんだめっき8が供給された
電極6と突起電極3とが相対するように位置合わせす
る。次に、図3(b)に示されるように、基板5上にこ
のままの状態で基板の最外周に配された電極6上の低い
はんだめっき8aが突起電極に接触するまで、基板5と
パッケージ本体1とを接近させパッケージ本体1を搭載
し、はんだめっき8が溶融する温度例えば200℃まで
加熱した後冷却することによって、突起電極3とはんだ
めっき8とは電気的に接続されるとともに固着される。
The semiconductor device constructed as described above is mounted on the substrate 5 as follows. First, FIG.
As shown in (a), the solder plating 8 is supplied on the electrode 6 by a plating method, and the electrode 6 to which the solder plating 8 is supplied and the protruding electrode 3 are aligned so as to face each other. Next, as shown in FIG. 3 (b), the substrate 5 and the package 5 are packaged in this state on the substrate 5 until the low solder plating 8 a on the electrode 6 arranged on the outermost periphery of the substrate 5 contacts the protruding electrodes. By mounting the package main body 1 close to the main body 1 and heating the solder plating 8 to a temperature at which the solder plating 8 melts, for example, 200 ° C., and then cooling, the protruding electrodes 3 and the solder plating 8 are electrically connected and fixed. It

【0034】上述した本発明の実施の形態2である半導
体装置の実装方法では、パッケージ本体1に形成された
突起電極3の大きさ、高さは全て同じに設計されてお
り、上述した実施の形態1と異なる点は、基板5の電極
6に供給されるはんだめっき8の高さを変えた点で、最
外周の電極6上のめっき高さがその内側に配された電極
6上のめっき高さより低くなるように設計し形成した点
である。つまり、はんだめっき高さが設計値として低い
はんだめっき8aは約27μm、高いはんだめっき8b
は約30μmにそれぞれ設定されている。しかしなが
ら、実際のめっき工程では、めっき高さは通常±1μm
の範囲でばらつくから、はんだめっきの最高の高さと最
低の高さでは約2μmの差異が生じる。この差異を考慮
して低いはんだめっき8aと高いはんだめっき8bとの
めっき高さの差異を決定している。
In the semiconductor device mounting method according to the second embodiment of the present invention described above, the size and height of the projecting electrodes 3 formed on the package body 1 are all designed to be the same. The difference from the first embodiment is that the height of the solder plating 8 supplied to the electrode 6 of the substrate 5 is changed, and the plating height on the electrode 6 on the outermost periphery is the plating on the electrode 6 arranged inside thereof. This is a point designed and formed to be lower than the height. That is, the solder plating 8a having a low solder plating height as a design value is about 27 μm, and the solder plating 8a having a high solder plating height 8b is high.
Are set to about 30 μm, respectively. However, in the actual plating process, the plating height is usually ± 1 μm.
Therefore, there is a difference of about 2 μm between the maximum height and the minimum height of solder plating. In consideration of this difference, the difference in plating height between the low solder plating 8a and the high solder plating 8b is determined.

【0035】つまり、パッケージ本体1を基板5上に搭
載した後、加熱するとはんだが溶融することになり、パ
ッケージ本体1の搭載荷重によってはんだめっき8中に
突起電極3が押し込まれることとなる。このとき高いは
んだめっき8bは突起電極3と接触しているために濡れ
が生じる。この濡れが生じた部分では、高いはんだめっ
き8bの表面張力が作用し、それによりパッケージ本体
1と基板5とがさらに引き寄せられ、その結果、めっき
高さの低いはんだめっき8aと突起電極3とが接触して
濡れを生じる。ここで高さの低いはんだめっき8aが、
突起電極3と接触するためには、パッケージ本体1と基
板5とを低いはんだめっき8aと高いはんだめっき8b
とのはんだめっきの高さの差異である約3μm以上は接
近させねばならない。
That is, when the package body 1 is mounted on the substrate 5 and then heated, the solder is melted, and the protruding electrode 3 is pushed into the solder plating 8 by the mounting load of the package body 1. At this time, since the high solder plating 8b is in contact with the protruding electrode 3, wetting occurs. In the wetted portion, the high surface tension of the solder plating 8b acts to draw the package body 1 and the substrate 5 further, and as a result, the solder plating 8a having a low plating height and the protruding electrode 3 are separated from each other. Contact with them to cause wetting. Here, the solder plating 8a having a low height is
In order to make contact with the bump electrodes 3, the package body 1 and the substrate 5 are soldered with a low solder plating 8a and a high solder plating 8b.
The difference in the height of the solder plating from the above must be close to each other by about 3 μm or more.

【0036】従って、はんだめっき8のめっき高さのば
らつき量は2μmであるので、最外周に配された突起電
極3が、はんだめっき8と完全に接合していればその内
側に配された突起電極3は間違いなく完全に接合してい
ると判断できる。つまり、最外周に配された突起電極3
に未接合不良が発生しないように、パッケージ本体1を
基板5へ実装し、簡単な光学的検査によって最外周に配
された突起電極3の接合部のみを観察して評価し、未接
合不良のないことを確認すれば、外部から観察すること
ができない、最外周でない部分に配された突起電極3に
おいても接合部に未接合不良が発生することはない。さ
らに、電気検査によって短絡不良が無いことを確認すれ
ば実装接合部の状態が良好であると判定できる。
Therefore, since the variation of the plating height of the solder plating 8 is 2 μm, if the projection electrode 3 arranged on the outermost periphery is completely joined to the solder plating 8, the projections arranged inside the projection electrode 3 are formed. It can be judged that the electrode 3 is definitely bonded. That is, the protruding electrodes 3 arranged on the outermost periphery
In order to prevent unbonded defects from occurring, the package body 1 is mounted on the substrate 5, and a simple optical inspection is performed to observe and evaluate only the bonded parts of the protruding electrodes 3 arranged on the outermost periphery. If it is confirmed that there is no unbonded defect in the bonded portion even in the protruding electrode 3 which is not observable from the outside and is arranged in a portion other than the outermost periphery. Furthermore, if it is confirmed by an electrical inspection that there is no short circuit defect, it can be determined that the state of the mounting joint is good.

【0037】また、本発明の実施の形態2において、最
外周の突起電極3とこれに対応する電極6とをモニタ電
極とする場合、最外周の突起電極3と電極6上の低いは
んだめっき8aとは必ずしも良好な接合状態でなくと
も、接触している状態であればよく、この場合でもはん
だめっきのばらつき量より基板5と突起電極3間は接近
しているためその内側の電極6の高いはんだめっき8b
と突起電極3との接合部に未接合不良が発生することは
ない。
In the second embodiment of the present invention, when the outermost protruding electrode 3 and the corresponding electrode 6 are used as monitor electrodes, the outermost protruding electrode 3 and the low solder plating 8a on the electrode 6 are used. Does not necessarily need to be in a good joined state, but may be in a state of being in contact. Even in this case, since the substrate 5 and the projecting electrode 3 are closer to each other than the variation of the solder plating, the electrode 6 on the inside is high. Solder plating 8b
No unbonded defect will occur in the bonded portion between the bump electrode 3 and the bump electrode 3.

【0038】また、この実施の形態2においては、低い
はんだめっき8aと高いはんだめっき8bとのめっき高
さの差異をはんだめっきのばらつき量より大きく設定し
ているが、これは、突起電極3の形成工程においてその
高さのばらつきを考慮し、より確実に接合状態を判定す
るためであって理論的にはばらつき量と同じでよい。
Further, in the second embodiment, the difference in plating height between the low solder plating 8a and the high solder plating 8b is set to be larger than the variation of the solder plating. This is because the bonding state can be determined more reliably in consideration of the variation in the height in the forming process, and theoretically the same as the variation amount.

【0039】さらに、低いはんだめっき8aと高いはん
だめっき8bのめっき高さの差が、めっきのばらつき量
より小さくとも、わずかでも差異を生じさせることによ
って、最外周の低いはんだめっき8aはその内側に配さ
れた高いはんだめっき8bより接合しにくくなる。つま
り、はんだめっきの高さのばらつきはどの箇所において
も同様の確率によって生じるとすれば、最外周の低いは
んだめっき8aと突起電極3との間の未接合不良が確率
的に最も生じやすくなるため、最外周側に未接合不良が
生じていなければその内側も未接合不良が生じていない
と判断できる。
Further, even if the difference in the plating height between the low solder plating 8a and the high solder plating 8b is smaller than the variation amount of the plating, even a slight difference is generated, so that the solder plating 8a having the lowest outermost circumference is located inside thereof. It becomes more difficult to join than the high solder plating 8b arranged. In other words, if the variation in the height of the solder plating is caused by the same probability at any place, the unbonded defect between the solder plating 8a having the lowest outermost circumference and the protruding electrode 3 is stochastically most likely to occur. If there is no unbonded defect on the outermost peripheral side, it can be judged that no unbonded defect has occurred on the inner side as well.

【0040】なお、ここでは接合材としてのはんだをめ
っき法によって供給する場合について述べたが、蒸着や
スパッタなどについて供給する場合においては、供給す
る接合材のばらつきはほぼないものの、突起電極3の形
成工程において突起電極の高さのばらつきによって未接
合不良が発生する場合が考えられるので、上述した実施
の形態1で示したように最外周の突起電極3の高さを低
くしたり、実施の形態2で示したように最外周の電極6
の接合材の高さを低くすることによって、実施の形態1
及び2で示したものと同様の効果が得られる。
Although the case where the solder as the bonding material is supplied by the plating method has been described here, in the case of supplying vapor deposition, sputtering, etc., although there is almost no variation in the bonding material to be supplied, the protrusion electrode 3 Since there is a possibility that unbonding failure may occur due to the height variation of the protruding electrodes in the forming process, the height of the outermost protruding electrodes 3 may be reduced as described in the first embodiment, or the unbonded defects may be reduced. The outermost electrode 6 as shown in the form 2
Embodiment 1 by reducing the height of the joining material of
The same effects as those shown in 2 and 2 are obtained.

【0041】実施の形態3.図4は本発明の実施の形態
3である半導体装置を示す側面図及び上面図である。こ
の発明の実施の形態3である半導体装置と従来の半導体
装置との異なる点は、突起電極3が配された面内で、か
つパッケージ本体1の外周に対して鉛直方向から観察す
るときに、突起電極3の一部又は全部が観察可能となる
ように外周部から内周部に向かうにつれて突起電極3が
一定方向にずらして配列されている点であって、その他
はほぼ従来の技術と同じである。
Embodiment 3 4A and 4B are a side view and a top view showing a semiconductor device according to a third embodiment of the present invention. The difference between the semiconductor device according to the third embodiment of the present invention and the conventional semiconductor device is that when observed from the vertical direction with respect to the outer periphery of the package body 1 in the plane in which the protruding electrodes 3 are arranged, The protruding electrodes 3 are arranged so as to be displaced in a certain direction from the outer peripheral portion toward the inner peripheral portion so that part or all of the protruding electrodes 3 can be observed. Is.

【0042】上述したように構成された半導体装置は、
上述した実施の形態1で示したものと全く同じ方法で基
板5上に実装されることとなる。図5はこの半導体装置
を基板5に実装した場合の電極接合部を示す側面図であ
る。図中円内で示される箇所Aは突起電極3と基板5上
のはんだペースト7とに濡れが生じることによってフィ
レットが形成された接合状態が良好な接合部、Cは突起
電極3とはんだペースト7とが濡れを生じず、フィレッ
トが形成されなかった不完全な接合部を示す。
The semiconductor device configured as described above is
It is mounted on the substrate 5 by the same method as that shown in the first embodiment. FIG. 5 is a side view showing an electrode joint portion when this semiconductor device is mounted on the substrate 5. A portion A indicated by a circle in the drawing is a joint portion in which a fillet is formed due to wetting between the protruding electrode 3 and the solder paste 7 on the substrate 5, and C is a good joint state, and C is the protruding electrode 3 and the solder paste 7. Indicates an incomplete joint where no fillet was formed without wetting.

【0043】このように突起電極3を外周部より内周部
に向かうにつれて一定方向にずらして配列させることに
よって、外部より内周側に配された突起電極3の側面を
観察することができるので画像認識、目視等の簡単な光
学的外観検査によってフィレットの形成の有無が確認で
き、従来からの電気的な検査では発見しにくかった不完
全な接合部Cを容易に発見でき、半導体装置としての信
頼性が向上する。また、内側に配された突起電極の接合
状態をパッケージ本体1の外周に対して鉛直方向からの
観察によって発見できるため、画像認識に用いられるカ
メラの位置が固定でき、簡単な検査装置を用いて、接合
状態の良否を判定できる。
By thus arranging the protruding electrodes 3 so as to be displaced in a constant direction from the outer peripheral portion toward the inner peripheral portion, the side surface of the protruding electrode 3 arranged on the inner peripheral side from the outside can be observed. The presence or absence of fillet formation can be confirmed by a simple optical appearance inspection such as image recognition and visual inspection, and an incomplete joint C, which was difficult to find by conventional electrical inspection, can be easily found. Improves reliability. Further, since the bonding state of the protruding electrodes arranged inside can be found by observing the outer circumference of the package body 1 from the vertical direction, the position of the camera used for image recognition can be fixed, and a simple inspection device can be used. It is possible to judge the quality of the joined state.

【0044】なお、上述した本発明の実施の形態におい
ては、接合材としてはんだを用いたものについて説明し
たが、これに限るものではなく、導電性樹脂、異方性導
電樹脂、金属フィラー入り接着剤等導電性を有し、半導
体装置を基板5上に固着できるものであればよい。
In the above-mentioned embodiment of the present invention, the solder is used as the bonding material, but the bonding material is not limited to this, and the conductive resin, the anisotropic conductive resin, and the adhesive containing metal filler are used. Any material having conductivity such as an agent and capable of fixing the semiconductor device on the substrate 5 may be used.

【0045】[0045]

【発明の効果】本発明の請求項1記載の半導体装置にお
いては、突起電極群の最外側の行又は列に配された突起
電極の高さを、その内側に配された突起電極の高さより
低く形成しているので、この半導体装置を基体に接合す
る場合、未接合不良が最外側に集中する。従って外部か
らの簡単な光学的検査によって、半導体装置と基体との
実装接合部の良否を判定することができる半導体装置の
構造を提供することができるという効果を有する。
In the semiconductor device according to the first aspect of the present invention, the height of the protruding electrodes arranged in the outermost row or column of the protruding electrode group is more than the height of the protruding electrodes arranged inside thereof. Since the semiconductor device is formed low, unbonded defects are concentrated on the outermost side when the semiconductor device is bonded to the base. Therefore, there is an effect that it is possible to provide a structure of a semiconductor device capable of judging the quality of the mounting joint between the semiconductor device and the base body by a simple optical inspection from the outside.

【0046】さらに本発明の請求項2記載の半導体装置
においては、突起電極群の最外側の行又は列に配された
突起電極の高さがその内側に配された突起電極の高さよ
り低く、その高さの差が供給される接合材の高さのばら
つき量より大きく形成されているので、この半導体装置
を基体に接合する場合、電極上に供給される接合材にば
らつきが生じても、そのばらつき量より低い高さの最外
側の突起電極の実装接合部に未接合不良が発生していな
ければ、その内側に配された突起電極の実装接合部では
未接合不良が確実に発生していないと判定することがで
きる。従って、最外側に配された実装接合部を光学的検
査によって評価すれば、半導体装置と基体との実装接合
部の良否を判定することができるという効果を有する。
Further, in the semiconductor device according to claim 2 of the present invention, the height of the bump electrodes arranged in the outermost row or column of the bump electrode group is lower than the height of the bump electrodes arranged inside thereof. Since the difference in the height is formed to be larger than the variation amount of the height of the bonding material to be supplied, when the semiconductor device is bonded to the base body, even if the bonding material supplied to the electrodes varies, If there is no unbonded defect in the mounting joint of the outermost protruding electrode whose height is lower than the variation amount, unbonded defect is surely generated in the mounted joint of the protruding electrode arranged inside it. It can be determined that there is no. Therefore, if the mounting joint portion arranged on the outermost side is evaluated by an optical inspection, it is possible to determine the quality of the mounting joint portion between the semiconductor device and the base body.

【0047】本発明の請求項3記載の半導体装置におい
ては、めっき法によって供給される接合材の高さのばら
つき量は現在の技術では2μmであるので、最外側に配
される突起電極とその内側に配される突起電極の高さの
差を2μmより大きくすれば最外側に配される突起電極
の接合状態を観察し、未接合不良が発生していなけれ
ば、その内側も未接合不良が発生していないと判定でき
るという効果を有する。
In the semiconductor device according to the third aspect of the present invention, the amount of variation in the height of the bonding material supplied by the plating method is 2 μm in the present technology, so that the protruding electrode arranged on the outermost side and If the difference in height of the protruding electrodes arranged on the inner side is made larger than 2 μm, the bonding state of the protruding electrodes arranged on the outermost side is observed. It has the effect that it can be determined that it has not occurred.

【0048】本発明の請求項4記載の半導体装置の実装
方法においては、基体の電極上に供給する接合材の高さ
を、電極群の最外側に配された電極よりその内側に配さ
れた電極より低くすることによって、最外側の電極が最
も未接合不良の発生する可能性が高くなるため、この箇
所に未接合不良が発生していなければその内側は未接合
不良が発生していないこととなる。従って、外部より光
学的検査によって、最外側の電極の接合状態の良否を判
定することによって半導体装置と基板との実装接合状態
が評価できるため、検査コストを抑制することができる
という効果を有する。
In the method for mounting a semiconductor device according to a fourth aspect of the present invention, the height of the bonding material supplied onto the electrodes of the base is arranged inside the electrodes arranged on the outermost side of the electrode group. By making it lower than the electrode, the possibility of the most unbonded defect occurring at the outermost electrode increases, so if there is no unbonded defect at this location, then there should be no unbonded defect inside it. Becomes Therefore, it is possible to evaluate the mounting bonding state of the semiconductor device and the substrate by judging the quality of the bonding state of the outermost electrode by an optical inspection from the outside, and thus it is possible to suppress the inspection cost.

【0049】さらに、本発明の請求項5記載の半導体装
置の実装方法においては、電極群の最外側の電極上の接
合材の高さを、その内側の電極上の接合材の高さより接
合材の高さのばらつき量より低く形成したので、最外側
の電極に未接合不良が発生していなければ、接合材の高
さにばらつきが生じてもより確実にその内側の電極に未
接合不良が発生することはなく、最外側の電極の接合状
態を外部からの光学的検査によって判定することによっ
て、半導体装置と基体の実装接合状態を評価できるとい
う効果を有する。
Furthermore, in the method for mounting a semiconductor device according to claim 5 of the present invention, the height of the bonding material on the outermost electrodes of the electrode group is set to be higher than the height of the bonding material on the electrodes inside thereof. Since it is formed to be lower than the amount of variation in height of the bonding material, if there is no unbonded defect in the outermost electrode, even if there is variation in the height of the bonding material, the unbonded defect in the inner electrode will be more reliable. It is possible to evaluate the mounting bonding state of the semiconductor device and the base by determining the bonding state of the outermost electrode by an optical inspection from the outside, which does not occur.

【0050】また、本発明の請求項6記載の半導体装置
の実装方法においては、接合材をめっき法によって電極
上に供給するが、現在の技術において、そのばらつき量
は2μmであるので、電極群の最外側の電極上の接合材
の高さとその内側の電極上の接合材の高さとの差を2μ
mより大きくすれば、最外側の電極の接合状態を外部か
らの光学的検査によって、半導体装置と基体の実装接合
状態を評価できるという効果を有する。
Further, in the method for mounting a semiconductor device according to claim 6 of the present invention, the bonding material is supplied onto the electrodes by a plating method. However, in the present technology, the variation amount is 2 μm, so the electrode group The difference between the height of the bonding material on the outermost electrode and the height of the bonding material on the inner electrode is 2μ
If it is made larger than m, there is an effect that the bonding state of the outermost electrode can be evaluated by an optical inspection from the outside to evaluate the mounting bonding state of the semiconductor device and the substrate.

【0051】本発明の請求項7記載の半導体装置として
は、突起電極群が配された面内で、かつ突起電極群の最
外側に配された突起電極の整列方向に対して鉛直方向よ
り観察するときに、その内側に配されたすべての突起電
極それぞれの少なくとも一部分が観察できるように配さ
れている。従って、この半導体装置を基体に実装接合し
た場合、外部からの光学的検査によって簡単に接合状態
を評価できる半導体装置の構造が提供できるという効果
を有する。
According to a seventh aspect of the present invention, the semiconductor device is observed from the vertical direction with respect to the alignment direction of the projection electrodes arranged on the plane where the projection electrode group is arranged and on the outermost side of the projection electrode group. At this time, at least a part of each of the protruding electrodes arranged inside thereof is arranged so that it can be observed. Therefore, when this semiconductor device is mounted and bonded to the base, there is an effect that it is possible to provide a structure of the semiconductor device in which the bonding state can be easily evaluated by an optical inspection from the outside.

【0052】また、本発明の請求項8記載の半導体装置
の実装方法においては、請求項1〜3のいずれかに記載
の半導体装置を基板に実装接合するので、上述したよう
に実装後の検査において、外部からの光学的検査によっ
て簡単に接合状態が評価できるという効果を有する。
Further, in the method for mounting a semiconductor device according to claim 8 of the present invention, since the semiconductor device according to any one of claims 1 to 3 is mounted and bonded to a substrate, the inspection after mounting is performed as described above. In, there is an effect that the bonding state can be easily evaluated by an optical inspection from the outside.

【0053】また、本発明の請求項9記載の半導体装置
の実装方法においては、請求項7記載の半導体装置を基
板に実装接合するので、上述したように実装後の検査に
おいて、外部からの光学的検査によって簡単に接合状態
が評価できるという効果を有する。
Further, in the method for mounting a semiconductor device according to claim 9 of the present invention, since the semiconductor device according to claim 7 is mounted and bonded to the substrate, as described above, in the inspection after mounting, it is possible to perform optical inspection from the outside. This has the effect that the joining state can be easily evaluated by a physical inspection.

【0054】本発明の請求項10記載の半導体装置実装
部の検査方法においては、請求項4〜6、8、9のいず
れか記載の半導体装置の実装方法によって、半導体装置
が基体に実装された後、電気的検査によって短絡不良
を、電極群の最外側に配された電極接合部のみを光学的
検査を行うことによって未接合不良を評価するようにし
たので、検査が簡単になり検査時間が短縮できるととも
に、検査のコストを抑えることができるという効果を有
する。
In the method for inspecting a semiconductor device mounting portion according to claim 10 of the present invention, the semiconductor device is mounted on a substrate by the method for mounting a semiconductor device according to any one of claims 4 to 6, 8 and 9. Later, electrical inspection was used to evaluate short-circuit defects, and unbonded defects were evaluated by performing optical inspection only on the electrode joints located on the outermost side of the electrode group. There is an effect that the cost can be shortened and the inspection cost can be suppressed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の実施の形態1である半導体装置を示
す断面図である。
FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

【図2】 本発明の実施の形態1である半導体装置の基
体への実装工程を示す実装工程断面図である。
FIG. 2 is a mounting step sectional view showing a step of mounting the semiconductor device according to the first embodiment of the present invention on a substrate.

【図3】 本発明の実施の形態2である半導体装置の基
体への実装工程を示す実装工程断面図である。
FIG. 3 is a mounting step sectional view showing a step of mounting a semiconductor device on a base body according to a second embodiment of the present invention.

【図4】 本発明の実施の形態3である半導体装置を示
す断面図及び上面図である。
FIG. 4 is a sectional view and a top view showing a semiconductor device according to a third embodiment of the present invention.

【図5】 本発明の実施の形態3である半導体装置の基
体への実装接合部を示す側面図である。
FIG. 5 is a side view showing a mounting joint portion to a base of a semiconductor device according to a third embodiment of the present invention.

【図6】 従来の半導体装置を示す斜視図である。FIG. 6 is a perspective view showing a conventional semiconductor device.

【図7】 従来の半導体装置を示す断面図である。FIG. 7 is a cross-sectional view showing a conventional semiconductor device.

【図8】 従来の半導体装置の基体への実装工程を示す
実装工程断面図である。
FIG. 8 is a sectional view of a mounting process showing a conventional mounting process of a semiconductor device on a substrate.

【図9】 従来の半導体装置の基体への実装接合部を示
す側面図である。
FIG. 9 is a side view showing a mounting joint portion of a conventional semiconductor device to a base body.

【符号の説明】[Explanation of symbols]

1 パッケージ本体、3 突起電極、3a 低い突起電
極、3b 高い突起電極、5 基板、6 電極、7 は
んだペースト、8 はんだめっき、8a 低いはんだめ
っき、8b 高いはんだめっき。
1 package body, 3 protruding electrodes, 3a low protruding electrodes, 3b high protruding electrodes, 5 substrates, 6 electrodes, 7 solder paste, 8 solder plating, 8a low solder plating, 8b high solder plating.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 安達 照 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Teru Adachi 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd.

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 基体上に形成された電極と接合材を介し
て電気的に接合される突起電極が、行及び列方向に複数
個配されて構成された突起電極群を有する半導体装置に
おいて、上記突起電極群の最外側の行又は列に配された
上記突起電極の高さが、その内側に配された上記突起電
極の高さより低いことを特徴とする半導体装置。
1. A semiconductor device having a projecting electrode group configured by arranging a plurality of projecting electrodes electrically connected to an electrode formed on a substrate through a bonding material in a row and a column direction, A semiconductor device, wherein the height of the protruding electrodes arranged in the outermost row or column of the protruding electrode group is lower than the height of the protruding electrodes arranged inside thereof.
【請求項2】 基体上に形成された電極上に供給される
接合材を介して電気的に接合される突起電極が、行及び
列方向に複数個配されて構成された突起電極群を有する
半導体装置において、上記突起電極群の最外側の行又は
列に配された上記突起電極の高さが、その内側に配され
た上記突起電極の高さより低く、その高さの差が上記供
給される接合材の高さのばらつき量より大きいことを特
徴とする半導体装置。
2. A projection electrode group formed by arranging a plurality of projection electrodes electrically connected to each other through a bonding material supplied on an electrode formed on a substrate in the row and column directions. In the semiconductor device, the height of the protruding electrodes arranged in the outermost row or column of the protruding electrode group is lower than the height of the protruding electrodes arranged inside thereof, and the difference in height is supplied. The semiconductor device is characterized in that it is larger than the variation in height of the bonding material.
【請求項3】 基体上に形成された電極上にめっき法に
より供給される接合材を介して電気的に接合される突起
電極が、行及び列方向に複数個配されて構成された突起
電極群を有する半導体装置において、上記突起電極群の
最外側の行又は列に配された上記突起電極の高さが、そ
の内側に配された上記突起電極の高さより低く、その高
さの差が2μmより大きいことを特徴とする半導体装
置。
3. A projection electrode formed by arranging a plurality of projection electrodes electrically connected to a electrode formed on a substrate through a bonding material supplied by a plating method in row and column directions. In a semiconductor device having a group, the height of the protruding electrodes arranged in the outermost row or column of the protruding electrode group is lower than the height of the protruding electrodes arranged inside thereof, and the difference in height is A semiconductor device having a size larger than 2 μm.
【請求項4】 電極が行及び列方向に複数個配されて構
成された電極群が形成された基体の上記電極群の最外側
の行又は列に配された電極上に供給される接合材の高さ
が、その内側に配された電極上に供給される接合材の高
さより低くなるように接合材を上記電極群へ供給する工
程と、上記接合材が配された上記基体の電極と、突起電
極が行及び列方向に複数個配されて構成された突起電極
群を有する半導体装置の突起電極とがそれぞれ対向する
ように位置合わせをした後、上記電極群の最外側の行又
は列に配された電極上の高さの低い接合材が上記突起電
極と接触するまで上記半導体装置と上記基体とを接近さ
せ、上記接合材を介して上記基体上の電極群と上記半導
体装置の突起電極群とを接触させ、上記基体に上記半導
体装置を接合する工程とを備えた半導体装置の実装方
法。
4. A bonding material supplied onto the electrodes arranged in the outermost row or column of the electrode group of the substrate on which the electrode group formed by arranging a plurality of electrodes in the row and column directions is formed. A step of supplying a bonding material to the electrode group so that the height of the bonding material is lower than the height of the bonding material supplied on the electrode arranged inside the electrode, and the electrode of the substrate on which the bonding material is arranged. , The outermost row or column of the electrode group after alignment so that the bump electrodes of the semiconductor device having the bump electrode group formed by arranging a plurality of bump electrodes in the row and column directions face each other. The semiconductor device and the base are brought close to each other until the low-height bonding material on the electrode arranged in contact with the bump electrode contacts the electrode group on the base and the projection of the semiconductor device via the bonding material. A process of contacting the electrode group and joining the semiconductor device to the substrate. A method for mounting a semiconductor device, comprising:
【請求項5】 基体の電極群の最外側の行又は列に配さ
れた電極上に供給される接合材の高さと、その内側に配
された電極上に供給される接合材の高さとの差が、接合
材を供給する際に生じる接合材の高さのばらつき量より
大きくなるように接合材を供給することを特徴とする請
求項4記載の半導体装置の実装方法。
5. The height of the bonding material supplied on the electrodes arranged in the outermost rows or columns of the electrode group of the base body and the height of the bonding material supplied on the electrodes arranged inside thereof. 5. The method for mounting a semiconductor device according to claim 4, wherein the bonding material is supplied so that the difference is larger than the variation amount of the height of the bonding material generated when the bonding material is supplied.
【請求項6】 接合材をめっき法によって電極上に供給
し、基体の電極群の最外側の行又は列に配された電極上
に供給される接合材の高さと、その内側に配された電極
上に供給される接合材の高さとの差が2μmより大きく
なるように接合材をめっき法にて供給することを特徴と
する請求項4記載の半導体装置の実装方法。
6. The bonding material is supplied onto the electrodes by a plating method, and the height of the bonding material supplied onto the electrodes arranged on the outermost row or column of the electrode group of the substrate and the height inside the bonding material are arranged inside the bonding material. 5. The method for mounting a semiconductor device according to claim 4, wherein the bonding material is supplied by a plating method so that the difference from the height of the bonding material supplied on the electrodes is larger than 2 μm.
【請求項7】 基体上に形成された電極と接合材を介し
て電気的に接合される突起電極が、行及び列方向に複数
個配されて構成された突起電極群を有する半導体装置に
おいて、この突起電極群が配された面内で、かつ上記突
起電極群の最外側に配された突起電極の整列方向に対し
て鉛直方向から観察するときに、その内側に配されたす
べての突起電極それぞれの少なくとも一部分が観察可能
なように上記突起電極を配した突起電極群を有すること
を特徴とする半導体装置。
7. A semiconductor device having a projecting electrode group formed by arranging a plurality of projecting electrodes electrically connected to electrodes formed on a substrate through a bonding material in row and column directions, When observing from the vertical direction with respect to the alignment direction of the protruding electrodes arranged on the outermost side of the protruding electrode group in the plane on which the protruding electrode group is arranged, all the protruding electrodes arranged inside the protruding electrode group A semiconductor device having a protruding electrode group in which the protruding electrodes are arranged so that at least a part of each can be observed.
【請求項8】 電極が行及び列方向に複数個配されて構
成された電極群が形成された基体の上記それぞれの電極
上に接合材を供給する工程と、接合材が供給された上記
基体の電極と、請求項1〜3のいずれかに記載の半導体
装置の突起電極とがそれぞれ対向するように位置合わせ
をした後、上記突起電極群の最外側の行又は列に配され
た高さの低い突起電極が上記接合材と接触するまで上記
半導体装置と上記基体とを接近させ、上記接合材を介し
て上記基体上の電極群と上記半導体装置の突起電極群と
を接触させ、上記基体に上記半導体装置を接合する工程
とを備えたことを特徴とする半導体装置の実装方法。
8. A step of supplying a bonding material onto each of the electrodes of a base body on which an electrode group formed by arranging a plurality of electrodes in the row and column directions is formed, and the base body to which the bonding material is supplied. And the protrusion electrodes of the semiconductor device according to any one of claims 1 to 3 are aligned so as to face each other, and then the heights arranged in the outermost rows or columns of the protrusion electrode group. The semiconductor device and the base body are brought close to each other until the protruding electrode having a low contact angle is brought into contact with the bonding material, and the electrode group on the base body and the protruding electrode group of the semiconductor device are brought into contact with each other via the bonding material. And a step of joining the semiconductor device to each other.
【請求項9】 電極が行及び列方向に複数個配されて構
成された電極群が形成された基体の上記それぞれの電極
上に接合材を供給する工程と、接合材が供給された上記
基体の電極と、請求項7記載の半導体装置の突起電極と
がそれぞれ対向するように位置合わせをした後、上記突
起電極群の最外側の行又は列に配された高さの低い突起
電極が上記接合材と接触するまで上記半導体装置と上記
基体とを接近させ、上記接合材を介して上記基体上の電
極群と上記半導体装置の突起電極群とを接触させ、上記
基体に上記半導体装置を接合する工程とを備えたことを
特徴とする半導体装置の実装方法。
9. A step of supplying a bonding material onto each of the electrodes of a base body on which an electrode group formed by arranging a plurality of electrodes in the row and column directions is formed, and the base body to which the bonding material is supplied. And the protruding electrodes of the semiconductor device according to claim 7 are aligned so as to face each other, and the protruding electrodes of low height arranged in the outermost row or column of the protruding electrode group are The semiconductor device and the base body are brought close to each other until they come into contact with the bonding material, and the electrode group on the base body and the protruding electrode group of the semiconductor device are brought into contact with each other via the bonding material to bond the semiconductor device to the base body. A method of mounting a semiconductor device, comprising:
【請求項10】 請求項4〜6、8、9のいずれかに記
載の半導体装置の実装方法によって、上記半導体装置が
基体へ実装された後の半導体装置実装部の検査方法にお
いて、突起電極と電極との接合状態の電気的検査と、突
起電極群及び電極群の最外側に配された突起電極と電極
との接合状態の光学的検査とを行うことによって実装部
の評価を行うことを特徴とする半導体装置実装部の検査
方法。
10. A method for inspecting a semiconductor device mounting portion after the semiconductor device is mounted on a substrate by the method for mounting a semiconductor device according to any one of claims 4 to 6, 8 and 9, wherein a protruding electrode is used. The mounting part is evaluated by performing an electrical inspection of the bonding state with the electrodes and an optical inspection of the bonding state between the protruding electrode group and the protruding electrodes arranged on the outermost side of the electrode group and the electrode. Inspection method of semiconductor device mounting part.
JP34068595A 1995-12-27 1995-12-27 Semiconductor device, method of mounting the same, and method of inspecting the mounted portion Expired - Fee Related JP3325755B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34068595A JP3325755B2 (en) 1995-12-27 1995-12-27 Semiconductor device, method of mounting the same, and method of inspecting the mounted portion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34068595A JP3325755B2 (en) 1995-12-27 1995-12-27 Semiconductor device, method of mounting the same, and method of inspecting the mounted portion

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Publication Number Publication Date
JPH09181124A true JPH09181124A (en) 1997-07-11
JP3325755B2 JP3325755B2 (en) 2002-09-17

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ID=18339335

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Country Status (1)

Country Link
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007023747A1 (en) * 2005-08-23 2007-03-01 Rohm Co., Ltd. Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
JP2007059547A (en) * 2005-08-23 2007-03-08 Rohm Co Ltd Semiconductor chip and method of manufacturing semiconductor chip
JP2007059548A (en) * 2005-08-23 2007-03-08 Rohm Co Ltd Semiconductor chip and method of manufacturing semiconductor chip
JP2017028156A (en) * 2015-07-24 2017-02-02 新光電気工業株式会社 Mounting structure and manufacturing method therefor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007023747A1 (en) * 2005-08-23 2007-03-01 Rohm Co., Ltd. Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
JP2007059547A (en) * 2005-08-23 2007-03-08 Rohm Co Ltd Semiconductor chip and method of manufacturing semiconductor chip
JP2007059548A (en) * 2005-08-23 2007-03-08 Rohm Co Ltd Semiconductor chip and method of manufacturing semiconductor chip
JP4723312B2 (en) * 2005-08-23 2011-07-13 ローム株式会社 Semiconductor chip and semiconductor device
US8653657B2 (en) 2005-08-23 2014-02-18 Rohm Co., Ltd. Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device
JP2017028156A (en) * 2015-07-24 2017-02-02 新光電気工業株式会社 Mounting structure and manufacturing method therefor

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