JPH1116965A - Characteristics inspection method of semiconductor wafer - Google Patents

Characteristics inspection method of semiconductor wafer

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Publication number
JPH1116965A
JPH1116965A JP16247797A JP16247797A JPH1116965A JP H1116965 A JPH1116965 A JP H1116965A JP 16247797 A JP16247797 A JP 16247797A JP 16247797 A JP16247797 A JP 16247797A JP H1116965 A JPH1116965 A JP H1116965A
Authority
JP
Japan
Prior art keywords
wafer
tape
electrode
semiconductor wafer
attached
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16247797A
Other languages
Japanese (ja)
Inventor
Yasumasa Ishikawa
恭巨 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP16247797A priority Critical patent/JPH1116965A/en
Publication of JPH1116965A publication Critical patent/JPH1116965A/en
Pending legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of crack of a water, when a semiconductor wafer is handled. SOLUTION: A p-n junction separation trench 2 separating a p-n junction 4 from a bonding pad electrode 3 side of a wafer 1 is formed. A diebond side electrode 5 is mounted on a tape 9 having adhesive agent on which a gold wire 10 is stuck, and the wafer 1 is stuck on the diebond side electrode 5. Since the tape 9 becomes a retaining member, crackings of the wafer is hardly generated, when the p-n junction separation trench 2 is formed deep. The diebond side electrode 5 is electrically led out via the gold wire 10, so that the characteristics of the respective chips on a semiconductor wafer can be measured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体ウエハの特
性検査方法、特にウエハの割れを減少させることができ
る検査方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting characteristics of a semiconductor wafer, and more particularly to an inspection method capable of reducing cracks in a wafer.

【0002】[0002]

【従来の技術】図3を参照して、従来のLED等のチッ
プの形成プロセスを説明する。p型半導体とn型半導体
の2層構造からなる厚さ300μm前後のウエハ1(一
方の面がp型、他方の面がn型)の片側にワイヤボンド
を前提としたボンディングパッド電極3を、他方にラン
プ筐体等に銀ペーストで接着(ダイボンド)することを
前提とした電極5を形成する。
2. Description of the Related Art A conventional process for forming a chip such as an LED will be described with reference to FIG. A bonding pad electrode 3 based on wire bonding is provided on one side of a wafer 1 having a thickness of about 300 μm (one surface is p-type and the other surface is n-type) having a two-layer structure of a p-type semiconductor and an n-type semiconductor. On the other hand, the electrode 5 is formed on the premise that it is bonded (die-bonded) to a lamp housing or the like with a silver paste.

【0003】ボンディングパッド電極3はワイヤボンド
に適した大きさのドット電極とし、ダイボンド側電極5
は、ウエハ1全面を覆った全面電極、あるいは部分電極
の場合でもウエハ1全面でつながっていて目がチップサ
イズよりも小さいメッシュ状電極とドット電極の組み合
わせにすることが一般に行われている。
The bonding pad electrode 3 is a dot electrode having a size suitable for wire bonding, and the die bonding side electrode 5
In general, a combination of a mesh electrode and a dot electrode, which are connected to the entire surface of the wafer 1 and have eyes smaller than the chip size, are generally used even in the case of a whole electrode covering the entire surface of the wafer 1 or a partial electrode.

【0004】このウエハ1上に形成した個々のチップの
電気的光学的特性を測定するためには、チップサイズに
対応した寸法でウエハ1のボンディングパッド形成面側
からダイシングにより機械的にp/n 接合4を分離した後
に、加工歪み除去のための化学的エッチングを行った状
態を準備する必要がある。
In order to measure the electrical and optical characteristics of the individual chips formed on the wafer 1, p / n is mechanically diced from the bonding pad forming surface side of the wafer 1 to a size corresponding to the chip size. After the junction 4 is separated, it is necessary to prepare a state in which chemical etching is performed to remove processing strain.

【0005】p/n 接合分離溝2の深さはウエハ1のp/n
接合4を分離する側の表面からp/n接合4までの距離よ
り大きくなければならないが、一方この接合分離したウ
エハ1を単独でハンドリングするためには、少なくとも
残り代として100μm程度残す必要がある。
The depth of the p / n junction separation groove 2 is the p / n of the wafer 1
The distance must be greater than the distance from the surface on the side where the bond 4 is separated to the p / n bond 4. On the other hand, in order to handle the bonded and separated wafer 1 alone, it is necessary to leave at least about 100 μm as the remaining margin. .

【0006】このウエハ1の特性を検査するには、図4
に示すように、ウエハ1を単独でハンドリングし、ダイ
ボンド側面の電極5を金属板(テストステージ7)に接
触させ電気的接触を確保し、かつ他方ボンディングパッ
ド側面の電極3にプローブ針6を接触させて電気的接続
を確保することにより、チップ1個ずつの電気的光学的
特性を測定し合否判定する。これをウエハ1上に形成し
てあるチップの全数あるいは予め決めた抜取頻度で繰り
返す。その後、個々のチップに分断するため、p/n 接合
分離溝2に沿ってダイボンド側の面からケガキ傷を形成
し機械的に割るスクライブ法を用いた加工を行う。
In order to inspect the characteristics of the wafer 1, FIG.
As shown in (1), the wafer 1 is handled independently, the electrode 5 on the side surface of the die bond is brought into contact with the metal plate (test stage 7) to secure electrical contact, and the probe needle 6 is brought into contact with the electrode 3 on the side surface of the bonding pad. In this way, the electrical connection is ensured, so that the electrical and optical characteristics of each chip are measured and pass / fail judgment is made. This is repeated with the total number of chips formed on the wafer 1 or with a predetermined extraction frequency. Thereafter, in order to divide the chips into individual chips, scribing is formed along the p / n junction separation groove 2 from the surface on the die bond side, and processing is performed using a scribing method of mechanically dividing.

【0007】[0007]

【発明が解決しようとする課題】従来技術ではこのよう
なスクライブ法によって個々のチップに分断する工程に
おいて、p/n 接合分離溝2とウエハ1の劈開方向が一致
しない場合に残り代の大きさに比例してチップ形状が悪
化する( 設計した位置で割れずに別の位置で割れてしま
う) という欠点があった。
In the prior art, in the step of dividing into individual chips by such a scribe method, when the cleavage direction of the p / n junction separation groove 2 and the wafer 1 do not match, the size of the remaining margin is increased. However, there is a disadvantage that the chip shape is deteriorated in proportion to (the crack is broken at another position without breaking at the designed position).

【0008】一方、残り代を薄くするとウエハ1の機械
的強度が低下して、ウエハハンドリング中にウエハ割れ
を生じ、作業効率を著しく低下させる原因となる。本発
明は、チップ形状を安定化させるためにp/n 接合分離溝
2の残り代を薄くしたウエハ1に対して、ウエハの割れ
を減少させることが可能な電気的光学的特性検査の方法
を提供するものである。
On the other hand, if the remaining margin is made thinner, the mechanical strength of the wafer 1 is reduced, and the wafer is cracked during wafer handling, resulting in a significant decrease in work efficiency. The present invention provides a method of inspecting the electrical and optical characteristics of a wafer 1 in which the remaining portion of the p / n junction separation groove 2 is reduced in order to stabilize the chip shape and which can reduce the crack of the wafer. To provide.

【0009】[0009]

【課題を解決するための手段】本発明の半導体ウエハの
特性検査方法は、一方の面にボンディングパッド電極、
他方の面にダイボンド側電極が形成され、前記一方の面
からはチップサイズに対応した寸法で分断する溝が形成
され、前記他方の面側には残り代が残されている半導体
ウエハの特性検査方法において、粘着材を塗布したテー
プに導電性金属ワイヤを貼り、そのテープを前記半導体
ウエハの前記他方の面に貼ることで、前記他方の面側の
電極の電気的接触を前記導電性金属ワイヤで取るもので
ある。このように、テープをウエハに貼り付けることに
より、ウエハ単独状態よりも機械的強度が増加する。
According to the method for inspecting the characteristics of a semiconductor wafer according to the present invention, a bonding pad electrode,
A die-bonding electrode is formed on the other surface, a groove is formed from the one surface so as to be divided at a size corresponding to a chip size, and a characteristic inspection of a semiconductor wafer is left on the other surface. In the method, an electrically conductive metal wire is attached to a tape coated with an adhesive material, and the tape is attached to the other surface of the semiconductor wafer, thereby making electrical contact of the electrode on the other surface side to the conductive metal wire. What to take in. As described above, by attaching the tape to the wafer, the mechanical strength is increased as compared with the case of the wafer alone.

【0010】また、粘着材を紫外線を照射することによ
り粘着度が弱くなる方向へ変化するものとすることによ
り、特性測定の後、ウエハに不必要な力が加わらないよ
うテープ粘着材に紫外線を照射し粘着力を低下させてウ
エハをテープから取り外すことができる。さらに、テー
プをドーナツ形状の金属フレームに貼り付けることによ
り取り扱い自体が容易になるとともに、電気的な引き出
しも容易になる。
In addition, by irradiating the adhesive with ultraviolet light, the adhesive is changed in a direction in which the adhesive strength is weakened, so that after the characteristic measurement, ultraviolet light is applied to the tape adhesive so that an unnecessary force is not applied to the wafer. Irradiation reduces the adhesive strength and allows the wafer to be removed from the tape. Further, by attaching the tape to the donut-shaped metal frame, the handling itself is facilitated, and the electrical extraction is also facilitated.

【0011】[0011]

【発明の実施の形態】本発明では、図1に示すように、
厚さ300μm前後のウエハ1に対し、残り代が20〜
50μmとなるように、p/n 接合分離溝2を深く形成す
る。一方、導電性金属ワイヤとして金ワイヤ10を用
い、粘着材として紫外線を照射することにより粘着度が
弱くなる方向へ変化するものを用いて、図2に示すよう
に、粘着材を塗布した樹脂製テープ9に金ワイヤ10を
貼り付ける。この金ワイヤ10を貼り付けたテープ9を
弛まないようにして、中空のドーナツ形状の金属フレー
ム8に貼り付ける。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, as shown in FIG.
For wafer 1 having a thickness of about 300 μm, the remaining allowance is 20 to
The p / n junction separation groove 2 is formed deeply to have a thickness of 50 μm. On the other hand, as shown in FIG. 2, a gold wire 10 is used as a conductive metal wire, and a material whose adhesiveness changes in a direction in which the adhesiveness is weakened by irradiating ultraviolet rays is used as an adhesive. A gold wire 10 is attached to the tape 9. The tape 9 to which the gold wire 10 has been attached is attached to the hollow donut-shaped metal frame 8 without loosening.

【0012】この状態のテープ9の粘着材の上に上記ウ
エハ1を乗せ、ダイボンド側面で貼り付ける。このよう
にテープ9が貼り付けられたウエハ1をテストステージ
7に乗せ、プローバー装置の片方の電極を金属フレーム
8に取り付け、他方の電極をプローバー装置のプローブ
針6に取り付けて、このプローブ針6をボンディングパ
ッド電極3に接触させることにより、装置電源の+側
(あるいは−側)−プローブ針6−ボンディングパッド
電極3−チップp/n 接合4−ダイボンド側電極5−金ワ
イヤ10−金属フレーム8−装置電源の−側(あるいは
+側)という電流の流れを作って、ウエハ1上のチップ
の電気的光学的特性を測定し、合否判断する。不良チッ
プにはバッドマークを付ける。これをウエハ1上の全て
のボンディングパッドに対して、あるいは予め決めた抜
取頻度で繰り返す。
The wafer 1 is placed on the adhesive material of the tape 9 in this state, and is adhered on the side surface of the die bond. The wafer 1 on which the tape 9 is stuck in this manner is placed on the test stage 7, one electrode of the prober device is attached to the metal frame 8, and the other electrode is attached to the probe needle 6 of the prober device. Is brought into contact with the bonding pad electrode 3 so that the + side (or-side) of the device power supply-the probe needle 6-the bonding pad electrode 3-the tip p / n junction 4-the die bonding side electrode 5-the gold wire 10-the metal frame 8 A current flow on the minus side (or plus side) of the device power supply is made, and the electrical and optical characteristics of the chips on the wafer 1 are measured to make a pass / fail decision. Bad marks are attached to defective chips. This is repeated for all bonding pads on the wafer 1 or at a predetermined extraction frequency.

【0013】特性測定の後、ウエハ1に不必要な力が加
わらないようテープ粘着材に紫外線を照射し粘着力を低
下させてウエハ1をテープ9から取り外す。次に、p/n
接合分離溝2に沿ってダイボンド側面からダイヤモンド
ツールを使用してケガキ傷を入れた(スクライブした)
後、圧力を加えスクライブ傷を起点に個々のチップを分
断する。
After the measurement of the characteristics, the tape 1 is removed from the tape 9 by irradiating the tape adhesive with ultraviolet rays to reduce the adhesive force so that unnecessary force is not applied to the wafer 1. Then, p / n
A scratch was made (scribed) using a diamond tool from the side of the die bond along the bonding separation groove 2.
Thereafter, pressure is applied to divide the individual chips starting from the scribed scratches.

【0014】以上は本発明の基本的な実施の態様であ
る。以下に更に詳細な説明をする。テープ9は、テスト
ステージ7より十分大きく、かつプローバー装置の構造
上、許容可能なサイズとする。テープ基材に材質、厚さ
等、特別な制約はない。
The above is a basic embodiment of the present invention. The following is a more detailed description. The tape 9 is sufficiently larger than the test stage 7 and has an allowable size due to the structure of the prober device. There are no special restrictions on the material, thickness, etc., of the tape base material.

【0015】導電性金属ワイヤは細く加工するために展
性の高い、また腐食や錆によって電導性が劣化しない点
で、金ワイヤ10が望ましい。金ワイヤ10は、チップ
サイズより十分細く、またウエハ1と粘着材との間に挟
み込んだときに粘着材高さが大きく変化してウエハ1割
れの要因とならないような、20μm以下の太さとす
る。この金ワイヤ10を少なくとも1本、あるいは必要
に応じて複数本、金ワイヤ10と金ワイヤ10が交差し
ないようにテープ粘着材のウエハ1サイズよりも十分に
大きい範囲でかつ金属フレーム8に十分に達するように
貼り付ける。
The conductive metal wire is preferably a gold wire 10 because it is highly malleable because it is processed to be thin, and the conductivity is not deteriorated by corrosion or rust. The gold wire 10 is sufficiently thinner than the chip size, and has a thickness of 20 μm or less so that the height of the adhesive material does not greatly change when sandwiched between the wafer 1 and the adhesive material to cause a crack in the wafer 1. . At least one gold wire 10 or a plurality of gold wires 10 if necessary, in a range sufficiently larger than the size of the tape-adhesive wafer 1 and sufficiently in the metal frame 8 so that the gold wires 10 do not cross each other. Paste to reach.

【0016】この金ワイヤ10を貼り付けたテープ9を
弛まないようにして、中空のドーナツ形状の金属フレー
ム8に貼り付けることで、取り扱いが容易になるととも
に、この金属フレーム8と貼り付けた金ワイヤ10とが
同電位となって、電気的な引き出しも容易になる。
The tape 9 to which the gold wire 10 is attached is not loosened and is attached to the hollow donut-shaped metal frame 8 so that the handling becomes easy, and the metal frame 8 and the attached gold are attached. The electric potential of the wire 10 is the same as that of the wire 10, so that electrical withdrawal becomes easy.

【0017】ウエハ1を前述のテープ9に貼り付けるこ
とにより、全面あるいはメッシュ状のダイボンド側電極
5が金ワイヤ10と接触し、ダイボンド側電極5は金ワ
イヤ10および金属フレーム8と同電位となる。
By attaching the wafer 1 to the above-mentioned tape 9, the entire surface or the mesh-shaped die-bonding electrode 5 comes into contact with the gold wire 10, and the die-bonding electrode 5 has the same potential as the gold wire 10 and the metal frame 8. .

【0018】[0018]

【発明の効果】ウエハ1にテープ9を貼り付けてハンド
リングする本発明の方法では、テープ9が保持材となっ
てウエハ1が従来方法と比較して割れにくく、また割れ
ても分割された一方のウエハ片と他方のウエハ片の位置
関係が元の形状時の位置関係を維持しているので、何れ
のウエハも金ワイヤ10によってダイボンド側の電極5
の接触が確保できている限り、1枚のウエハとして電気
的光学的特性の測定をそのまま続行することが可能とな
り作業効率が改善される。
According to the method of the present invention in which the tape 9 is adhered to the wafer 1 for handling, the tape 9 serves as a holding material so that the wafer 1 is less likely to be broken as compared with the conventional method. Since the positional relationship between the wafer piece and the other wafer piece maintains the original positional relationship in the original shape, any of the wafers is connected to the die bonding electrode 5 by the gold wire 10.
As long as the contact can be ensured, the measurement of the electrical and optical characteristics can be continued as one wafer, and the working efficiency is improved.

【0019】ウエハ1のp/n 接合分離溝2の残り代を薄
くして形成するので、残り代を厚く確保する従来方法と
比較して、チップ形状が安定する。ウエハ1のダイボン
ド側電極5の電気的接触を導電性金属ワイヤで取るの
で、テストステージ7を電導製のものにする制約がなく
なる。
Since the remaining margin of the p / n junction separation groove 2 of the wafer 1 is formed thinner, the chip shape is more stable than the conventional method in which the remaining margin is made thicker. Since the electrical contact of the electrode 5 on the die bond side of the wafer 1 is made with a conductive metal wire, there is no restriction that the test stage 7 be made of a conductive material.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の全体図である。FIG. 1 is an overall view of the present invention.

【図2】本発明の動作説明図である。FIG. 2 is a diagram illustrating the operation of the present invention.

【図3】従来技術を説明する図である。FIG. 3 is a diagram illustrating a conventional technique.

【図4】従来技術の全体図である。FIG. 4 is an overall view of the related art.

【符号の説明】[Explanation of symbols]

1…ウエハ、2…p/n 接合分離溝、3…ボンディングパ
ッド電極、4…p/n 接合、5…ダイボンド側電極、6…
プローブ針、7…テストステージ、8…金属フレーム、
9…粘着材付テープ、10…金ワイヤ
DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... p / n junction separation groove, 3 ... Bonding pad electrode, 4 ... p / n junction, 5 ... Die bond side electrode, 6 ...
Probe needle, 7 ... test stage, 8 ... metal frame,
9 Tape with adhesive material 10 Gold wire

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 一方の面にボンディングパッド電極、他
方の面にダイボンド側電極が形成され、前記一方の面か
らはチップサイズに対応した寸法で分断する溝が形成さ
れ、前記他方の面側には残り代が残されている半導体ウ
エハの特性検査方法において、粘着材を塗布したテープ
に導電性金属ワイヤを貼り、そのテープを前記半導体ウ
エハの前記他方の面に貼ることで、前記他方の面側の電
極の電気的接触を前記導電性金属ワイヤで取ることを特
徴とする半導体ウエハの特性検査方法。
1. A bonding pad electrode is formed on one surface, a die-bonding electrode is formed on the other surface, a groove is formed from the one surface in a size corresponding to a chip size, and a groove is formed on the other surface side. In the method for inspecting characteristics of a semiconductor wafer in which the remaining margin is left, a conductive metal wire is attached to a tape coated with an adhesive, and the tape is attached to the other surface of the semiconductor wafer, so that the other surface is formed. A method for inspecting characteristics of a semiconductor wafer, wherein an electrical contact of a side electrode is made with the conductive metal wire.
【請求項2】 前記粘着材は紫外線を照射することによ
り粘着度が弱くなる方向へ変化するものであることを特
徴とする請求項1記載の半導体ウエハの特性検査方法。
2. The semiconductor wafer characteristic inspection method according to claim 1, wherein the adhesive changes in a direction in which the adhesiveness decreases when the adhesive is irradiated with ultraviolet rays.
【請求項3】 前記テープをドーナツ形状の金属フレー
ムに貼り付けることを特徴とする請求項1又は2記載の
半導体ウエハの特性検査方法。
3. The method according to claim 1, wherein the tape is attached to a donut-shaped metal frame.
JP16247797A 1997-06-19 1997-06-19 Characteristics inspection method of semiconductor wafer Pending JPH1116965A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16247797A JPH1116965A (en) 1997-06-19 1997-06-19 Characteristics inspection method of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16247797A JPH1116965A (en) 1997-06-19 1997-06-19 Characteristics inspection method of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH1116965A true JPH1116965A (en) 1999-01-22

Family

ID=15755371

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16247797A Pending JPH1116965A (en) 1997-06-19 1997-06-19 Characteristics inspection method of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH1116965A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005294773A (en) * 2004-04-06 2005-10-20 Renesas Technology Corp Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005294773A (en) * 2004-04-06 2005-10-20 Renesas Technology Corp Method for manufacturing semiconductor device
JP4570896B2 (en) * 2004-04-06 2010-10-27 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device

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