CN111896856B - Chip electrical performance testing system and method - Google Patents

Chip electrical performance testing system and method Download PDF

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Publication number
CN111896856B
CN111896856B CN202010805833.0A CN202010805833A CN111896856B CN 111896856 B CN111896856 B CN 111896856B CN 202010805833 A CN202010805833 A CN 202010805833A CN 111896856 B CN111896856 B CN 111896856B
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tested
semiconductor layer
type semiconductor
electrode
wafer
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CN111896856A (en
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罗坤
黄斌斌
李永同
熊慧
刘兆
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Jiangxi Qianzhao Photoelectric Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2632—Circuits therefor for testing diodes
    • G01R31/2635—Testing light-emitting diodes, laser diodes or photodiodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2644—Adaptations of individual semiconductor devices to facilitate the testing thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention provides a chip electrical performance test system and a chip electrical performance test method, wherein a plurality of core grains share an N-type semiconductor layer, a plurality of first electrode pads are arranged in the edge area of the N-type semiconductor layer and used as fixed negative electrode test points, when the electrical performance of the corresponding core grains is required to be tested, only a positive electrode probe structure is required to be contacted with a second electrode pad of the corresponding core grains, and then electrical performance test parameters of the core grains can be obtained through reasonable conversion. Therefore, according to the chip electrical performance testing system provided by the application, each core particle only needs to test the second electrode bonding pad (P electrode), the testing efficiency can be greatly improved, the contact frequency between the first electrode bonding pad (N electrode) and the probe is reduced, the service life of the probe is prolonged, the consumption of the probe is further reduced, the testing cost is reduced, and the aging phenomenon of the chip is also reduced.

Description

Chip electrical performance testing system and method
Technical Field
The invention relates to the technical field of electrical performance testing, in particular to a system and a method for testing the electrical performance of a chip.
Background
With the continuous development of science and technology, as a novel light emitting device, an LED (Light Emitting Diode ) has the advantages of energy saving, environmental protection, good color rendering property, good response speed and the like compared with the traditional light emitting device, is widely applied to the life and work of people, and brings great convenience to the daily life of people.
The LED chip is tested for electrical properties before it leaves the factory. Conventional electrical performance testing of chips requires the use of probes to contact the N and P electrodes one by one for the optoelectronic performance test.
However, conventional testing systems and methods require probes to be contacted to the P-electrode and the N-electrode of each core particle for testing, respectively, resulting in extremely low testing efficiency.
Disclosure of Invention
In view of the above, the present invention provides a system and a method for testing electrical performance of a chip, which have the following technical schemes:
a chip electrical performance test system, the chip electrical performance test system comprising: the wafer to be tested, one positive electrode probe structure and a plurality of negative electrode probe structures;
a plurality of independent core grains are divided on the wafer to be tested, the core grains share an N-type semiconductor layer, and a plurality of first electrode pads are arranged in the edge area of the N-type semiconductor layer;
a second electrode pad is arranged on each core particle;
the negative electrode probe structures are the same as the first electrode pads in number and are in one-to-one corresponding contact;
in the process of testing the electrical performance of the chip, the positive electrode probe structure is respectively contacted with the second electrode bonding pad of each core particle so as to test the electrical performance of each core particle.
Optionally, in the above chip electrical performance testing system, the chip electrical performance testing system further includes:
and the surface of the bearing table is used for placing the wafer to be tested.
Optionally, in the above system for testing electrical performance of a chip, the wafer to be tested includes:
a substrate;
the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially arranged on the substrate;
and the dicing channels penetrate through the P-type semiconductor layer and the active layer to form a plurality of independent core particles.
Optionally, in the above system for testing electrical performance of a chip, the N-type semiconductor layer is an N-type GaN layer.
Optionally, in the above system for testing electrical performance of a chip, the P-type semiconductor layer is a P-type GaN layer.
Optionally, in the above chip electrical performance test system, the width of the edge area of the N-type semiconductor layer is 0.1mm-1mm.
Optionally, in the above chip electrical performance test system, the number of pads of the first electrode pads is at least 6.
Optionally, in the above chip electrical performance test system, the plurality of first electrode pads are uniformly arranged in an edge region of the N-type semiconductor layer.
A method for testing electrical performance of a chip, the method comprising:
providing a wafer to be tested, wherein a plurality of independent core grains are divided on the wafer to be tested, the core grains share an N-type semiconductor layer, a plurality of first electrode bonding pads are arranged in the edge area of the N-type semiconductor layer, and a second electrode bonding pad is arranged on each core grain;
contacting the plurality of negative electrode probe structures with the plurality of first electrode pads in a one-to-one correspondence manner;
and selecting core particles to be tested, and contacting the positive electrode probe structure with a second electrode bonding pad on the chip to be tested.
Optionally, in the above method for testing electrical performance of a chip, the method for testing electrical performance of a chip further includes:
taking the center of the wafer to be tested as a test origin;
establishing a reference coordinate system;
acquiring a coordinate position of the core particle to be tested in the reference coordinate system, wherein the coordinate position comprises an abscissa and an ordinate;
acquiring the length and the width of the wafer to be tested;
and according to the abscissa, the ordinate, the length and the width of the wafer to be tested and the test value of the test machine, combining the calculation coefficients to obtain the electrical performance parameters of the core particles to be tested.
Compared with the prior art, the invention has the following beneficial effects:
according to the chip electrical property test system provided by the invention, a plurality of core particles share the N-type semiconductor layer, and the edge area of the N-type semiconductor layer is provided with the plurality of first electrode pads as the fixed negative electrode test points, when the electrical property of the corresponding core particles is required to be tested, only the positive electrode probe structure is required to be contacted with the second electrode pads of the corresponding core particles, and then the electrical property test parameters of the core particles can be obtained through reasonable conversion.
Therefore, according to the chip electrical performance testing system provided by the application, each core particle only needs to test the second electrode bonding pad (P electrode), the testing efficiency can be greatly improved, the contact frequency between the first electrode bonding pad (N electrode) and the probe is reduced, the service life of the probe is prolonged, the consumption of the probe is further reduced, the testing cost is reduced, and the aging phenomenon of the chip is also reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic top view of a chip electrical performance testing system according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1 in accordance with an embodiment of the present invention;
FIG. 3 is a schematic top view of another system for testing electrical performance of chips according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view along line B-B' of FIG. 3 in accordance with an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a wafer to be tested according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another wafer to be tested according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a position of a first electrode pad according to an embodiment of the present invention;
fig. 8 is a flow chart of a method for testing electrical performance of a chip according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, fig. 1 is a schematic top view of a chip electrical performance testing system according to an embodiment of the invention.
Referring to FIG. 2, FIG. 2 is a schematic cross-sectional view of FIG. 1 along line A-A' in accordance with an embodiment of the present invention.
The chip electrical performance test system comprises: a wafer 11 to be tested, a positive electrode probe structure 15 and a plurality of negative electrode probe structures 16.
The wafer 11 to be tested is divided into a plurality of independent core grains 13, the plurality of core grains 13 share the N-type semiconductor layer 12, and a plurality of first electrode pads 14 are arranged in the edge area of the N-type semiconductor layer 12.
A second electrode pad 17 is provided on each of the core particles 13.
The number of the negative electrode probe structures 16 is the same as that of the first electrode pads 14, and are in one-to-one contact.
In the process of testing the electrical performance of the chip, the positive electrode probe structure 15 is respectively contacted with the second electrode pad 17 of each core particle 13, so as to test the electrical performance of each core particle.
In this embodiment, the N-type semiconductor layer 12 is shared by the plurality of core particles 13, and the plurality of first electrode pads 14 are disposed at the edge region of the N-type semiconductor layer 12 as fixed negative electrode test points, when the electrical performance of the corresponding core particles needs to be tested, only the positive electrode probe structure 15 needs to be contacted with the second electrode pads 17 of the corresponding core particles, and then the electrical performance test parameters of the core particles can be obtained through reasonable conversion.
Therefore, according to the chip electrical performance testing system provided by the application, each core particle only needs to test the second electrode bonding pad (P electrode), the testing efficiency can be greatly improved, the contact frequency between the first electrode bonding pad (N electrode) and the probe is reduced, the service life of the probe is prolonged, the consumption of the probe is further reduced, the testing cost is reduced, and the aging phenomenon of the chip is also reduced.
Referring to fig. 3, fig. 3 is a schematic top view of another chip electrical performance testing system according to an embodiment of the invention.
Referring to fig. 4, fig. 4 is a schematic cross-sectional view of fig. 3 along B-B' in accordance with an embodiment of the present invention.
Further, according to the above embodiment of the present invention, the chip electrical performance testing system further includes:
a carrying table 18, wherein the surface of the carrying table 18 is used for placing the wafer to be tested.
In this embodiment, other test structures may be fixed on the carrier 18, for example, a plurality of negative electrode probe structures 2+ may be fixed on the carrier 18, and after the wafer 11 to be tested is placed on the carrier 18, the plurality of negative electrode probe structures 16 may be in one-to-one contact with the plurality of first electrode pads 14.
Further, according to the above embodiment of the present invention, referring to fig. 5, fig. 5 is a schematic structural diagram of a wafer to be tested according to an embodiment of the present invention.
The wafer to be tested includes:
a substrate 19;
an N-type semiconductor layer 12, an active layer 131, and a P-type semiconductor layer 132 sequentially disposed on the substrate 19;
dicing streets 20, the dicing streets 20 penetrating the P-type semiconductor layer 132 and the active layer 131 to form a plurality of independent core particles 13.
In this embodiment, the substrate 19 includes, but is not limited to, a sapphire substrate, and the structure of the wafer to be tested is merely illustrated by way of example, and may further include other functional layers, which are not limited in the embodiment of the present invention.
It should be noted that the scribe line 20 needs to penetrate at least the active layer 131 to prevent leakage between the core particles.
Optionally, the N-type semiconductor layer 12 is an N-type GaN layer.
Optionally, the P-type semiconductor layer 132 is a P-type GaN layer.
Further, according to the above embodiment of the present invention, referring to fig. 6, fig. 6 is a schematic structural diagram of another wafer to be tested according to the embodiment of the present invention.
The width of the edge area of the N-type semiconductor layer 12 is 0.1mm-1mm.
In this embodiment, the width of the edge region of the N-type semiconductor layer 12 is 0.3mm or 0.6mm or 0.8mm or the like.
Further, according to the above embodiment of the present invention, the number of pads of the first electrode pads 14 is at least 6.
In this embodiment, the number of the first electrode pads 14 may be appropriately set according to the actual situation, with the accuracy of the electrical performance test structure improved.
Further, according to the above embodiment of the present invention, referring to fig. 7, fig. 7 is a schematic diagram illustrating a position of a first electrode pad according to an embodiment of the present invention.
The plurality of first electrode pads 14 are uniformly arranged in the edge region of the N-type semiconductor layer 12.
In this embodiment, taking 6 first electrode pads 14 as an example, the 6 first electrode pads 14 are all located in the edge area of the N-type semiconductor layer 12, the distances h between the 6 first electrode pads 14 and the center of the N-type semiconductor layer 12 are the same, and the included angles β between the adjacent two first electrode pads 14 and the central line of the N-type semiconductor layer 12 are the same.
Further, based on all the above embodiments of the present invention, another embodiment of the present invention further provides a method for testing electrical performance of a chip, and referring to fig. 8, fig. 8 is a flow chart of a method for testing electrical performance of a chip according to an embodiment of the present invention.
The chip electrical property testing method comprises the following steps:
s10, providing a wafer to be tested, wherein a plurality of independent core grains are divided on the wafer to be tested, the core grains share an N-type semiconductor layer, a plurality of first electrode bonding pads are arranged in the edge area of the N-type semiconductor layer, and each core grain is provided with a second electrode bonding pad.
In the step, a wafer to be tested is provided, and is subjected to process treatment, and during the MESA procedure, the epitaxial layer structure on the N-type semiconductor layer is subjected to etching treatment so as to expose the edge area of the N-type semiconductor layer.
The width of the edge area of the N-type semiconductor layer is 0.1mm-1mm.
For example, the width of the edge region of the N-type semiconductor layer is 0.3mm or 0.6mm or 0.8mm, etc.
And pre-cutting the wafer to be tested, wherein the cutting path penetrates through the P-type semiconductor layer and the active layer to form a plurality of independent core particles.
And S20, the plurality of negative electrode probe structures are contacted with the plurality of first electrode pads in a one-to-one correspondence manner.
S30, selecting core particles to be tested, and enabling the positive electrode probe structure to be in contact with a second electrode bonding pad on the chip to be tested.
Further, based on the above-described embodiment of the present invention,
taking the center of the wafer to be tested as a test origin;
establishing a reference coordinate system;
acquiring a coordinate position of the core particle to be tested in the reference coordinate system, wherein the coordinate position comprises an abscissa and an ordinate;
acquiring the length and the width of the wafer to be tested;
and according to the abscissa, the ordinate, the length and the width of the wafer to be tested and the test value of the test machine, combining the calculation coefficients to obtain the electrical performance parameters of the core particles to be tested.
In this embodiment, the electrical property parameter vf1=vf1 of the core particle to be tested Test value -K* ((1010000-L1*ABS(X)) 2 +(1010000-L2*ABS(Y)) 2 )^(1/2)/2。
Wherein, (X, Y) is the coordinate position of the core particle to be tested;
l1 is the length of the wafer to be tested;
l2 is the width of the wafer to be tested;
VF1 test value The test value is the test value of the test machine;
k is a calculation coefficient which is determined based on the type and the size of the core particle and can be obtained by comparing the VF1 value of the same core particle by adopting a conventional test method and the test method provided by the invention.
The above describes in detail a system and a method for testing electrical performance of a chip provided by the present invention, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include, or is intended to include, elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. A system for testing electrical performance of a chip, the system comprising: the wafer to be tested, one positive electrode probe structure and a plurality of negative electrode probe structures;
the wafer to be tested is divided into a plurality of independent core grains, the plurality of core grains share an N-type semiconductor layer, a plurality of first electrode pads are arranged in the edge area of the N-type semiconductor layer, and the plurality of first electrode pads are uniformly distributed in the edge area of the N-type semiconductor layer;
a second electrode pad is arranged on each core particle;
the negative electrode probe structures are the same as the first electrode pads in number and are in one-to-one corresponding contact;
in the process of testing the electrical performance of the chip, the positive electrode probe structure is respectively contacted with the second electrode bonding pad of each core particle so as to test the electrical performance of each core particle.
2. The chip electrical property testing system of claim 1, further comprising:
and the surface of the bearing table is used for placing the wafer to be tested.
3. The system of claim 1, wherein the wafer to be tested comprises:
a substrate;
the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially arranged on the substrate;
and the dicing channels penetrate through the P-type semiconductor layer and the active layer to form a plurality of independent core particles.
4. The system of claim 3, wherein the N-type semiconductor layer is an N-type GaN layer.
5. The system of claim 3, wherein the P-type semiconductor layer is a P-type GaN layer.
6. The system of claim 1, wherein the N-type semiconductor layer has a width of 0.1mm to 1mm in the edge region.
7. The system of claim 1, wherein the number of pads of the first electrode pads is at least 6.
8. A method for testing electrical properties of a chip applied to the system for testing electrical properties of a chip according to any one of claims 1 to 7, wherein the method for testing electrical properties of a chip comprises:
providing a wafer to be tested, wherein a plurality of independent core grains are divided on the wafer to be tested, the core grains share an N-type semiconductor layer, a plurality of first electrode pads are arranged in the edge area of the N-type semiconductor layer, the first electrode pads are uniformly distributed in the edge area of the N-type semiconductor layer, and a second electrode pad is arranged on each core grain;
contacting the plurality of negative electrode probe structures with the plurality of first electrode pads in a one-to-one correspondence manner;
selecting core particles to be tested, and enabling the positive electrode probe structure to be in contact with a second electrode bonding pad on the chip to be tested;
taking the center of the wafer to be tested as a test origin;
establishing a reference coordinate system;
acquiring a coordinate position of the core particle to be tested in the reference coordinate system, wherein the coordinate position comprises an abscissa and an ordinate;
acquiring the length and the width of the wafer to be tested;
obtaining an electrical performance parameter vf1=vf1 of the core particle to be tested according to the abscissa, the ordinate, the length and width of the wafer to be tested and the test value of the test machine by combining the calculation coefficients Test value -K*（（1010000-L1*ABS（X）） 2 +（1010000-L2*ABS（Y）） 2 ）^（1/2）/2；
Wherein, (X, Y) is the coordinate position of the core particle to be tested;
l1 is the length of the wafer to be tested;
l2 is the width of the wafer to be tested;
VF1 test value The test value is the test value of the test machine;
k is a calculation coefficient.
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