CN111896856A - System and method for testing electrical performance of chip - Google Patents

System and method for testing electrical performance of chip Download PDF

Info

Publication number
CN111896856A
CN111896856A CN202010805833.0A CN202010805833A CN111896856A CN 111896856 A CN111896856 A CN 111896856A CN 202010805833 A CN202010805833 A CN 202010805833A CN 111896856 A CN111896856 A CN 111896856A
Authority
CN
China
Prior art keywords
tested
semiconductor layer
type semiconductor
electrode
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010805833.0A
Other languages
Chinese (zh)
Other versions
CN111896856B (en
Inventor
罗坤
黄斌斌
李永同
熊慧
刘兆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangxi Qianzhao Photoelectric Co ltd
Original Assignee
Jiangxi Qianzhao Photoelectric Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangxi Qianzhao Photoelectric Co ltd filed Critical Jiangxi Qianzhao Photoelectric Co ltd
Priority to CN202010805833.0A priority Critical patent/CN111896856B/en
Publication of CN111896856A publication Critical patent/CN111896856A/en
Application granted granted Critical
Publication of CN111896856B publication Critical patent/CN111896856B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2632—Circuits therefor for testing diodes
    • G01R31/2635—Testing light-emitting diodes, laser diodes or photodiodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2644—Adaptations of individual semiconductor devices to facilitate the testing thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]

Abstract

The invention provides a system and a method for testing electrical property of a chip.A plurality of core particles share an N-type semiconductor layer, a plurality of first electrode pads are arranged at the edge area of the N-type semiconductor layer and used as fixed negative electrode test points, when the electrical property of the corresponding core particle needs to be tested, only an anode probe structure needs to be contacted with a second electrode pad of the corresponding core particle, and the electrical property test parameters of the core particle can be obtained through reasonable conversion. Therefore, according to the chip electrical performance testing system provided by the application, each core particle only needs to test the second electrode pad (P electrode), so that the testing efficiency can be greatly improved, the contact frequency between the first electrode pad (N electrode) and the probe is reduced, the service life of the probe is prolonged, the consumption of the probe is reduced, the testing cost is reduced, and the aging phenomenon of the chip is also reduced.

Description

System and method for testing electrical performance of chip
Technical Field
The invention relates to the technical field of electrical property testing, in particular to a system and a method for testing electrical property of a chip.
Background
With the continuous development of scientific technology, LEDs (Light Emitting diodes) are used as novel Light Emitting devices, and compared with traditional Light Emitting devices, LEDs have the advantages of energy saving, environmental protection, good color rendering and response speed, and the like, and are widely applied to life and work of people, thereby bringing great convenience to daily life of people.
The electrical performance of the LED chip is tested before the LED chip is shipped. Conventional chip electrical performance testing requires that the probes are contacted with the N electrode and the P electrode one by one for photoelectric performance testing.
However, the conventional test system and method require that the probe is contacted to the P-electrode and the N-electrode of each core particle for separate testing, resulting in very low testing efficiency.
Disclosure of Invention
In view of the above, in order to solve the above problems, the present invention provides a system and a method for testing electrical performance of a chip, and the technical scheme is as follows:
a chip electrical performance testing system, the chip electrical performance testing system comprising: the device comprises a wafer to be tested, a positive probe structure and a plurality of negative probe structures;
a plurality of independent core particles are divided on the wafer to be tested, the core particles share an N-type semiconductor layer, and a plurality of first electrode pads are arranged in the edge area of the N-type semiconductor layer;
each core grain is provided with a second electrode pad;
the number of the negative probe structures is the same as that of the first electrode bonding pads, and the negative probe structures are in one-to-one corresponding contact with the first electrode bonding pads;
in the chip electrical performance test process, the positive electrode probe structure is respectively contacted with the second electrode pad of each core grain so as to test the electrical performance of each core grain.
Optionally, in the above chip electrical performance testing system, the chip electrical performance testing system further includes:
the surface of the bearing table is used for placing the wafer to be tested.
Optionally, in the above system for testing electrical performance of a chip, the wafer to be tested includes:
a substrate;
the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially arranged on the substrate;
cutting lines penetrating the P-type semiconductor layer and the active layer to form a plurality of independent core grains.
Optionally, in the above system for testing electrical performance of a chip, the N-type semiconductor layer is an N-type GaN layer.
Optionally, in the above system for testing electrical performance of a chip, the P-type semiconductor layer is a P-type GaN layer.
Optionally, in the above system for testing electrical performance of a chip, the width of the edge region of the N-type semiconductor layer is 0.1mm to 1 mm.
Optionally, in the above chip electrical performance testing system, the number of the first electrode pads is at least 6.
Optionally, in the above chip electrical performance testing system, the plurality of first electrode pads are uniformly arranged in an edge region of the N-type semiconductor layer.
A chip electrical property testing method comprises the following steps:
providing a wafer to be tested, wherein a plurality of independent core particles are divided on the wafer to be tested, the core particles share an N-type semiconductor layer, a plurality of first electrode pads are arranged in the edge area of the N-type semiconductor layer, and a second electrode pad is arranged on each core particle;
correspondingly contacting a plurality of negative electrode probe structures with a plurality of first electrode bonding pads one by one;
and selecting core particles to be tested, and contacting the positive probe structure with a second electrode pad on the chip to be tested.
Optionally, in the above method for testing electrical performance of a chip, the method for testing electrical performance of a chip further includes:
taking the center of the wafer to be tested as a test origin;
establishing a reference coordinate system;
acquiring the coordinate position of the core grain to be tested in the reference coordinate system, wherein the coordinate position comprises a horizontal coordinate and a vertical coordinate;
acquiring the length and the width of the wafer to be tested;
and obtaining the electrical property parameters of the core particles to be tested by combining the calculation coefficients according to the abscissa, the ordinate, the length and the width of the wafer to be tested and the test value of a test machine.
Compared with the prior art, the invention has the following beneficial effects:
according to the chip electrical property testing system provided by the invention, a plurality of core particles share the N-type semiconductor layer, and a plurality of first electrode pads are arranged in the edge area of the N-type semiconductor layer and used as fixed negative electrode testing points.
Therefore, according to the chip electrical performance testing system provided by the application, each core particle only needs to test the second electrode pad (P electrode), so that the testing efficiency can be greatly improved, the contact frequency between the first electrode pad (N electrode) and the probe is reduced, the service life of the probe is prolonged, the consumption of the probe is reduced, the testing cost is reduced, and the aging phenomenon of the chip is also reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic top view of a system for testing electrical properties of a chip according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1 in accordance with an embodiment of the present invention;
FIG. 3 is a schematic top view of another system for testing electrical properties of chips according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view taken along line B-B' of FIG. 3 in accordance with an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a wafer to be tested according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of another wafer to be tested according to an embodiment of the present invention;
fig. 7 is a schematic diagram illustrating a position of a first electrode pad according to an embodiment of the present invention;
fig. 8 is a schematic flow chart of a method for testing electrical properties of a chip according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic top view of a chip electrical performance testing system according to an embodiment of the present invention.
Referring to fig. 2, fig. 2 is a schematic cross-sectional view taken along a-a' of fig. 1 according to an embodiment of the present invention.
The chip electrical performance test system comprises: a wafer 11 to be tested, a positive probe structure 15 and a plurality of negative probe structures 16.
A plurality of independent core particles 13 are divided on the wafer 11 to be tested, the core particles 13 share the N-type semiconductor layer 12, and a plurality of first electrode pads 14 are arranged in the edge region of the N-type semiconductor layer 12.
Each of the core particles 13 is provided with a second electrode pad 17 thereon.
The number of the negative electrode probe structures 16 is the same as that of the first electrode pads 14, and the negative electrode probe structures and the first electrode pads are in one-to-one contact.
During the chip electrical performance test, the positive probe structure 15 is respectively contacted with the second electrode pad 17 of each of the core particles 13, so as to perform the electrical performance test on each of the core particles.
In this embodiment, the plurality of core particles 13 share the N-type semiconductor layer 12, and the plurality of first electrode pads 14 are disposed in the edge region of the N-type semiconductor layer 12 as fixed negative test points, so that when the electrical performance of a corresponding core particle needs to be tested, only the positive probe structure 15 needs to be in contact with the second electrode pad 17 of the corresponding core particle, and then the electrical performance test parameters of the core particle can be obtained through reasonable conversion.
Therefore, according to the chip electrical performance testing system provided by the application, each core particle only needs to test the second electrode pad (P electrode), so that the testing efficiency can be greatly improved, the contact frequency between the first electrode pad (N electrode) and the probe is reduced, the service life of the probe is prolonged, the consumption of the probe is reduced, the testing cost is reduced, and the aging phenomenon of the chip is also reduced.
Referring to fig. 3, fig. 3 is a schematic top view of another chip electrical performance testing system according to an embodiment of the present invention.
Referring to FIG. 4, FIG. 4 is a schematic cross-sectional view taken along line B-B' of FIG. 3 according to an embodiment of the present invention.
Further, based on the above embodiment of the present invention, the chip electrical performance testing system further includes:
a bearing platform 18, wherein the surface of the bearing platform 18 is used for placing the wafer to be tested.
In this embodiment, other testing structures may be fixed on the carrier 18, for example, a plurality of negative probe structures 2+ may be fixed on the carrier 18, and after the wafer 11 to be tested is placed on the carrier 18, a plurality of negative probe structures 16 may be in one-to-one contact with the plurality of first electrode pads 14.
Further, based on the above embodiments of the present invention, referring to fig. 5, fig. 5 is a schematic structural diagram of a wafer to be tested according to an embodiment of the present invention.
The wafer to be tested comprises:
a substrate 19;
an N-type semiconductor layer 12, an active layer 131, and a P-type semiconductor layer 132 sequentially disposed on the substrate 19;
and dicing streets 20, the dicing streets 20 penetrating the P-type semiconductor layer 132 and the active layer 131 to form a plurality of independent core particles 13.
In this embodiment, the substrate 19 includes, but is not limited to, a sapphire substrate, and the structure of the wafer to be tested is only illustrated by way of example, and may further include other functional layers, which are not limited in the embodiment of the present invention.
It should be noted that the scribe line 20 needs to penetrate at least the active layer 131 to prevent the electrical leakage between the core particles.
Optionally, the N-type semiconductor layer 12 is an N-type GaN layer.
Optionally, the P-type semiconductor layer 132 is a P-type GaN layer.
Further, based on the above embodiments of the present invention, referring to fig. 6, fig. 6 is a schematic structural diagram of another wafer to be tested according to an embodiment of the present invention.
The width of the edge area of the N-type semiconductor layer 12 is 0.1mm-1 mm.
In this embodiment, the width of the edge region of the N-type semiconductor layer 12 is 0.3mm, 0.6mm, 0.8mm, or the like.
Further, based on the above-described embodiment of the present invention, the number of the first electrode pads 14 is at least 6.
In this embodiment, the number of the first electrode pads 14 may be determined according to actual conditions, and the number of the first electrode pads may be set reasonably in the case of improving the accuracy of the electrical performance test structure.
Further, based on the above-mentioned embodiment of the present invention, referring to fig. 7, fig. 7 is a schematic position diagram of a first electrode pad according to an embodiment of the present invention.
The plurality of first electrode pads 14 are uniformly arranged at the edge region of the N-type semiconductor layer 12.
In this embodiment, 6 first electrode pads 14 are taken as an example for explanation, the 6 first electrode pads 14 are all located in the edge region of the N-type semiconductor layer 12, the distance h between the 6 first electrode pads 14 and the center of the N-type semiconductor layer 12 is the same, and the included angle β between two adjacent first electrode pads 14 and the center connecting line of the N-type semiconductor layer 12 is the same.
Further, based on all the above embodiments of the present invention, in another embodiment of the present invention, a method for testing electrical performance of a chip is further provided, and referring to fig. 8, fig. 8 is a schematic flow chart of the method for testing electrical performance of a chip according to the embodiment of the present invention.
The chip electrical property testing method comprises the following steps:
s10, providing a wafer to be tested, wherein a plurality of independent core particles are divided on the wafer to be tested, the core particles share the N-type semiconductor layer, a plurality of first electrode pads are arranged on the edge area of the N-type semiconductor layer, and each core particle is provided with a second electrode pad.
In this step, a wafer to be tested is provided and subjected to a process treatment, and during the MESA process, an epitaxial layer structure on the N-type semiconductor layer is etched to expose an edge region of the N-type semiconductor layer.
The width of the edge area of the N-type semiconductor layer is 0.1mm-1 mm.
For example, the width of the edge region of the N-type semiconductor layer is 0.3mm, 0.6mm, 0.8mm, or the like.
And pre-cutting the wafer to be tested, wherein cutting channels penetrate through the P-type semiconductor layer and the active layer to form a plurality of independent core grains.
And S20, correspondingly contacting the negative electrode probe structures with the first electrode pads one by one.
And S30, selecting a core particle to be tested, and contacting the positive probe structure with a second electrode pad on the chip to be tested.
Further, based on the above-described embodiments of the present invention,
taking the center of the wafer to be tested as a test origin;
establishing a reference coordinate system;
acquiring the coordinate position of the core grain to be tested in the reference coordinate system, wherein the coordinate position comprises a horizontal coordinate and a vertical coordinate;
acquiring the length and the width of the wafer to be tested;
and obtaining the electrical property parameters of the core particles to be tested by combining the calculation coefficients according to the abscissa, the ordinate, the length and the width of the wafer to be tested and the test value of a test machine.
In this embodiment, the electrical property parameter VF1 ═ VF1 of the core particles to be testedTest value-K* ((1010000-L1*ABS(X))2+(1010000-L2*ABS(Y))2)^(1/2)/2。
Wherein, (X, Y) is the coordinate position of the core particle to be tested;
l1 is the length of the wafer to be tested;
l2 is the width of the wafer to be tested;
VF1test valueThe test value of the test machine is obtained;
k is a calculation coefficient which is determined based on the model and the size of the core grain and can be obtained by comparing the VF1 values of the same core grain by adopting a conventional test method and the test method provided by the invention.
The above detailed description of the system and method for testing electrical performance of a chip provided by the present invention is provided, and the principle and the implementation of the present invention are explained by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A system for testing electrical properties of a chip, the system comprising: the device comprises a wafer to be tested, a positive probe structure and a plurality of negative probe structures;
a plurality of independent core particles are divided on the wafer to be tested, the core particles share an N-type semiconductor layer, and a plurality of first electrode pads are arranged in the edge area of the N-type semiconductor layer;
each core grain is provided with a second electrode pad;
the number of the negative probe structures is the same as that of the first electrode bonding pads, and the negative probe structures are in one-to-one corresponding contact with the first electrode bonding pads;
in the chip electrical performance test process, the positive electrode probe structure is respectively contacted with the second electrode pad of each core grain so as to test the electrical performance of each core grain.
2. The chip electrical performance testing system of claim 1, further comprising:
the surface of the bearing table is used for placing the wafer to be tested.
3. The system for testing electrical properties of chips of claim 1, wherein said wafer to be tested comprises:
a substrate;
the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially arranged on the substrate;
cutting lines penetrating the P-type semiconductor layer and the active layer to form a plurality of independent core grains.
4. The system for testing electrical properties of chips of claim 3, wherein said N-type semiconductor layer is an N-type GaN layer.
5. The system for testing electrical properties of chips of claim 3, wherein said P-type semiconductor layer is a P-type GaN layer.
6. The system for testing the electrical performance of chips as defined in claim 1, wherein the width of the edge region of the N-type semiconductor layer is 0.1mm-1 mm.
7. The chip electrical performance testing system of claim 1, wherein the number of pads of the first electrode pads is at least 6.
8. The system for testing electrical properties of chips of claim 1, wherein a plurality of said first electrode pads are uniformly arranged on an edge region of said N-type semiconductor layer.
9. A chip electrical property testing method is characterized by comprising the following steps:
providing a wafer to be tested, wherein a plurality of independent core particles are divided on the wafer to be tested, the core particles share an N-type semiconductor layer, a plurality of first electrode pads are arranged in the edge area of the N-type semiconductor layer, and a second electrode pad is arranged on each core particle;
correspondingly contacting a plurality of negative electrode probe structures with a plurality of first electrode bonding pads one by one;
and selecting core particles to be tested, and contacting the positive probe structure with a second electrode pad on the chip to be tested.
10. The method of testing electrical performance of a chip of claim 9, further comprising:
taking the center of the wafer to be tested as a test origin;
establishing a reference coordinate system;
acquiring the coordinate position of the core grain to be tested in the reference coordinate system, wherein the coordinate position comprises a horizontal coordinate and a vertical coordinate;
acquiring the length and the width of the wafer to be tested;
and obtaining the electrical property parameters of the core particles to be tested by combining the calculation coefficients according to the abscissa, the ordinate, the length and the width of the wafer to be tested and the test value of a test machine.
CN202010805833.0A 2020-08-12 2020-08-12 Chip electrical performance testing system and method Active CN111896856B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010805833.0A CN111896856B (en) 2020-08-12 2020-08-12 Chip electrical performance testing system and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010805833.0A CN111896856B (en) 2020-08-12 2020-08-12 Chip electrical performance testing system and method

Publications (2)

Publication Number Publication Date
CN111896856A true CN111896856A (en) 2020-11-06
CN111896856B CN111896856B (en) 2023-05-23

Family

ID=73228946

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010805833.0A Active CN111896856B (en) 2020-08-12 2020-08-12 Chip electrical performance testing system and method

Country Status (1)

Country Link
CN (1) CN111896856B (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1612322A (en) * 2003-10-31 2005-05-04 株式会社瑞萨科技 Fabrication method of semiconductor integrated circuit device
CN102749570A (en) * 2012-07-26 2012-10-24 上海宏力半导体制造有限公司 Wafer test device and wafer test method for probe station
CN103094253A (en) * 2011-11-07 2013-05-08 无锡华润上华科技有限公司 Grid oxide layer test structure
CN103456857A (en) * 2013-09-27 2013-12-18 聚灿光电科技(苏州)有限公司 Light-emitting diode (LED) chip and manufacturing method thereof
CN203630173U (en) * 2013-12-09 2014-06-04 中芯国际集成电路制造(北京)有限公司 Probe card
CN105510649A (en) * 2014-10-08 2016-04-20 日本麦可罗尼克斯股份有限公司 Probe card
CN105720145A (en) * 2016-03-25 2016-06-29 山东浪潮华光光电子股份有限公司 Preparation method of multi-chip parallel illumination module
CN108122814A (en) * 2017-10-27 2018-06-05 江西乾照光电有限公司 The sorting transfer method of LED core particle in a kind of LED chip
CN208284493U (en) * 2018-04-26 2018-12-25 江西乾照光电有限公司 A kind of light-emitting diode chip for backlight unit with improvement electrode electromigration ability
CN110361644A (en) * 2019-08-22 2019-10-22 厦门乾照光电股份有限公司 A kind of detection device and method of LED chip electric property

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1612322A (en) * 2003-10-31 2005-05-04 株式会社瑞萨科技 Fabrication method of semiconductor integrated circuit device
CN103094253A (en) * 2011-11-07 2013-05-08 无锡华润上华科技有限公司 Grid oxide layer test structure
CN102749570A (en) * 2012-07-26 2012-10-24 上海宏力半导体制造有限公司 Wafer test device and wafer test method for probe station
CN103456857A (en) * 2013-09-27 2013-12-18 聚灿光电科技(苏州)有限公司 Light-emitting diode (LED) chip and manufacturing method thereof
CN203630173U (en) * 2013-12-09 2014-06-04 中芯国际集成电路制造(北京)有限公司 Probe card
CN105510649A (en) * 2014-10-08 2016-04-20 日本麦可罗尼克斯股份有限公司 Probe card
CN105720145A (en) * 2016-03-25 2016-06-29 山东浪潮华光光电子股份有限公司 Preparation method of multi-chip parallel illumination module
CN108122814A (en) * 2017-10-27 2018-06-05 江西乾照光电有限公司 The sorting transfer method of LED core particle in a kind of LED chip
CN208284493U (en) * 2018-04-26 2018-12-25 江西乾照光电有限公司 A kind of light-emitting diode chip for backlight unit with improvement electrode electromigration ability
CN110361644A (en) * 2019-08-22 2019-10-22 厦门乾照光电股份有限公司 A kind of detection device and method of LED chip electric property

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
李支康等: "基于共晶键合技术的CMUTs结构设计与试验测试" *

Also Published As

Publication number Publication date
CN111896856B (en) 2023-05-23

Similar Documents

Publication Publication Date Title
US7973331B2 (en) Light-emitting device
EP1653510A3 (en) Semiconductor device and manufacturing method of the same
WO2014060355A3 (en) Method for producing a multiplicity of optoelectronic semiconductor components
TW200611305A (en) Package structure, fabrication method thereof and method of electrically connecting a plurality of semiconductor chips in a vertical stack
US20110156236A1 (en) Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
WO2003107444A3 (en) Light-emitting diode electrode geometry
CN105428474B (en) A kind of simple making method of efficient LED chip
KR20140122689A (en) Led component by integrating epitaxial structure and package substrate together and method of manufacturing the same
KR20090034788A (en) Integrated circuit package system including die having relieved active region
CN103107163B (en) Semiconductor test structure and forming method and testing method thereof
CN102324390B (en) Rectifier diode core manufacturing method
CN111896856B (en) Chip electrical performance testing system and method
CN101604715A (en) Gallium nitride LED chip and preparation method thereof
CN101750563B (en) Structure for detecting short circuit of through holes or contact holes in semiconductor device
EP1367645A3 (en) Semiconductor device and manufacturing method thereof
TWI405308B (en) Package and fabricating method thereof
CN108120869A (en) A kind of test method of metal semiconductor interface recombination current density
US20050274971A1 (en) Light emitting diode and method of making the same
KR20130071468A (en) Method for producing an optoelectronic semiconductor component, and optoelectronic semiconductor component
CN213124483U (en) LED chip and assembly thereof, AC bridge type rectification assembly and light-emitting equipment
CN101494260B (en) LED element
EP3588570A3 (en) Display module, display device, and method of manufacturing the display module
CN103887150A (en) Method for preparing test sample
CN217387195U (en) Flip-chip type MICROLED chip structure
CN202534653U (en) Mesa-type unidirectional negative resistance diode chip

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant