CN103456857A - Light-emitting diode (LED) chip and manufacturing method thereof - Google Patents
Light-emitting diode (LED) chip and manufacturing method thereof Download PDFInfo
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- CN103456857A CN103456857A CN2013104527813A CN201310452781A CN103456857A CN 103456857 A CN103456857 A CN 103456857A CN 2013104527813 A CN2013104527813 A CN 2013104527813A CN 201310452781 A CN201310452781 A CN 201310452781A CN 103456857 A CN103456857 A CN 103456857A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 125
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000002360 preparation method Methods 0.000 claims description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 11
- 239000011259 mixed solution Substances 0.000 claims description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000009616 inductively coupled plasma Methods 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 5
- 241000208340 Araliaceae Species 0.000 description 3
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 3
- 235000003140 Panax quinquefolius Nutrition 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 235000008434 ginseng Nutrition 0.000 description 3
- 230000011218 segmentation Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000002224 dissection Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
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Abstract
The invention discloses a light-emitting diode (LED) chip and a manufacturing method thereof. The LED chip comprises a substrate, a semiconductor epitaxial layer located on the substrate, a transparent conductive layer located on the semiconductor epitaxial layer, a P electrode located on the transparent conductive layer and an N electrode on the semiconductor epitaxial layer, wherein all of or a part of side walls of the semiconductor epitaxial layer and the substrate are set to be continuous oblique planes. Under the condition that the overall size of the chip is not increased, the light-emitting area of the chip is increased through design improvement. In addition, additional process steps are not increased, the original cost is maintained, and the photoelectric property of the chip is improved.
Description
Technical field
The present invention relates to technical field of semiconductor luminescence, particularly relate to a kind of LED chip and preparation method thereof.
Background technology
Light-emitting diode (Light-Emitting Diode, LED) is the luminous semi-conductor electricity sub-element of a kind of energy.This electronic component occurred as far back as 1962, can only send in early days the ruddiness of low luminosity, developed afterwards other monochromatic versions, and the light that can send has even to this day spreaded all over visible ray, infrared ray and ultraviolet ray, and luminosity is also brought up to suitable luminosity.And purposes is also by the beginning as indicator light, display panel etc.; Along with the continuous progress of technology, light-emitting diode has been widely used in display, television set daylighting is decorated and illumination.
The LED chip making technology is as follows:
The non-doping semiconductor layer of epitaxial growth, n type semiconductor layer, multiple quantum well light emitting layer, p type semiconductor layer successively on substrate, form the LED wafer;
The LED wafer exposes the N type semiconductor table top through photoetching, etching, and the N type semiconductor table top comprises the N-type metal electric polar region of single core grain and the isolated groove between the core grain, and this isolated groove cross section is the type, is called the N-type isolated groove, width 20～40 μ m;
After LED chip completes, finally it is divided into to single core grain from whole wafer, chip manufacturing complete and substrate thinning after, directly carry out the stealthy cutting of laser, cutting, along the N-type isolated groove of chip chamber, is carried out splitting afterwards again, and the core grain is separated.
While cutting apart the core grain, the invisible laser dissection, in the middle of substrate, easily produces the oblique segmentation problem during splitting, in order to make chip surface, keeps complete, and chip chamber N-type isolated groove must guarantee to have certain width, and this will lose light-emitting area greatly.
Therefore, for above-mentioned technical problem, be necessary to provide a kind of new LED chip and preparation method thereof.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of LED chip that has improved light-emitting area and preparation method thereof.
To achieve these goals, the technical scheme that the embodiment of the present invention provides is as follows:
A kind of LED chip, described LED chip comprises substrate, be positioned at semiconductor epitaxial layers on substrate, be positioned at the transparency conducting layer on semiconductor epitaxial layers and be positioned at P electrode on transparency conducting layer and the N electrode on semiconductor epitaxial layers, and all or part of sidewall of described semiconductor epitaxial layers and substrate is set to continuous inclined-plane.
As a further improvement on the present invention, described semiconductor epitaxial layers comprises n type semiconductor layer, luminescent layer, the p type semiconductor layer be positioned at successively on substrate, described P electrode is positioned on transparency conducting layer and by transparency conducting layer and p type semiconductor layer and is electrically connected, n type semiconductor layer is provided with the N type semiconductor table top, and the N electrode is positioned on the N type semiconductor table top.
As a further improvement on the present invention, described semiconductor epitaxial layers is being positioned at N type semiconductor table top place, the following sidewall of N type semiconductor table-surface level face is made as inclined-plane, the above sidewall of N type semiconductor table-surface level face is vertical plane, and semiconductor epitaxial layers is continuous inclined-plane at the sidewall that is positioned at N type semiconductor table top outside.
As a further improvement on the present invention, described semiconductor epitaxial layers also comprises is located at the non-doping semiconductor layer of going back between n type semiconductor layer and substrate, and the sidewall of described non-doping semiconductor layer and all or part of n type semiconductor layer, all or part of substrate is set to continuous inclined-plane.
As a further improvement on the present invention, described transparency conducting layer below also is provided with the current blocked layer, and described current blocked layer is positioned at the below of P electrode, and the current blocked layer is SiO
2, Si
3n
4, SiO
xn
y.
As a further improvement on the present invention, the vertical depth on described inclined-plane is 15～40 μ m, and the horizontal range on inclined-plane is 1～10 μ m.
Correspondingly, a kind of preparation method of LED chip said method comprising the steps of:
S1, provide a substrate, at the Grown semiconductor epitaxial layers, form the LED wafer, described semiconductor epitaxial layers comprises n type semiconductor layer, luminescent layer and the p type semiconductor layer upwards set gradually from substrate;
Form the N type semiconductor table section on S2, the n type semiconductor layer in semiconductor epitaxial layers;
S3, SiO grows on semiconductor epitaxial layers
2masking layer carries out the laser cutting-up in the middle of the adjacent core grain, and forming two inclined-planes is V-groove, SiO
2the thickness of masking layer is 0.2～2 μ m, and the V-groove degree of depth is 15～40 μ m, and top width is 2～20 μ m;
S4, the mixed solution that whole LED wafer is placed in to SPA and the concentrated sulfuric acid are corroded;
S5, removal SiO
2masking layer, form the V-type isolated groove at the core intergranular;
S6, make transparency conducting layer on semiconductor epitaxial layers, and carry out annealing in process;
S7, make P electrode and N electrode respectively on transparency conducting layer and N type semiconductor table top;
S8, the LED wafer is thinned to thickness the polishing of 60～200um;
S9, the LED wafer is carried out to splitting along the V-type isolated groove, the core grain is separated and forms some LED chips.
As a further improvement on the present invention, in the mixed solution of described step S4, SPA and concentrated sulfuric acid volume ratio are 1:1～1:3, and the temperature of described mixed solution is 200～300 ℃.
As a further improvement on the present invention, in described step S2, also comprise:
Forming sidewall on n type semiconductor layer in semiconductor epitaxial layers is vertically disposed N-type isolated groove, and for the laser cutting-up is collimated, described N-type isolated groove width is less than the top width of V-groove, and N-type isolated groove width is 1～20 μ m.
As a further improvement on the present invention, described step S2 completes by photoetching or inductively coupled plasma engraving method.
Compared with prior art, LED chip of the present invention and preparation method thereof in the situation that do not increase the chip overall dimensions, passes through design improvement, increased the light-emitting area of chip, and do not increase additional technical steps, maintained original cost, promoted the photoelectric properties of chip.
The accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, the accompanying drawing the following describes is only some embodiment that put down in writing in the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The vertical section structure schematic diagram that Fig. 1 is single LEDs chip in first embodiment of the invention;
The plan structure schematic diagram that Fig. 2 is single LEDs chip in first embodiment of the invention;
The vertical section structure schematic diagram that Fig. 3 is adjacent LED chip in first embodiment of the invention;
The plan structure schematic diagram that Fig. 4 is LED wafer in first embodiment of the invention;
The plan structure schematic diagram that Fig. 5 is LED wafer in second embodiment of the invention.
Embodiment
In order to make those skilled in the art person understand better the technical scheme in the present invention, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment obtained, should belong to the scope of protection of the invention.
In addition, may use label or the sign of repetition in different embodiment.These only repeat, in order simply clearly to narrate the present invention, not represent between discussed different embodiment and/or structure and to have any relevance.
The present invention discloses a kind of LED chip, comprise substrate, be positioned at semiconductor epitaxial layers on substrate, be positioned at the transparency conducting layer on semiconductor epitaxial layers and be positioned at P electrode on transparency conducting layer and the N electrode on semiconductor epitaxial layers, semiconductor epitaxial layers comprises n type semiconductor layer, luminescent layer, p type semiconductor layer, the P electrode is positioned on transparency conducting layer and by transparency conducting layer and p type semiconductor layer and is electrically connected, n type semiconductor layer is provided with the N type semiconductor table top, and the N electrode is positioned on the N type semiconductor table top.Wherein, all or part of sidewall of semiconductor epitaxial layers and substrate is set to continuous inclined-plane.
Ginseng Figure 1 shows that the sectional structure schematic diagram of LED chip in the first execution mode of the present invention, and LED chip is respectively from bottom to up:
Substrate 1, substrate can be sapphire, Si, SiC, GaN, ZnO etc.;
Non-doping semiconductor layer 2, non-doping semiconductor layer can be GaN etc.;
N type semiconductor layer 3, n type semiconductor layer can be N-type GaN etc.N type semiconductor layer 3 is provided with N type semiconductor table top 31;
Luminescent layer 4, luminescent layer can be GaN, InGaN etc.;
P type semiconductor layer 5, p type semiconductor layer can be P type GaN etc.;
Transparency conducting layer 6 can be transparency conducting layer ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, In
4sn
3o
12, NiAu etc., the transparency conducting layer below also is provided with current blocked layer 7, current blocked layer 7 is positioned at the below of P electrode, the current blocked layer can be SiO
2, Si
3n
4, SiO
xn
ydeng;
Shown in Fig. 2, in the present embodiment, on the corresponding sidewall of N type semiconductor table top 31, the sidewall of below the 31 and position of part substrate more than 1 of N type semiconductor table top is set to continuous inclined-plane; On all the other positions, the sidewall of part substrate 1, non-doping semiconductor layer 2, n type semiconductor layer 3, luminescent layer 4, p type semiconductor layer 5 all is set to continuous inclined-plane, and corresponding bevel angle is symmetrical arranged.The vertical depth on inclined-plane is 15～40 μ m, and the horizontal range on inclined-plane is 1～10 μ m.
As shown in Figure 3, not before splitting, because the chip sidewall is set to continuous inclined-plane, between two adjacent LED chips, be formed with V-type isolated groove 10 at LED chip, the vertical depth of V-type isolated groove 10 is 15～40 μ m, and the top width of V-type isolated groove 10 is 2～20 μ m.Using the V-type isolated groove as core intergranular isolated groove, and its top width is much smaller than the isolated groove of stealth cutting, and the efficient lighting area of single core grain can enlarge 5% left and right.
Correspondingly, in present embodiment, the preparation method of LED chip specifically comprises the following steps:
S1, provide a substrate, at the Grown semiconductor epitaxial layers, form the LED wafer, semiconductor epitaxial layers comprises n type semiconductor layer, luminescent layer and the p type semiconductor layer upwards set gradually from substrate, wherein, substrate can be sapphire, Si, SiC, GaN, ZnO etc., and n type semiconductor layer can be N-type GaN etc., luminescent layer can be GaN, InGaN etc., and p type semiconductor layer can be P type GaN etc.Preferably, the non-doping semiconductor layer of can also first growing on substrate, non-doping semiconductor layer can be GaN etc.;
S2, form the N type semiconductor table section on the n type semiconductor layer in semiconductor epitaxial layers by photoetching or inductively coupled plasma etching method;
S3, SiO grows on semiconductor epitaxial layers
2masking layer carries out the laser cutting-up in the middle of the adjacent core grain, forms V-groove, SiO
2the thickness of masking layer is 0.2～2 μ m, and the V-groove degree of depth is 15～40 μ m, and top width is 2～20 μ m;
S4, the mixed solution that whole LED wafer is placed in to SPA and the concentrated sulfuric acid are corroded, and preferably, in mixed solution, the volume ratio of SPA and the concentrated sulfuric acid is 1:1～1:3, and the temperature of mixed solution is 200～300 ℃;
S5, removal SiO
2masking layer, form the V-type isolated groove at the core intergranular;
S6, make transparency conducting layer on semiconductor epitaxial layers, and carry out annealing in process.Transparency conducting layer can be ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, In
4sn
3o
12, NiAu etc.;
S7, make P electrode and N electrode respectively on transparency conducting layer and N type semiconductor table top, P electrode and N electrode adopt metal material, preferably can select Au, Al etc.;
S8, the LED wafer is thinned to thickness the polishing of 60～200um;
S9, ginseng Fig. 3, Figure 4 shows that the LED wafer obtained after step S1～S8, the LED wafer is carried out to splitting along the V-type isolated groove, the core grain is separated and forms some LED chips.
Preferably, after step S5, also comprise:
Make the current blocked layer under corresponding P electrode, the current blocked layer can be SiO
2, Si
3n
4, SiO
xn
y(x, y are greater than 0 integer).
Before step S8, also comprise:
Make the passivation protection layer, described passivation protection layer can be SiO
2, Si
3n
4, SiO
xn
y(x, y are greater than 0 integer).
Be grown in semiconductor epitaxial layer thickness on substrate general<10 μ m, after the dark V-groove of front laser cutting-up 15～40 μ m, nature is separated the core grain.In the last chip splitting stage, the core grain will split along this V-type isolated groove, even the problem of substrate oblique segmentation is arranged, and semiconductor epitaxial structure that also can injured surface.
In the second execution mode of the present invention, identical in the structure of LED chip and the first execution mode, the manufacture method of different LED chips.
In the present embodiment, shown in ginseng Fig. 5, in step S2, also comprise:
Forming sidewall on n type semiconductor layer in semiconductor epitaxial layers between each core grain is vertically disposed N-type isolated groove 11, and this N-type isolated groove width is less than the top width of V-groove, and N-type isolated groove width is 1～20 μ m.
The N-type isolated groove is for collimating to the laser cutting-up, because the top width of V-groove is greater than the width of N-type isolated groove, after the laser cutting-up, the N-type isolated groove is removed fully, and manufacture craft after this and the first execution mode are identical, at this, are no longer repeated.
In the present embodiment, first prepare the N-type isolated groove for laser is collimated, can improve the making precision of V-groove, improve the efficiency of technique.
As can be seen from the above technical solutions, in LED chip of the present invention and preparation method thereof, the V-type isolated groove is narrower than N-type isolated groove in the stealth cutting, and the efficient lighting area of LED chip can enlarge to both sides.
It is superior that the photoelectric properties of LED chip become along with the increase of its light-emitting area, and the present invention in the situation that do not increase the chip overall dimensions, passes through design improvement, increased the light-emitting area of chip, and do not increase additional technical steps, maintained original cost, promoted the photoelectric properties of chip.
In the chip splitting stage, the core grain will split along this V-type isolated groove in addition, even the problem of substrate oblique segmentation is arranged, and semiconductor epitaxial structure that also can injured surface.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned example embodiment, and in the situation that do not deviate from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore, no matter from which point, all should regard embodiment as exemplary, and be nonrestrictive, scope of the present invention is limited by claims rather than above-mentioned explanation, therefore is intended to include in the present invention dropping on the implication that is equal to important document of claim and all changes in scope.Any Reference numeral in claim should be considered as limit related claim.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should make specification as a whole, and the technical scheme in each embodiment also can, through appropriate combination, form other execution modes that it will be appreciated by those skilled in the art that.
Claims (10)
1. a LED chip, described LED chip comprises substrate, be positioned at semiconductor epitaxial layers on substrate, be positioned at the transparency conducting layer on semiconductor epitaxial layers and be positioned at P electrode on transparency conducting layer and the N electrode on semiconductor epitaxial layers, it is characterized in that, all or part of sidewall of described semiconductor epitaxial layers and substrate is set to continuous inclined-plane.
2. LED chip according to claim 1, it is characterized in that, described semiconductor epitaxial layers comprises n type semiconductor layer, luminescent layer, the p type semiconductor layer be positioned at successively on substrate, described P electrode is positioned on transparency conducting layer and by transparency conducting layer and p type semiconductor layer and is electrically connected, n type semiconductor layer is provided with the N type semiconductor table top, and the N electrode is positioned on the N type semiconductor table top.
3. LED chip according to claim 2, it is characterized in that, described semiconductor epitaxial layers is being positioned at N type semiconductor table top place, the following sidewall of N type semiconductor table-surface level face is made as inclined-plane, the above sidewall of N type semiconductor table-surface level face is vertical plane, and semiconductor epitaxial layers is continuous inclined-plane at the sidewall that is positioned at N type semiconductor table top outside.
4. LED chip according to claim 2, it is characterized in that, described semiconductor epitaxial layers also comprises is located at the non-doping semiconductor layer of going back between n type semiconductor layer and substrate, and the sidewall of described non-doping semiconductor layer and all or part of n type semiconductor layer, all or part of substrate is set to continuous inclined-plane.
5. LED chip according to claim 1, is characterized in that, described transparency conducting layer below also is provided with the current blocked layer, and described current blocked layer is positioned at the below of P electrode, and the current blocked layer is SiO
2, Si
3n
4, SiO
xn
y.
6. LED chip according to claim 1 and 2, is characterized in that, the vertical depth on described inclined-plane is 15～40 μ m, and the horizontal range on inclined-plane is 1～10 μ m.
7. the preparation method of a LED chip, is characterized in that, said method comprising the steps of:
S1, provide a substrate, at the Grown semiconductor epitaxial layers, form the LED wafer, described semiconductor epitaxial layers comprises n type semiconductor layer, luminescent layer and the p type semiconductor layer upwards set gradually from substrate;
Form the N type semiconductor table section on S2, the n type semiconductor layer in semiconductor epitaxial layers;
S3, SiO grows on semiconductor epitaxial layers
2masking layer carries out the laser cutting-up in the middle of the adjacent core grain, and forming two inclined-planes is V-groove, SiO
2the thickness of masking layer is 0.2～2 μ m, and the V-groove degree of depth is 15～40 μ m, and top width is 2～20 μ m;
S4, the mixed solution that whole LED wafer is placed in to SPA and the concentrated sulfuric acid are corroded;
S5, removal SiO
2masking layer, form the V-type isolated groove at the core intergranular;
S6, make transparency conducting layer on semiconductor epitaxial layers, and carry out annealing in process;
S7, make P electrode and N electrode respectively on transparency conducting layer and N type semiconductor table top;
S8, the LED wafer is thinned to thickness the polishing of 60～200um;
S9, the LED wafer is carried out to splitting along the V-type isolated groove, the core grain is separated and forms some LED chips.
8. the preparation method of LED chip according to claim 7, is characterized in that, in the mixed solution of described step S4, SPA and concentrated sulfuric acid volume ratio are 1:1～1:3, and the temperature of described mixed solution is 200～300 ℃.
9. the preparation method of LED chip according to claim 7, is characterized in that, in described step S2, also comprises:
Forming sidewall on n type semiconductor layer in semiconductor epitaxial layers is vertically disposed N-type isolated groove, and for the laser cutting-up is collimated, described N-type isolated groove width is less than the top width of V-groove, and N-type isolated groove width is 1～20 μ m.
10. according to the preparation method of claim 7 or 9 described LED chips, it is characterized in that, described step S2 completes by photoetching or inductively coupled plasma engraving method.
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| CN109427565A (en) * | 2017-09-01 | 2019-03-05 | 晶能光电（江西）有限公司 | A kind of method for cutting wafer |
| CN110010733A (en) * | 2019-03-25 | 2019-07-12 | 大连德豪光电科技有限公司 | The preparation method and light-emitting diode chip for backlight unit of light-emitting diode chip for backlight unit |
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| CN111864025A (en) * | 2019-04-30 | 2020-10-30 | 云谷（固安）科技有限公司 | Micro light-emitting diode, manufacturing method thereof and display device |
| CN111896856A (en) * | 2020-08-12 | 2020-11-06 | 江西乾照光电有限公司 | System and method for testing electrical performance of chip |
| CN113540144A (en) * | 2021-06-18 | 2021-10-22 | 泉州三安半导体科技有限公司 | Wafer for realizing ESD (electro-static discharge) test of multiple LED chips, normally-installed LED chip and manufacturing method thereof |
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