JP2000183218A - Manufacture of ic package - Google Patents

Manufacture of ic package

Info

Publication number
JP2000183218A
JP2000183218A JP10354040A JP35404098A JP2000183218A JP 2000183218 A JP2000183218 A JP 2000183218A JP 10354040 A JP10354040 A JP 10354040A JP 35404098 A JP35404098 A JP 35404098A JP 2000183218 A JP2000183218 A JP 2000183218A
Authority
JP
Japan
Prior art keywords
step
ic
dicing blade
blade
dicing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10354040A
Other languages
Japanese (ja)
Inventor
Toshimitsu Maki
Shuichi Sawamoto
俊光 巻
修一 澤本
Original Assignee
Mitsumi Electric Co Ltd
ミツミ電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsumi Electric Co Ltd, ミツミ電機株式会社 filed Critical Mitsumi Electric Co Ltd
Priority to JP10354040A priority Critical patent/JP2000183218A/en
Publication of JP2000183218A publication Critical patent/JP2000183218A/en
Application status is Withdrawn legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an IC package for improving quality and productivity in a dicing process after the molding of a resin package. SOLUTION: Plural IC chips 20 are loaded on the surface of a printed board 50, and the plural IC chips 20 are sealed by a resin package 40. Then, the resin package 40 and a pattern 52 on the surface of the print board are cut by a first dicing blade 61 (a first process), and then a main body 51 of the print board 50 is cut by a second dicing blade 62 (a second process).

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、ICパッケージの製造方法、特にパッケージの切断方法に関する。 The present invention relates to a method of manufacturing an IC package, a method of particular package cutting.

【0002】 [0002]

【従来の技術】近年、携帯電話等の小型機器への適用から生ずるICパッケージの小型化および薄型化の要望に応えて、CSP(チップ・スケール・パッケージ)やB In recent years, to meet the demands of smaller and thinner of IC packages resulting from the application to small devices such as mobile phones, CSP (chip scale package) and B
GA(ボール・グリッド・アレイ)方式のICパッケージが検討されている。 IC package of GA (ball grid array) system has been studied.

【0003】図2は、CSP型ICパッケージの一例を示す断面図である。 [0003] Figure 2 is a sectional view showing an example of a CSP type IC package. この図において、10は平坦なリードフレームであり、その中央にはICチップ20をダイボンディングするアイランド部11が形成されている。 In this figure, 10 is a flat lead frame, the island portion 11 for die-bonding the IC chip 20 in the center is formed.
リードフレーム10の周辺には、ICチップ20の上部電極との間をボンディングワイヤ30で接続するリード部12が形成されている。 Around the lead frame 10, the lead portion 12 that connects the upper electrode of the IC chip 20 by bonding wires 30 are formed. ICチップ20の周囲は樹脂パッケージ40によって封止される。 Around the IC chip 20 is sealed by the resin package 40.

【0004】図3(a)および(b)は、BGA型IC [0004] FIGS. 3 (a) and (b), BGA type IC
パッケージの一例を示す平面図および断面図である。 Plan view showing an example of a package and a cross-sectional view. 本例では、ICチップ20の搭載にプリント基板50を使用する。 In the present example, the printed circuit board 50 to the mounting of the IC chip 20. このプリント基板50は、緩衝材(インターポーザー)となるポリイミド製の基板本体51の表面側に、ICチップ20を搭載するアイランド部および必要な導体部を印刷した導体パターン52を形成してある。 The printed circuit board 50, the surface side of the cushioning material polyimide substrate body 51 made of a (interposer), is formed a conductor pattern 52 printed with the island portion and the required conductor portion for mounting the IC chip 20.
ICチップ20の上部電極21と導体パターン52との間はボンディングワイヤ30で接続される。 Between the upper electrode 21 and the conductor pattern 52 of the IC chip 20 are connected by a bonding wire 30. ICチップ20の周囲は樹脂パッケージ40で封止される。 Around the IC chip 20 is sealed by the resin package 40.

【0005】基板本体51の裏面側には外部端子となるパターン53を印刷形成してある。 [0005] On the back side of the substrate main body 51 are formed by printing a pattern 53 serving as an external terminal. 表面側のパターン5 Pattern of the surface side 5
2と裏面側のパターン53とはスルーホール54で接続される。 The 2 and the back side of the pattern 53 are connected by the through hole 54. 裏面側のパターン53の表面には、外部端子となる半田ボール55が熱溶着されている。 On the surface of the back side of the pattern 53, the solder balls 55 serving as external terminals are thermally welded.

【0006】複数のICチップは共通の樹脂パッケージに封止された後、切断されて個々のICパッケージに分離される。 [0006] After the plurality of IC chips sealed in a common resin package, it is cut and separated into individual IC packages. この切断は一般に金属またはボンド材+ダイアモンド製のダイシングブレードを用いるダイサーで行われる。 This cleavage is generally carried out at a dicer using a metal or dicing blade bonding material + made diamonds.

【0007】図4(a)の断面図は、2つのICチップ20A,20Bを共通の樹脂パッケージ40で封止した切断前の状態を模式的に示してある。 [0007] sectional view of FIG. 4 (a), two IC chips 20A, a state before cutting sealing the 20B in common resin package 40 is shown schematically. この状態で、IC In this state, IC
チップ20A,20Bの中間をダイシングブレード60 Chips 20A, 20B dicing blade intermediate 60
で切断すると、2つの個別ICパッケージ40A,40 In the cutting, two separate IC package 40A, 40
Bに分割できる。 It can be divided into B.

【0008】 [0008]

【発明が解決しようとする課題】従来のダイシング方法では、1回のダイシングで樹脂パッケージ40とプリント基板50の双方を同時に切断するため、効率はよいが、ブレード60により基板本体51の切断面に生ずる荒れ、並びに基板本体51と表面パターン52の接合界面へのストレス付与という問題を残す。 In [Problems that the Invention is to Solve Conventional dicing method, for simultaneously cutting both the resin package 40 and the printed circuit board 50 in a single dicing, the efficiency is better, by a blade 60 to the cutting surface of the substrate main body 51 resulting rough and leave the problem of stressing to the bonding interface of the substrate main body 51 and the surface pattern 52.

【0009】また、配線を電解メッキで作成している場合には、特性検査は切断後に行われるため、個別のIC Further, if you are creating a wiring by electroplating, since the characteristic inspection is performed after the cutting, the individual IC
パッケージを1個毎に検査する必要があり、効率が悪い。 There is a need to check the package for each one, efficiency is poor. 分割された複数のICパッケージを一括検査しようとすれば、複数のICパッケージ40A,40Bをテープで固定する必要があるが、これだけでは位置精度にばらつきが生じてコンタクト方法が複雑になる。 If the divided plurality of IC packages were trying to batch testing, a plurality of IC packages 40A, although 40B and is necessary to fix a tape, the contact method is complicated by variations occur in the positional accuracy just this.

【0010】本発明は、樹脂パッケージのモールド後のダイシング工程で品質および生産性を向上させることのできるICパッケージの製造方法を提供することを目的としている。 [0010] The present invention aims to provide a manufacturing method of the IC package capable of improving the quality and productivity in the dicing process after the molding of the resin package.

【0011】 [0011]

【課題を解決するための手段】本発明の上記目的は、プリント基板の表面上に複数のICチップを搭載する工程と、前記複数のICチップを共通の樹脂パッケージで封止する工程と、前記樹脂パッケージおよび前記プリント基板表面のパターンをダイシングブレードで切断する第1の工程と、前記プリント基板の本体をダイシングブレードで切断する第2の工程とを備えるICパッケージの製造方法で達成できる。 The above object of the present invention solve problems which means for a] includes the step of mounting a plurality of IC chips on the surface of the printed circuit board, a step of sealing the plurality of IC chips in a common resin package, the a first step of cutting a pattern of the resin package and the printed circuit board surface with a dicing blade can be achieved in the manufacturing method of the IC package and a second step of cutting the main body of the printed circuit board by a dicing blade.

【0012】本発明の実施の形態では、前記第2の工程は、前記第1の工程と同じ種類のダイシングブレードで行われるか、あるいは前記第1の工程のダイシングブレードとは異なる種類のダイシングブレードで行われる。 [0012] In the embodiment of the present invention, the second step, the first step and either performed with the same type of the dicing blade, or the first step different types of the dicing blade and dicing blade It is carried out at.
後者の場合、前記第2の工程は、例えば前記第1の工程のダイシングブレードより幅狭の異なるダイシングブレードで行われる。 In the latter case, the second step, the width takes place in a narrow differs dicing blade from the dicing blade, for example the first step. 更に、前記第1の工程と前記第2の工程の間に、特性検査工程を更に備えることができる。 Furthermore, between the first step and the second step may further include a characteristic inspection process.

【0013】 [0013]

【発明の実施の形態】以下、図面に示した実施形態を参照して、本発明を詳細に説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, with reference to embodiments shown in the drawings, the present invention will be described in detail. 図1(a)〜(d) Figure 1 (a) ~ (d)
は、本発明の一実施形態に係るICパッケージの製造方法を示す工程図である。 Is a process diagram showing the manufacturing method of the IC package according to an embodiment of the present invention. 図1(a)は、プリント基板5 1 (a) is a printed circuit board 5
0の表面上に複数のICチップ20A,20Bを搭載する工程と、前記複数のICチップ20A,20Bを共通の樹脂パッケージ40で封止する工程とを経た状態を示している。 A plurality of IC chips 20A on the surface of 0 indicates a step of mounting 20B, a state in which after the step of sealing said plurality of IC chips 20A, and 20B with a common resin package 40. プリント基板50の構成は、図4と同様である。 Configuration of the printed circuit board 50 is similar to FIG.

【0014】図1(b)は、樹脂パッケージ40およびプリント基板50表面のパターン52を第1のダイシングブレード61で切断する第1の工程を示している。 [0014] FIG. 1 (b) shows a first step of cutting the pattern 52 of the resin package 40 and the printed circuit board 50 surface in a first dicing blade 61. この第1の工程では、樹脂パッケージ40は完全に切断されて、個別の樹脂パッケージ40A,40Bとなる。 In the first step, the resin package 40 is completely cut, the individual resin package 40A, the 40B. 同時に、プリント基板50は、その表面パターン52だけが切断され、基板本体51は連結したままの状態を保つ。 At the same time, the printed circuit board 50, only the surface pattern 52 is cut, the substrate main body 51 keeps the remains linked.

【0015】この後、第1のブレード61を引き上げると、図1(c)に示すように、樹脂パッケージ40A, [0015] Thereafter, by pulling the first blade 61, as shown in FIG. 1 (c), the resin package 40A,
40B間に溝41が残る。 Groove 41 remains between 40B. この状態では、基板本体51 In this state, the substrate main body 51
が連続しているので、複数のICパッケージ40A,4 Since There are continuous, a plurality of IC packages 40A, 4
0Bを配列し直すことなく、これらに対する特性検査を実施できる。 Without rearranging the 0B, it can be carried out property inspection for these.

【0016】上記の特性検査実施後に、図1(d)に示すように、基板本体51を第2のダイシングブレード6 [0016] After the above characteristic test performed, as shown in FIG. 1 (d), the substrate main body 51 second dicing blade 6
2で完全に切断して、個別のICパッケージ40A,4 Completely digested with 2, separate IC package 40A, 4
0Bを分離する(第2の工程)。 Separating 0B (second step). この第2の工程で使用される第2のブレード62は、第1のブレード61と同じ種類のものでも良いが、異なる種類の第2のブレード62を使用すると、ダイシング面の粗さをダイシングする材料に合わせて細かくすることができる。 Second blade 62 used in this second step may be of the same type as the first blade 61, but using the second blade 62 of different kinds, dicing the dicing surface roughness it can be finely in accordance with the material.

【0017】第2のブレード62の種類は、ブレードの材質だけではなく、第1のブレード61で形成された溝41の幅より狭い幅を持つものとする事ができる。 The type of the second blade 62 is not only the blade material, it can be assumed to have a width less than the width of the groove 41 formed in the first blade 61. この実施形態で示す第1の工程と第2の工程は、逆にすることもできる。 The first and second steps shown in this embodiment can also be reversed. 即ち、第1の工程で基板本体51を切断し、第2の工程で表面パターン52と樹脂パッケージ4 That is, by cutting the substrate main body 51 in the first step, the second surface pattern 52 in step and the resin package 4
0を切断する、という順序である。 0 to cleave a sequence called.

【0018】上述した本発明のICパッケージ製造方法には、次の利点がある。 [0018] The IC package manufacturing method of the present invention described above has the following advantages. (1)材料毎にブレードを選定できるので、ダイシング面の粗さを細かくすることが可能である。 (1) it is possible to select a blade for each material, it is possible to finely dicing surface roughness. (2)ブレードへの負荷が少ないため、薄い刃の使用が可能になる。 (2) because the load on the blade is small, it is possible to use a thin blade. この結果、高密度実装が可能になるので、低コスト化を図ることができる。 This results in high-density mounting, it is possible to reduce the cost. (3)ブレードへの負荷が少ないため、ブレードの寿命が長くなる。 (3) because the load on the blade is small, the lifetime of the blade becomes longer. (4)不要な配線部を第1の工程で切断して除去する事により、板状でのマルチ測定が可能となり、テスト効率が向上する。 (4) by removing an unnecessary wiring portion is cut in the first step, it is possible to multi-measurement in the plate, thereby improving testing efficiency.

【0019】 [0019]

【発明の効果】以上述べたように本発明によれば、樹脂パッケージのモールド後のダイシング工程で品質および生産性を向上させることのできるICパッケージの製造方法を実現できる。 According to the present invention as described above, according to the present invention, a manufacturing method of the IC package capable of improving the quality and productivity in the dicing process after the molding of the resin package can be realized.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の一実施形態に係るICパッケージの製造方法を示す工程図である。 1 is a process diagram showing the manufacturing method of the IC package according to an embodiment of the present invention.

【図2】 CSP型ICパッケージの一例を示す断面図である。 2 is a sectional view showing an example of a CSP type IC package.

【図3】 BGA型ICパッケージの一例を示す平面図および断面図である。 3 is a plan view and a sectional view showing an example of a BGA type IC package.

【図4】 従来のICパッケージの切断方法を示す断面図である。 4 is a sectional view showing a cutting method of a conventional IC package.

【符号の説明】 DESCRIPTION OF SYMBOLS

20 ICチップ 30 ボンディングワイヤ 40 樹脂パッケージ 50 プリント基板 51 基板本体 52 表面パターン 53 裏面パターン 54 スルーホール 61 第1のダイシングブレード 62 第2のダイシングブレード 20 IC chip 30 bonding wire 40 a resin package 50 PCB 51 substrate main body 52 surface pattern 53 back-side pattern 54 through-hole 61 first dicing blade 62 second dicing blade

Claims (5)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 プリント基板の表面上に複数のICチップを搭載する工程と、 前記複数のICチップを共通の樹脂パッケージで封止する工程と、 前記樹脂パッケージおよび前記プリント基板表面のパターンをダイシングブレードで切断する第1の工程と、 前記プリント基板の本体をダイシングブレードで切断する第2の工程とを備えることを特徴とするICパッケージの製造方法。 Dicing with claim 1 wherein the step of mounting a plurality of IC chips on the surface of the printed circuit board, a step of sealing the plurality of IC chips in a common resin package, a pattern of the resin package and the printed circuit board surface the first step and the second step of the manufacturing method of the IC package characterized in that it comprises a cutting with the body of the dicing blade of the printed circuit board to be cut with the blade.
  2. 【請求項2】 前記第2の工程は、前記第1の工程と同じ種類のダイシングブレードで行われることを特徴とする請求項1のICパッケージの製造方法。 Wherein said second step is the manufacturing method of the IC package according to claim 1, characterized in that it is performed in the first of the same type of the dicing blade and process.
  3. 【請求項3】 前記第2の工程は、前記第1の工程のダイシングブレードとは異なる種類のダイシングブレードで行われることを特徴とする請求項1のICパッケージの製造方法。 Wherein the second step is the manufacturing method of the IC package according to claim 1, characterized in that it is performed in a different kind of the dicing blade and dicing blade of the first step.
  4. 【請求項4】 前記第2の工程は、前記第1の工程のダイシングブレードより幅狭の異なるダイシングブレードで行われることを特徴とする請求項3のICパッケージの製造方法。 Wherein said second step is the manufacturing method of the IC package according to claim 3, characterized in that it is performed in the first width than the dicing blade steps narrow differs dicing blade.
  5. 【請求項5】 前記第1の工程と前記第2の工程の間に、特性検査工程を更に備えることを特徴とする請求項1〜4のいずれかのICパッケージの製造方法。 5. During the first step and the second step, the manufacturing method of any of the IC package according to claim 1 to 4, further comprising a characteristic inspection process.
JP10354040A 1998-12-14 1998-12-14 Manufacture of ic package Withdrawn JP2000183218A (en)

Priority Applications (1)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
JP2000183218A true JP2000183218A (en) 2000-06-30

Family

ID=18434919

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Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003031526A (en) * 2001-07-16 2003-01-31 Gs-Melcotec Co Ltd Module and manufacturing method thereof
JP2010050489A (en) * 2001-06-07 2010-03-04 Renesas Technology Corp Semiconductor device
US7781089B2 (en) 2005-05-11 2010-08-24 Ricoh Company, Ltd. Protection circuit module for a secondary battery and a battery package using same
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JP2010050489A (en) * 2001-06-07 2010-03-04 Renesas Technology Corp Semiconductor device
JP2003031526A (en) * 2001-07-16 2003-01-31 Gs-Melcotec Co Ltd Module and manufacturing method thereof
US7781089B2 (en) 2005-05-11 2010-08-24 Ricoh Company, Ltd. Protection circuit module for a secondary battery and a battery package using same
JP2011512683A (en) * 2008-02-22 2011-04-21 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングOsram Opto Semiconductors GmbH Method of making a plurality of beam emitting components and beam emitting components
US8790939B2 (en) 2008-02-22 2014-07-29 Osram Opto Semiconductors Gmbh Method for producing a plurality of radiation-emitting components and radiation-emitting component
KR101525638B1 (en) * 2008-02-22 2015-06-03 오스람 옵토 세미컨덕터스 게엠베하 Method for producing a plurality of radiation emitting components and radiation emitting component
CN103855058A (en) * 2012-12-03 2014-06-11 东和株式会社 Apparatus and method for manufacturing electronic component
JP2014108491A (en) * 2012-12-03 2014-06-12 Towa Corp Cutting apparatus and method for manufacturing electronic component
CN103855058B (en) * 2012-12-03 2016-09-07 东和株式会社 Electronic components fabrication device and manufacture method
TWI551414B (en) * 2012-12-03 2016-10-01 Towa Corp Electronic component manufacturing apparatus and manufacturing method thereof
US9543205B2 (en) 2014-10-22 2017-01-10 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
CN106115007A (en) * 2016-08-30 2016-11-16 江门全合精密电子有限公司 A kind of can the packer of surface trimming

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