JP2000183218A - Manufacture of ic package - Google Patents
Manufacture of ic packageInfo
- Publication number
- JP2000183218A JP2000183218A JP10354040A JP35404098A JP2000183218A JP 2000183218 A JP2000183218 A JP 2000183218A JP 10354040 A JP10354040 A JP 10354040A JP 35404098 A JP35404098 A JP 35404098A JP 2000183218 A JP2000183218 A JP 2000183218A
- Authority
- JP
- Japan
- Prior art keywords
- package
- blade
- dicing
- dicing blade
- resin package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＩＣパッケージの
製造方法、特にパッケージの切断方法に関する。The present invention relates to a method for manufacturing an IC package, and more particularly to a method for cutting a package.
【０００２】[0002]
【従来の技術】近年、携帯電話等の小型機器への適用か
ら生ずるＩＣパッケージの小型化および薄型化の要望に
応えて、ＣＳＰ（チップ・スケール・パッケージ）やＢ
ＧＡ（ボール・グリッド・アレイ）方式のＩＣパッケー
ジが検討されている。2. Description of the Related Art In recent years, in response to the demand for smaller and thinner IC packages resulting from application to small devices such as mobile phones, CSP (chip scale package) and B
A GA (ball grid array) type IC package is being studied.
【０００３】図２は、ＣＳＰ型ＩＣパッケージの一例を
示す断面図である。この図において、１０は平坦なリー
ドフレームであり、その中央にはＩＣチップ２０をダイ
ボンディングするアイランド部１１が形成されている。
リードフレーム１０の周辺には、ＩＣチップ２０の上部
電極との間をボンディングワイヤ３０で接続するリード
部１２が形成されている。ＩＣチップ２０の周囲は樹脂
パッケージ４０によって封止される。FIG. 2 is a sectional view showing an example of a CSP type IC package. In this figure, reference numeral 10 denotes a flat lead frame, and an island portion 11 for die-bonding the IC chip 20 is formed at the center thereof.
At the periphery of the lead frame 10, a lead portion 12 for connecting with an upper electrode of the IC chip 20 by a bonding wire 30 is formed. The periphery of the IC chip 20 is sealed with a resin package 40.
【０００４】図３（ａ）および（ｂ）は、ＢＧＡ型ＩＣ
パッケージの一例を示す平面図および断面図である。本
例では、ＩＣチップ２０の搭載にプリント基板５０を使
用する。このプリント基板５０は、緩衝材（インターポ
ーザー）となるポリイミド製の基板本体５１の表面側
に、ＩＣチップ２０を搭載するアイランド部および必要
な導体部を印刷した導体パターン５２を形成してある。
ＩＣチップ２０の上部電極２１と導体パターン５２との
間はボンディングワイヤ３０で接続される。ＩＣチップ
２０の周囲は樹脂パッケージ４０で封止される。FIGS. 3A and 3B show a BGA type IC.
It is a top view and a sectional view showing an example of a package. In this example, the printed circuit board 50 is used for mounting the IC chip 20. The printed circuit board 50 has a conductor pattern 52 on which an island portion on which the IC chip 20 is mounted and a necessary conductor portion are printed on the front side of a polyimide substrate body 51 serving as a buffer material (interposer).
The upper electrode 21 of the IC chip 20 and the conductor pattern 52 are connected by a bonding wire 30. The periphery of the IC chip 20 is sealed with a resin package 40.
【０００５】基板本体５１の裏面側には外部端子となる
パターン５３を印刷形成してある。表面側のパターン５
２と裏面側のパターン５３とはスルーホール５４で接続
される。裏面側のパターン５３の表面には、外部端子と
なる半田ボール５５が熱溶着されている。A pattern 53 serving as an external terminal is printed and formed on the back side of the substrate body 51. Pattern 5 on the front side
2 and the pattern 53 on the back side are connected by a through hole 54. A solder ball 55 serving as an external terminal is heat-welded to the surface of the pattern 53 on the back side.
【０００６】複数のＩＣチップは共通の樹脂パッケージ
に封止された後、切断されて個々のＩＣパッケージに分
離される。この切断は一般に金属またはボンド材＋ダイ
アモンド製のダイシングブレードを用いるダイサーで行
われる。[0006] After a plurality of IC chips are sealed in a common resin package, they are cut and separated into individual IC packages. This cutting is generally performed by a dicer using a dicing blade made of metal or a bond material + diamond.
【０００７】図４（ａ）の断面図は、２つのＩＣチップ
２０Ａ，２０Ｂを共通の樹脂パッケージ４０で封止した
切断前の状態を模式的に示してある。この状態で、ＩＣ
チップ２０Ａ，２０Ｂの中間をダイシングブレード６０
で切断すると、２つの個別ＩＣパッケージ４０Ａ，４０
Ｂに分割できる。FIG. 4A is a cross-sectional view schematically showing a state before two IC chips 20A and 20B are sealed with a common resin package 40 before cutting. In this state, the IC
A dicing blade 60 is provided between the chips 20A and 20B.
And cut the two individual IC packages 40A, 40A
B.
【０００８】[0008]
【発明が解決しようとする課題】従来のダイシング方法
では、１回のダイシングで樹脂パッケージ４０とプリン
ト基板５０の双方を同時に切断するため、効率はよい
が、ブレード６０により基板本体５１の切断面に生ずる
荒れ、並びに基板本体５１と表面パターン５２の接合界
面へのストレス付与という問題を残す。In the conventional dicing method, both the resin package 40 and the printed board 50 are cut simultaneously by one dicing, so that the efficiency is high. There remains a problem of the resulting roughness and the application of stress to the bonding interface between the substrate body 51 and the surface pattern 52.
【０００９】また、配線を電解メッキで作成している場
合には、特性検査は切断後に行われるため、個別のＩＣ
パッケージを１個毎に検査する必要があり、効率が悪
い。分割された複数のＩＣパッケージを一括検査しよう
とすれば、複数のＩＣパッケージ４０Ａ，４０Ｂをテー
プで固定する必要があるが、これだけでは位置精度にば
らつきが生じてコンタクト方法が複雑になる。When the wiring is formed by electrolytic plating, the characteristic inspection is performed after cutting, so that individual IC
It is necessary to inspect each package individually, which is inefficient. In order to inspect a plurality of divided IC packages at once, it is necessary to fix the plurality of IC packages 40A and 40B with tape, but this alone causes variation in positional accuracy and complicates the contact method.
【００１０】本発明は、樹脂パッケージのモールド後の
ダイシング工程で品質および生産性を向上させることの
できるＩＣパッケージの製造方法を提供することを目的
としている。An object of the present invention is to provide a method of manufacturing an IC package capable of improving quality and productivity in a dicing process after molding of a resin package.
【００１１】[0011]
【課題を解決するための手段】本発明の上記目的は、プ
リント基板の表面上に複数のＩＣチップを搭載する工程
と、前記複数のＩＣチップを共通の樹脂パッケージで封
止する工程と、前記樹脂パッケージおよび前記プリント
基板表面のパターンをダイシングブレードで切断する第
１の工程と、前記プリント基板の本体をダイシングブレ
ードで切断する第２の工程とを備えるＩＣパッケージの
製造方法で達成できる。The object of the present invention is to provide a method for mounting a plurality of IC chips on a surface of a printed circuit board, sealing the plurality of IC chips with a common resin package, This can be achieved by an IC package manufacturing method including a first step of cutting a resin package and a pattern on the surface of the printed board with a dicing blade, and a second step of cutting the main body of the printed board with a dicing blade.
【００１２】本発明の実施の形態では、前記第２の工程
は、前記第１の工程と同じ種類のダイシングブレードで
行われるか、あるいは前記第１の工程のダイシングブレ
ードとは異なる種類のダイシングブレードで行われる。
後者の場合、前記第２の工程は、例えば前記第１の工程
のダイシングブレードより幅狭の異なるダイシングブレ
ードで行われる。更に、前記第１の工程と前記第２の工
程の間に、特性検査工程を更に備えることができる。In an embodiment of the present invention, the second step is performed with a dicing blade of the same type as the first step, or a dicing blade of a different type from the dicing blade of the first step. Done in
In the latter case, the second step is performed, for example, by using a different dicing blade narrower than the dicing blade in the first step. Further, a characteristic inspection step may be further provided between the first step and the second step.
【００１３】[0013]
【発明の実施の形態】以下、図面に示した実施形態を参
照して、本発明を詳細に説明する。図１（ａ）〜（ｄ）
は、本発明の一実施形態に係るＩＣパッケージの製造方
法を示す工程図である。図１（ａ）は、プリント基板５
０の表面上に複数のＩＣチップ２０Ａ，２０Ｂを搭載す
る工程と、前記複数のＩＣチップ２０Ａ，２０Ｂを共通
の樹脂パッケージ４０で封止する工程とを経た状態を示
している。プリント基板５０の構成は、図４と同様であ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments shown in the drawings. FIG. 1 (a) to (d)
FIG. 4 is a process chart showing a method for manufacturing an IC package according to an embodiment of the present invention. FIG. 1A shows a printed circuit board 5.
2 shows a state after a step of mounting a plurality of IC chips 20A and 20B on the surface of the “0” and a step of sealing the plurality of IC chips 20A and 20B with a common resin package 40. The configuration of the printed circuit board 50 is the same as that of FIG.
【００１４】図１（ｂ）は、樹脂パッケージ４０および
プリント基板５０表面のパターン５２を第１のダイシン
グブレード６１で切断する第１の工程を示している。こ
の第１の工程では、樹脂パッケージ４０は完全に切断さ
れて、個別の樹脂パッケージ４０Ａ，４０Ｂとなる。同
時に、プリント基板５０は、その表面パターン５２だけ
が切断され、基板本体５１は連結したままの状態を保
つ。FIG. 1B shows a first step of cutting the pattern 52 on the surface of the resin package 40 and the printed board 50 with a first dicing blade 61. In the first step, the resin package 40 is completely cut into individual resin packages 40A and 40B. At the same time, only the surface pattern 52 of the printed board 50 is cut, and the board body 51 remains connected.
【００１５】この後、第１のブレード６１を引き上げる
と、図１（ｃ）に示すように、樹脂パッケージ４０Ａ，
４０Ｂ間に溝４１が残る。この状態では、基板本体５１
が連続しているので、複数のＩＣパッケージ４０Ａ，４
０Ｂを配列し直すことなく、これらに対する特性検査を
実施できる。Thereafter, when the first blade 61 is pulled up, as shown in FIG. 1C, the resin packages 40A,
The groove 41 remains between 40B. In this state, the board body 51
Are continuous, so that a plurality of IC packages 40A, 4A
Characteristic inspection can be performed on these without re-arranging the OBs.
【００１６】上記の特性検査実施後に、図１（ｄ）に示
すように、基板本体５１を第２のダイシングブレード６
２で完全に切断して、個別のＩＣパッケージ４０Ａ，４
０Ｂを分離する（第２の工程）。この第２の工程で使用
される第２のブレード６２は、第１のブレード６１と同
じ種類のものでも良いが、異なる種類の第２のブレード
６２を使用すると、ダイシング面の粗さをダイシングす
る材料に合わせて細かくすることができる。After performing the above-described characteristic inspection, as shown in FIG.
2 to completely separate the individual IC packages 40A, 40A, 4
OB is separated (second step). The second blade 62 used in the second step may be of the same type as the first blade 61, but if a different type of second blade 62 is used, dicing of the dicing surface is performed. It can be made fine according to the material.
【００１７】第２のブレード６２の種類は、ブレードの
材質だけではなく、第１のブレード６１で形成された溝
４１の幅より狭い幅を持つものとする事ができる。この
実施形態で示す第１の工程と第２の工程は、逆にするこ
ともできる。即ち、第１の工程で基板本体５１を切断
し、第２の工程で表面パターン５２と樹脂パッケージ４
０を切断する、という順序である。The type of the second blade 62 is not limited to the material of the blade, but may have a width smaller than the width of the groove 41 formed by the first blade 61. The first step and the second step shown in this embodiment can be reversed. That is, the substrate body 51 is cut in the first step, and the surface pattern 52 and the resin package 4 are cut in the second step.
0 is cut off.
【００１８】上述した本発明のＩＣパッケージ製造方法
には、次の利点がある。（１）材料毎にブレードを選定
できるので、ダイシング面の粗さを細かくすることが可
能である。（２）ブレードへの負荷が少ないため、薄い
刃の使用が可能になる。この結果、高密度実装が可能に
なるので、低コスト化を図ることができる。（３）ブレ
ードへの負荷が少ないため、ブレードの寿命が長くな
る。（４）不要な配線部を第１の工程で切断して除去す
る事により、板状でのマルチ測定が可能となり、テスト
効率が向上する。The above-described IC package manufacturing method of the present invention has the following advantages. (1) Since a blade can be selected for each material, the roughness of the dicing surface can be reduced. (2) Since the load on the blade is small, a thin blade can be used. As a result, high-density mounting becomes possible, and cost reduction can be achieved. (3) Since the load on the blade is small, the life of the blade is prolonged. (4) By cutting and removing unnecessary wiring portions in the first step, multi-measurement in a plate shape becomes possible, and test efficiency is improved.
【００１９】[0019]
【発明の効果】以上述べたように本発明によれば、樹脂
パッケージのモールド後のダイシング工程で品質および
生産性を向上させることのできるＩＣパッケージの製造
方法を実現できる。As described above, according to the present invention, it is possible to realize a method of manufacturing an IC package capable of improving quality and productivity in a dicing step after molding of a resin package.
【図１】 本発明の一実施形態に係るＩＣパッケージの
製造方法を示す工程図である。FIG. 1 is a process chart showing a method for manufacturing an IC package according to an embodiment of the present invention.
【図２】 ＣＳＰ型ＩＣパッケージの一例を示す断面図
である。FIG. 2 is a cross-sectional view illustrating an example of a CSP type IC package.
【図３】 ＢＧＡ型ＩＣパッケージの一例を示す平面図
および断面図である。FIG. 3 is a plan view and a cross-sectional view illustrating an example of a BGA type IC package.
【図４】 従来のＩＣパッケージの切断方法を示す断面
図である。FIG. 4 is a cross-sectional view showing a conventional IC package cutting method.
２０ ＩＣチップ ３０ ボンディングワイヤ ４０ 樹脂パッケージ ５０ プリント基板 ５１ 基板本体 ５２ 表面パターン ５３ 裏面パターン ５４ スルーホール ６１ 第１のダイシングブレード ６２ 第２のダイシングブレード Reference Signs List 20 IC chip 30 Bonding wire 40 Resin package 50 Printed circuit board 51 Substrate main body 52 Surface pattern 53 Back pattern 54 Through hole 61 First dicing blade 62 Second dicing blade
Claims (5)
プを搭載する工程と、 前記複数のＩＣチップを共通の樹脂パッケージで封止す
る工程と、 前記樹脂パッケージおよび前記プリント基板表面のパタ
ーンをダイシングブレードで切断する第１の工程と、 前記プリント基板の本体をダイシングブレードで切断す
る第２の工程とを備えることを特徴とするＩＣパッケー
ジの製造方法。A step of mounting a plurality of IC chips on a surface of a printed circuit board; a step of sealing the plurality of IC chips with a common resin package; and dicing the pattern of the resin package and the surface of the printed circuit board. A method for manufacturing an IC package, comprising: a first step of cutting with a blade; and a second step of cutting the main body of the printed circuit board with a dicing blade.
じ種類のダイシングブレードで行われることを特徴とす
る請求項１のＩＣパッケージの製造方法。2. The method according to claim 1, wherein the second step is performed using a dicing blade of the same type as the first step.
イシングブレードとは異なる種類のダイシングブレード
で行われることを特徴とする請求項１のＩＣパッケージ
の製造方法。3. The IC package manufacturing method according to claim 1, wherein the second step is performed by using a dicing blade of a different type from the dicing blade in the first step.
イシングブレードより幅狭の異なるダイシングブレード
で行われることを特徴とする請求項３のＩＣパッケージ
の製造方法。4. The IC package manufacturing method according to claim 3, wherein said second step is performed with a dicing blade having a width smaller than that of said dicing blade in said first step.
に、特性検査工程を更に備えることを特徴とする請求項
１〜４のいずれかのＩＣパッケージの製造方法。5. The method for manufacturing an IC package according to claim 1, further comprising a characteristic inspection step between said first step and said second step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10354040A JP2000183218A (en) | 1998-12-14 | 1998-12-14 | Manufacture of ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10354040A JP2000183218A (en) | 1998-12-14 | 1998-12-14 | Manufacture of ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000183218A true JP2000183218A (en) | 2000-06-30 |
Family
ID=18434919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10354040A Withdrawn JP2000183218A (en) | 1998-12-14 | 1998-12-14 | Manufacture of ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000183218A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003031526A (en) * | 2001-07-16 | 2003-01-31 | Mitsumi Electric Co Ltd | Module and manufacturing method thereof |
| JP2008108872A (en) * | 2006-10-25 | 2008-05-08 | Denso Corp | Mold package and its manufacturing method |
| JP2010050489A (en) * | 2001-06-07 | 2010-03-04 | Renesas Technology Corp | Semiconductor device |
| US7781089B2 (en) | 2005-05-11 | 2010-08-24 | Ricoh Company, Ltd. | Protection circuit module for a secondary battery and a battery package using same |
| JP2011512683A (en) * | 2008-02-22 | 2011-04-21 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Method of making a plurality of beam emitting components and beam emitting components |
| CN103855058A (en) * | 2012-12-03 | 2014-06-11 | 东和株式会社 | Apparatus and method for manufacturing electronic component |
| KR20160047260A (en) * | 2014-10-22 | 2016-05-02 | 삼성전자주식회사 | Method of fabricating semiconductor package |
| CN106115007A (en) * | 2016-08-30 | 2016-11-16 | 江门全合精密电子有限公司 | A kind of can the packer of surface trimming |
-
1998
- 1998-12-14 JP JP10354040A patent/JP2000183218A/en not_active Withdrawn
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010050489A (en) * | 2001-06-07 | 2010-03-04 | Renesas Technology Corp | Semiconductor device |
| JP2003031526A (en) * | 2001-07-16 | 2003-01-31 | Mitsumi Electric Co Ltd | Module and manufacturing method thereof |
| US7781089B2 (en) | 2005-05-11 | 2010-08-24 | Ricoh Company, Ltd. | Protection circuit module for a secondary battery and a battery package using same |
| JP2008108872A (en) * | 2006-10-25 | 2008-05-08 | Denso Corp | Mold package and its manufacturing method |
| US8790939B2 (en) | 2008-02-22 | 2014-07-29 | Osram Opto Semiconductors Gmbh | Method for producing a plurality of radiation-emitting components and radiation-emitting component |
| JP2011512683A (en) * | 2008-02-22 | 2011-04-21 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Method of making a plurality of beam emitting components and beam emitting components |
| KR101525638B1 (en) * | 2008-02-22 | 2015-06-03 | 오스람 옵토 세미컨덕터스 게엠베하 | Method for producing a plurality of radiation emitting components and radiation emitting component |
| JP2014108491A (en) * | 2012-12-03 | 2014-06-12 | Towa Corp | Cutting apparatus and method for manufacturing electronic component |
| CN103855058A (en) * | 2012-12-03 | 2014-06-11 | 东和株式会社 | Apparatus and method for manufacturing electronic component |
| CN103855058B (en) * | 2012-12-03 | 2016-09-07 | 东和株式会社 | Electronic components fabrication device and manufacture method |
| TWI551414B (en) * | 2012-12-03 | 2016-10-01 | Towa Corp | Electronic component manufacturing apparatus and manufacturing method thereof |
| KR20160047260A (en) * | 2014-10-22 | 2016-05-02 | 삼성전자주식회사 | Method of fabricating semiconductor package |
| US9543205B2 (en) | 2014-10-22 | 2017-01-10 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
| KR102368069B1 (en) * | 2014-10-22 | 2022-02-25 | 삼성전자주식회사 | Method of fabricating semiconductor package |
| CN106115007A (en) * | 2016-08-30 | 2016-11-16 | 江门全合精密电子有限公司 | A kind of can the packer of surface trimming |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6452255B1 (en) | Low inductance leadless package | |
| US7439097B2 (en) | Taped lead frames and methods of making and using the same in semiconductor packaging | |
| US6650020B2 (en) | Resin-sealed semiconductor device | |
| US7888179B2 (en) | Semiconductor device including a semiconductor chip which is mounted spaning a plurality of wiring boards and manufacturing method thereof | |
| JP2003124421A (en) | Lead frame, manufacturing method therefor, and manufacturing method of semiconductor device using lead frame | |
| JP2001156217A (en) | Producing method for semiconductor device | |
| JP2002076040A (en) | Semiconductor device and manufacturing method thereof | |
| KR19980028019A (en) | Printed Circuit Board Strip Structure and Manufacturing Method of Semiconductor Package Using the Same | |
| JP3837215B2 (en) | Individual semiconductor device and manufacturing method thereof | |
| US7851902B2 (en) | Resin-sealed semiconductor device, manufacturing method thereof, base material for the semiconductor device, and layered and resin-sealed semiconductor device | |
| JPH08279591A (en) | Semiconductor device and its manufacture | |
| JP2000183218A (en) | Manufacture of ic package | |
| JP2001024133A (en) | Lead frame, resin sealed semiconductor device employing it and manufacture thereof | |
| JPH10256460A (en) | Terminal land frame, resin sealed type semiconductor device using it, and manufacture of the device | |
| US6772510B1 (en) | Mapable tape apply for LOC and BOC packages | |
| JP2006245459A (en) | Manufacturing method of semiconductor device | |
| JP2003273313A (en) | Semiconductor device and manufacturing method therefor | |
| US7485493B2 (en) | Singulating surface-mountable semiconductor devices and fitting external contacts to said devices | |
| KR100290783B1 (en) | Semiconductor package | |
| JP2002026168A (en) | Semiconductor device and its manufacturing method | |
| KR0157193B1 (en) | A structure of the known good die and its fabrication method | |
| KR200148753Y1 (en) | Semiconductor package | |
| JP2003078072A (en) | Manufacturing method for semiconductor device | |
| JP2003297997A (en) | Lead frame, semiconductor device using the same, and method for manufacturing thereof | |
| JP2000236058A (en) | Semiconductor device and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050926 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060220 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060829 |
|
| A761 | Written withdrawal of application |
Free format text: JAPANESE INTERMEDIATE CODE: A761 Effective date: 20060829 |