JP4570896B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a probe measurement corresponding to a thin wafer of a power semiconductor element having electrodes on the front and back surfaces of a wafer.

  For example, in the semiconductor device manufacturing technology, the power semiconductor element probe measuring technology is disclosed in Japanese Patent Laid-Open No. 5-333988 (Patent Document 1), Japanese Patent Laid-Open No. 8-153763 (Patent Document 2), The technique etc. which are described in 7-245401 gazette (patent document 3) and Japanese Unexamined-Japanese-Patent No. 8-330372 (patent document 4) are mentioned.

  In Patent Document 1, in order to enable probing of the power semiconductor element in the wafer state, a means (compression spring) is provided for maintaining a good conductive contact state on the wafer mounting side even if the flatness of the wafer is slightly changed. A measuring device is described.

  Patent Documents 2 and 3 describe a method for inspecting a power semiconductor element having electrodes on the front and back surfaces in a wafer state.

Patent Document 4 describes an inspection method in which the back surface of a wafer is fixed to a dicing sheet, and in this state, probe terminals are probed on the front electrode.
JP-A-5-333098 Japanese Patent Laid-Open No. 8-153763 JP 7-245401 A JP-A-8-330372

  By the way, as a result of examination by the present inventor regarding the probe measurement technique of the power semiconductor element in the semiconductor device manufacturing technique, the following has been clarified.

  For example, in recent years, power semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and vertical power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) have been reduced in thickness to improve characteristics and support small packages. In such a power semiconductor device having a reduced thickness, since the wafer is thin, it is difficult to perform probing by a handling method.

  In addition, in a semiconductor device with a thin wafer, a method of inspecting with a dicing tape attached to the back surface of the wafer may be considered. However, since the power semiconductor device has electrodes on the back surface as well as the front surface, Probe measurement with a dicing tape attached to the back surface is impossible.

  Therefore, in a power semiconductor element having electrodes on the front and back surfaces of the wafer, a method applicable to probe measurement corresponding to the thinning of the power semiconductor element is required, and a technique for realizing it is desired.

  An object of the present invention is to provide a measurement technique capable of easily realizing probe measurement corresponding to thinning of a power semiconductor element having electrodes on the front surface and the back surface of a wafer in the manufacturing technology of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is applied to a method for manufacturing a semiconductor device, and includes a step of forming an integrated circuit on a wafer, a step of attaching a measurement holding member having an opening on the surface of the wafer, and measuring an electrical characteristic of the integrated circuit, a wafer Including a step of peeling the measurement holding member affixed to the front surface of the wafer, affixing a cutting holding member to the back surface of the wafer and cutting it into individual integrated circuit chips, and a step of assembling the semiconductor device by storing the integrated circuit chips. It is a waste.

  Specifically, the integrated circuit has electrodes on the front surface and the back surface of the wafer, and the electrical characteristics of the integrated circuit are determined by the electrode on the front surface of the wafer through the opening of the holding member for measurement, the electrode on the back surface of the wafer, It is to be measured by connecting it electrically. The wafer has a thickness of 120 μm or less, 100 μm or less, 70 μm or less, or 60 μm or less. The integrated circuit is applied to a circuit that generates a lot of heat.

  The measurement holding member has an opening having a size smaller than the outer dimension of the wafer and has a structure in which the opening can be peeled off. After the measurement holding member is attached to the surface of the wafer, the opening The first holding member having an opening smaller than the outer dimension of the wafer and the second holding adhered to the first holding member It consists of a double structure with the member, and after the measurement holding member is attached to the surface of the wafer, the second holding member is peeled off to measure the electrical characteristics of the integrated circuit.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  It becomes possible to easily realize the probe measurement corresponding to the thinning of the power semiconductor element having electrodes on the front surface and the back surface of the wafer.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently indispensable in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape and positional relationship of components and the like, the shape is substantially the same unless otherwise specified and the case where it is not clearly apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
First, an example of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 is a diagram showing the top surface of the IGBT, FIG. 2 is a diagram showing the bottom surface of the IGBT, FIG. 3 is a diagram showing the vertical structure (trench type) of the IGBT, and FIG. 4 is a vertical structure (planar type) of the IGBT. FIG. 5 is a diagram showing a vertical structure (trench type) of a power MOSFET, FIG. 6 is a diagram showing a structure of a semiconductor device in which an IGBT and a power MOSFET are packaged, and FIG. 7 is a diagram showing an arrangement of the semiconductor device before molding. , Is.

  The semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment is applied to, for example, an IGBT as shown in FIGS. 1 to 4 and a power MOSFET as shown in FIG. 5, and each structure will be described below. .

  As shown in FIG. 1, the IGBT has a gate electrode (G) 1 and an emitter electrode (E) 2 provided on the upper surface of the chip, and a collector electrode (C) 3 provided on the lower surface of the chip as shown in FIG. It has been. The IGBT structure includes a trench type and a planar type.

As shown in FIG. 3, the trench type IGBT has a vertical structure in which an insulating film 13, a gate wiring layer 14, an insulating layer are formed on the surface of a wafer having a laminated structure of a base (p) 11 and an epitaxial layer (n ⁻ ) 12. The film 15, the emitter electrode 2 and the gate electrode 1 (not shown) are laminated in order, and the emitter electrode 2 and the gate electrode 1 are exposed on the upper surface as shown in FIG. A gate 16 is buried in the depth direction by a trench technique in the layered structure portion of the base (p) 11 and the epitaxial layer (n ⁻ ) 12, and the periphery of the gate 16 is covered with a gate oxide film 17. . Further, a well region (n ⁺ ) 18 is formed between the gates 16 on the surface layer of the wafer. On the other hand, an n ⁺ layer 19, a p ⁺ layer 20, and a collector electrode 3 are sequentially laminated on the back surface of the wafer having a laminated structure of the base (p) 11 and the epitaxial layer (n ⁻ ) 12, as shown in FIG. The collector electrode 3 is exposed on the lower surface.

As shown in FIG. 4, a planar IGBT has a vertical structure in which a gate oxide film 32, a gate 33, a wiring layer 34, an emitter electrode 2 and a gate (not shown) are formed on the surface of a wafer made of an epitaxial layer (n ⁻ ) 31. The electrodes 1 are sequentially stacked, and the emitter electrode 2 and the gate electrode 1 are exposed on the upper surface as shown in FIG. A well region (p) 35 and a well region (n ⁺ ) 36 are formed in the well region (p) 35 on the surface layer of the wafer. On the other hand, an n ⁺ layer 37, a p ⁺ layer 38, and a collector electrode 3 are sequentially laminated on the back surface of the wafer made of the epitaxial layer (n ⁻ ) 31, and the collector electrode 3 is exposed on the lower surface as shown in FIG. Yes.

The power MOSFET is provided with a gate electrode (G) 1a and a source electrode (S) (instead of the emitter electrode) 2a on the upper surface of the chip, and a drain electrode on the lower surface of the chip, as with the IGBT (FIGS. 1 and 2). (D) 3a (in place of the collector electrode) is provided. The structure of this power MOSFET also includes a trench type and a planar type. For example, the vertical structure of the trench type power MOSFET has no p ⁺ layer on the back surface of the wafer as shown in FIG. A drain electrode is stacked on the n ⁺ layer. That is, the power MOSFET includes a base (p) 41, an epitaxial layer (n ⁻ ) 42, an insulating film 43, a gate wiring layer 44, an insulating film 45, a gate 46, a gate oxide film 47, a well region (n ⁺ ) 48, An n ⁺ layer 49 is provided. The vertical structure of the planar power MOSFET is the same except that there is no p ⁺ layer on the back surface of the wafer.

  A semiconductor device in which an IGBT or power MOSFET chip having such a structure is packaged is manufactured, for example, in a structure as shown in FIG. 6 and arranged as shown in FIG. 7 and commercialized as a multi-chip IC.

  In this multi-chip IC example, two power semiconductor element chips 51 and 52 such as IGBT and power MOSFET and one control chip 53 are mounted on the same lead frame 54, and the power semiconductor element chips 51 and 52 are mounted. The electrodes on 52, the electrodes on the control chip 53, and the pads on the lead frame 54 are connected by wires 55 and molded by a resin 56. In the molded multichip IC, a portion serving as an external terminal of the lead frame 54 is exposed on the back surface, and the back surface portion of the lead frame 54 on which the power semiconductor element chips 51 and 52 and the control chip 53 are mounted is also provided. Exposed to enhance heat dissipation effect.

  Next, an example of a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 8 to FIG. 11 are diagrams showing each process and process flow from device formation to selection, and FIG. 12 is a diagram specifically showing the wafer test process.

The method for manufacturing a semiconductor device according to the present embodiment is applied to, for example, a method for manufacturing a power semiconductor element of a trench type IGBT shown in FIG. 3, and is manufactured by the following procedure. The same applies to the planar IGBT shown in FIG. 4, and the manufacturing of the power semiconductor device of the power MOSFET shown in FIG. 5 is the same as that of the IGBT except that the p ⁺ layer is not formed on the back surface of the wafer. is there.

(1) Device formation / wiring / passivation process In this process, the wafer 61 is subjected to various types of wafer processing to form IGBT power semiconductor elements, which are integrated circuits, and further, wiring for electrically connecting common terminals and the like is formed. Thereafter, a passivation film is formed on the surface except for the electrically exposed portion. After completion of this step, the gate electrode 1, emitter electrode 2, base 11, epitaxial layer 12, insulating film 13, gate wiring layer 14, insulating film 15, gate 16, gate oxide film 17, well shown in FIG. Region 18 is formed.

(2) Reinforcing Material (Tape / Rigid Body) Application Step In this step, a high-rigidity tape 62 for preventing warpage of the wafer 61 is attached to the surface of the wafer 61.

(3) Back-grinding (BG) protective tape or reinforcing material affixing process In this process, a heat-foaming tape for removing grinding powder in the next back-grinding process on the surface of the high-rigidity tape 62 affixed to the wafer 61 63 is pasted.

(4) Back surface grinding process In this process, the back surface of the wafer 61 is ground until it reaches a predetermined thickness. For example, as an example, the thickness of the wafer 61 is ground to a predetermined thickness in order to improve characteristics and accommodate a small package, such as 120 μm or less, 100 μm or less, 70 μm or less, or 60 μm or less.

(5) Tape or reinforcing material peeling step In this step, the thermal foam tape 63 attached to the surface of the high-rigidity tape 62 on the wafer 61 is peeled off.

(6) Spin Etching Step In this step, the unevenness on the back surface of the wafer 61 is spin etched using a chemical abrasive or the like to flatten the back surface of the wafer 61.

(7) Backside Implant (1) and (2) Steps In this step, phosphorus (P ⁺ ) and boron (B ⁺ ) ions are implanted from the back side of the wafer 61 to form the N ⁺ layer 19 and the P ⁺ layer 20. To do.

(8) Step of peeling reinforcing material (tape / rigid body) In this step, the high-rigidity tape 62 attached to the surface of the wafer 61 is peeled off.

(9) Surface Cleaning Process In this process, the surface of the wafer 61 is cleaned.

(10) Implant annealing step In this step, the N ⁺ layer 19 and the P ⁺ layer 20 formed on the back surface of the wafer 61 are heat-treated.

(11) Film formation pretreatment step In this step, pretreatment for forming a metal film is performed in the next backside metal film formation step.

(12) Back surface metal film forming step In this step, a metal film to be the collector electrode 3 is formed on the back surface of the wafer 61. For example, as an example, the metal film is made of a material such as nickel (Ni) / titanium (Ti) / nickel (Ni) / gold (Au).

(13) Alloy Process In this process, the collector film 3 is formed by heat-treating the metal film formed on the back surface of the wafer 61.

(14) Wafer Surface Tape Affixing / Dicing Frame Affixing Step In this step, a tape 64 as a measurement holding member having an opening is affixed to the surface of the wafer 61, and a dicing frame 65 is affixed to the tape 64. . For example, the tape 64 includes a UV irradiation release sheet or a heat release sheet made of a material such as polyvinyl chloride. The details of this process are as shown in FIGS. 13 and 14 described later.

(15) Wafer Test Process In this process, the back surface of the wafer 61 is mounted on a probing stage 66 having a back surface measurement terminal, the collector electrode 3 on the back surface is electrically connected, and the front surface of the wafer 61 is opened through the opening of the tape 64. The surface measurement terminals 67 and 68 are electrically connected to the gate electrode 1 and the emitter electrode 2 to measure the electrical characteristics of the IGBT power semiconductor element. For example, the measurement of electrical characteristics includes measurement of withstand voltage, leak current, Gm, on-resistance, and the like.

  Specifically, as shown in FIG. 12, a tape 64 having an opening is attached to the front surface of the wafer 61, a dicing frame 65 having an opening is attached to the back surface of the tape 64, and the wafer 61 In the state where the back surface is mounted on the probing stage 66, the electrical characteristics are measured. At the time of measuring the electrical characteristics, only the invalid area of the outer peripheral portion of the surface of the wafer 61 is attached to the tape 64, and the gate electrode 1 and the emitter electrode 2 formed on the surface are exposed. In addition, the entire rear surface of the wafer 61 on which the collector electrode 3 is formed is exposed and mounted on the probing stage 66.

  The measuring device used for this measurement includes a constant current source 76 for forcing, a constant voltage source 77 for gate signal, and a voltmeter 78, and the constant current source 76 is for contacting the collector electrode 3. An emitter forcing pin 68a for probing with the probing stage (forcing: F) 66 and the emitter electrode 2, and a probing stage (sensing: S) 66 for contacting the collector electrode 3 with the voltmeter 78 and the emitter sensing pin 68b are electrically connected to each other.

  On the other hand, since a constant voltage signal is applied to the gate as the emitter reference potential to the constant voltage source 77 for the gate signal, the negative electrode of the constant voltage source 77 is the forcing line (68a) and the sensing line (68b) of the emitter electrode 2. The positive electrode is electrically connected to the gate forcing pin 67a and the gate sensing pin 67b for probing the gate electrode 1.

  In measurement, the wafer 61 is set on a probing stage (forcing / sensing) 66 and brought into contact with the collector electrode 3, the emitter forcing pin 68 a and the emitter sensing pin 68 b are connected to the emitter electrode 2, and the gate is connected to the gate electrode 1. The forcing pin 67a and the gate sensing pin 67b are brought into contact with each other. Thereby, each measuring pin and each electrode of the wafer 61 are electrically connected.

  For example, when measuring the on-resistance, a constant voltage source 77 for the gate signal of the measuring device supplies a voltage sufficient to turn on the power semiconductor element of the IGBT through the gate forcing pin 67a and the gate sensing pin 67b. A large current is supplied by a constant current source 76 for forcing between the collector electrode 3 and the emitter electrode 2 through a probing stage (forcing) 66 and an emitter forcing pin 68a, and an on-voltage is measured by a voltmeter 78. Thus, the on-resistance can be obtained from the relationship between the voltage and the current.

(16) Surface Tape Peeling Step In this step, UV is irradiated from the surface of the wafer 61 and the tape 64 attached to the surface of the wafer 61 is peeled off.

(17) Dicing Tape Affixing Step In this step, a dicing tape 69 that is a cutting holding member is affixed to the back surface of the wafer 61. For example, the dicing tape 69 includes a UV irradiation release sheet or a heat release sheet made of a material such as polyvinyl chloride.

(18) Dicing Step In this step, the dicing tape 69 is attached to the back surface of the wafer 61 and the wafer 61 is cut into chips of individual IGBT power semiconductor elements with the grindstone 70. The cutting method is not limited to the grindstone 70, and other methods such as a laser are also possible.

(19) Assembly process In this process, a chip which is a semiconductor device is assembled by housing a chip of an IGBT power semiconductor element. In this step, for example, as shown in FIGS. 6 and 7, two power semiconductor element chips 51 and 52 and one control chip 53 are mounted on the same lead frame 54, and the power semiconductor element chip is mounted. The electrodes on 51 and 52, the electrodes on the control chip 53, and the pads on the lead frame 54 are connected by wires 55, and then molded by a resin 56 to complete a multi-chip IC having a package structure.

(20) Sorting Step In this step, the assembled semiconductor device having the package structure is tested, and a non-defective semiconductor device is shipped as a product.

  In the semiconductor device manufacturing method described above, the wire bonding in which the electrodes on the chips 51, 52, 53 and the pads on the lead frame 54 are connected by the wires 55 has been described as an example. It is also possible to form a package structure that is formed on a bump and is flip-chip bonded onto a lead frame.

  Next, based on FIGS. 13 to 16, in the method for manufacturing a semiconductor device according to the first embodiment of the present invention, the above-described (14) wafer surface tape attaching / dicing frame attaching step will be described in detail. FIG. 13 and FIG. 14 are diagrams showing each process and processing flow from wafer set to wafer frame removal, FIG. 15 is a diagram showing a tape ((a) is a plan view before a peeling part is peeled off, (B) is a plan view in a state after peeling), FIG. 15 is a view showing another tape ((a) is a plan view, (b) is a sectional view).

(141) Wafer Setting Step In this step, the wafer 61 is put in the holder 71 and the wafer 61 is sucked by the vacuum 72 through the through hole provided in the holder 71. Then, the dicing frame 65 is set on the holder 71.

(142) Tape Affixing Step In this step, the tape 64 is affixed to the surface of the wafer 61. For example, as shown in FIG. 14A, the tape 64 has a plurality of peeling portions 64a which are peelable openings smaller than the outer dimensions of the wafer 61 in order to make the tape 64 easier to handle. The one connected in 64b is used.

(143) UV irradiation step In this step, the mask 73 is mounted on a portion other than the portion 64a where the tape 64 is peeled off in the next tape peeling step, and the portion 64a where the tape 64 attached to the surface of the wafer 61 is peeled is irradiated with UV. To do.

(144) Tape peeling process In this process, the part 64a to be peeled off of the tape 64 is cut off by the connecting part 64b, and the part 64a to be peeled off from the surface of the wafer 61 is peeled off. FIG. 14B shows a state where the peeled portion 64a is peeled off, and the tape 64 has a structure having an opening.

(145) Wafer / Frame Extraction Step In this step, the vacuum 72 is cut and the wafer 61 attached with the tape 64 together with the dicing frame 65 is taken out. As a result, a tape 64 having an opening is attached to the surface of the wafer 61, and a dicing frame 65 having an opening is attached to the back surface of the tape 64.

  In the wafer surface tape adhering / dicing frame adhering process described above, the tape 64 in a state where the peeled portion 64a as the opening is connected by the connecting portion 64b as shown in FIGS. 15 (a) and 15 (b) is used. In addition, as shown in FIGS. 16A and 16B, for example, a tape 81 which is a holding member having an opening 81a having a size smaller than the outer dimension of the wafer 61, and the tape 81 It is also possible to use one having a double structure with a tape 82 which is a holding member adhered on the top.

  When the tapes 81 and 82 having the double structure are used, after the tapes 81 and 82 having the double structure are attached to the surface of the wafer 61, only the surface tape 82 is peeled off by UV irradiation, for example. By keeping the tape 81 having the opening attached, the tape 81 having the opening is attached to the front surface of the wafer 61 in the same manner as the tape 64 in FIG. The dicing frame 65 having the above can be attached.

  Therefore, according to the present embodiment, in a power semiconductor element such as an IGBT or a power MOSFET, the power semiconductor element is formed on the wafer 61, and the tape 64 having an opening is attached to the surface of the wafer 61. The electrical characteristics are measured by electrically connecting to the electrode on the front surface of the wafer 61 and the electrode on the back surface of the wafer 61 through the opening of the tape 64, and the tape 64 attached to the surface of the wafer 61 is peeled off. Then, a dicing tape 69 is attached to the back surface of the wafer 61 and cut into individual power semiconductor element chips, and a semiconductor device having a package structure is assembled, so that the power semiconductor element having electrodes on the front and back surfaces of the wafer 61 is thinned. It is possible to easily realize probe measurement compatible with wafer fabrication.

  In addition, since the back surface of the wafer 61 is mounted on the probing stage 66 and the back surface of the wafer 61 can be brought into close contact with the probing stage 66, it is possible to dissipate an integrated circuit that generates a large amount of heat, such as a power semiconductor element. Can be implemented.

(Embodiment 2)
Based on FIG. 17, an example of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described. FIG. 17 is a diagram showing a vertical structure of a small signal transistor.

  The semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present embodiment is different from the power semiconductor element of the IGBT and power MOSFET of the first embodiment, for example, in the semiconductor element of a small signal transistor as shown in FIG. Applied and its structure is described below.

As shown in FIG. 17, the vertical structure of the small signal transistor includes a well region (p) 92 and a well region (p) 92 formed on the surface layer of the substrate (n ⁻ ) 91 of the wafer 61a. A well region (n ⁺ ) 93 is formed therein. A base electrode (B) 94 and an emitter electrode (E) 95 are exposed on the surface of the wafer 61a, while the back surface of the wafer 61a is exposed as a collector electrode (C).

  Next, an example of a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 18 and FIG. 19 are diagrams showing each process and process flow from device formation to alloy, respectively.

  The manufacturing method of the semiconductor device according to the present embodiment is applied to the manufacturing method of the semiconductor element of the small signal transistor shown in FIG. 17, and is manufactured by the following procedure. In FIG. 18 and FIG. And the steps correspond to those of the first embodiment, but the portion where the processing flow is blank is a step where there is no processing.

  That is, in the method of manufacturing a semiconductor element of a small signal transistor, (1) after forming a small signal transistor as an integrated circuit on the wafer 61a in the device formation / wiring / passivation process, (2) a reinforcing material (tape / rigid body) The pasting process was carried out in the same manner. (3) There was no sticking of the thermal foam tape in the back grinding (BG) protective tape or reinforcing material pasting process, and (4) only the high rigidity tape 62 was pasted in the back grinding process. In this state, the back surface of the wafer 61a is ground, (5) the high-rigidity tape 62 is removed in the tape or reinforcing material peeling process, and (6) the spin etch process is performed in the same manner. From step 2) to step (9), there is no treatment of the surface cleaning step, and thereafter (10) the implantation annealing step to (13) the alloying step are carried out in the same manner.

  The subsequent (14) wafer surface tape attaching / dicing frame attaching step to (20) sorting step are the same as those in the first embodiment.

  Therefore, according to the present embodiment, in the manufacture of the semiconductor device of the small signal transistor, the probe measurement corresponding to the thin wafer of the semiconductor device of the small signal transistor can be easily realized as in the first embodiment. Can do.

(Embodiment 3)
An example of a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. FIG. 20 and FIG. 21 are diagrams showing each process and process flow from device formation to alloy, respectively.

  The manufacturing method of the semiconductor device according to the present embodiment is applied to the same power semiconductor element of the IGBT (power MOSFET) as that of the first embodiment, particularly with a wafer thickness of 50 μm or less. Manufactured. 20 and FIG. And the steps correspond to those of the first embodiment, but the portion where the processing flow is blank is a step where there is no processing.

  That is, in the method for manufacturing an IGBT power semiconductor element having a wafer thickness of 50 μm or less, (1) after forming an IGBT as an integrated circuit on the wafer 61b in the device formation / wiring / passivation step, (2) a reinforcing material (Tape / rigid body) Affixed with heat-foaming double-sided tape pressure sensitive adhesive 62a in the affixing process, (3) Abrasion material 63a such as glass or ceramic is affixed in the back grinding (BG) protective tape or reinforcing material affixing process (4) Back grinding process is performed in the same manner, (5) No tape or reinforcing material peeling process is performed, (6) From spin etch process to (7) Back implant (1), (2) process After performing (8) the reinforcing material (tape / rigid body) peeling process, the reinforcing material 63a and the heat-foaming double-sided tape pressure sensitive adhesive 62a are peeled off. (9) From the surface cleaning process (13 Up alloy process carried out analogously.

  The subsequent (14) wafer surface tape attaching / dicing frame attaching step to (20) sorting step are the same as those in the first embodiment.

  Therefore, according to the present embodiment, even in the manufacture of an IGBT (power MOSFET) power semiconductor element having a thickness of the wafer 61b of 50 μm or less, as in the first embodiment, the power semiconductor element can be made thinner. The probe measurement can be easily realized, and the power semiconductor element that generates a large amount of heat can be dissipated, so that a high power test can be performed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The method of manufacturing a semiconductor device according to the present invention is applied to a power semiconductor element such as an IGBT or a power MOSFET, or a semiconductor device in which an integrated circuit generating a large amount of heat is formed, and in particular, a power semiconductor element having electrodes on the front and back surfaces of a wafer. It is effective when applied to probe measurement for thin wafers.

In the semiconductor device manufactured by the manufacturing method of the semiconductor device concerning Embodiment 1 of the present invention, it is a figure showing the upper surface of IGBT. In the semiconductor device manufactured by the manufacturing method of the semiconductor device concerning Embodiment 1 of the present invention, it is a figure showing the undersurface of IGBT. In the semiconductor device manufactured by the manufacturing method of the semiconductor device concerning Embodiment 1 of the present invention, it is a figure showing the vertical structure (trench type) of IGBT. In the semiconductor device manufactured by the manufacturing method of the semiconductor device concerning Embodiment 1 of the present invention, it is a figure showing the vertical structure (planar type) of IGBT. In the semiconductor device manufactured by the manufacturing method of the semiconductor device concerning Embodiment 1 of the present invention, it is a figure showing the vertical structure (trench type) of power MOSFET. In the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention, it is a figure which shows the structure of the semiconductor device which packaged IGBT and power MOSFET. In the semiconductor device manufactured by the manufacturing method of the semiconductor device concerning Embodiment 1 of the present invention, it is a figure showing arrangement of a semiconductor device before mold. In the manufacturing method of the semiconductor device concerning Embodiment 1 of the present invention, it is a figure showing each process and process flow from device formation to spin etching. FIG. 9 is a diagram showing each process and processing flow from the back surface implanter to the alloy, following FIG. 8, in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 10 is a diagram illustrating each process and process flow from wafer surface tape sticking to surface tape peeling, following FIG. 9, in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIG. 11 is a diagram showing each process and process flow from dicing tape attachment to sorting in the method for manufacturing a semiconductor device according to the first embodiment of the present invention, following FIG. 10. In the manufacturing method of the semiconductor device concerning Embodiment 1 of the present invention, it is a figure showing a wafer test process concretely. It is a figure which shows each process and process flow from a wafer set to UV irradiation in the wafer surface tape sticking and dicing frame sticking process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. In the wafer surface tape attaching / dicing frame attaching step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention, each process from the tape peeling to the wafer / frame taking out and the processing flow are shown in FIG. FIG. (A), (b) is a figure which shows a tape in the wafer surface tape sticking and dicing frame sticking process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. (A), (b) is a figure which shows another tape in the wafer surface tape sticking and dicing frame sticking process of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is a figure which shows the vertical structure of a small signal transistor in the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. In the manufacturing method of the semiconductor device concerning Embodiment 2 of the present invention, it is a figure showing each process and process flow from device formation to spin etching. FIG. 19 is a diagram illustrating each process and processing flow from the back surface implantation to the alloy, following FIG. 18, in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. It is a figure which shows each process and process flow from device formation to spin etching in the manufacturing method of the semiconductor device concerning Embodiment 3 of this invention. FIG. 21 is a diagram illustrating each process and processing flow from the back surface implantation to the alloy, following FIG. 20, in the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

Explanation of symbols

1, 1a gate electrode 2 emitter electrode 2a source electrode 3 collector electrode 3a drain electrode 11 base 12 epitaxial layer 13 insulating film 14 gate wiring layer 15 insulating film 16 gate 17 gate oxide film 18 well region 19 n ⁺ layer 20 p ⁺ layer 31 Epitaxial layer 32 Gate oxide film 33 Gate 34 Wiring layer 35 Well region 36 Well region 37 n ⁺ layer 38 p ⁺ layer 41 Base 42 Epitaxial layer 43 Insulating film 44 Gate wiring layer 45 Insulating film 46 Gate 47 Gate oxide film 48 Well region 49 n ⁺ layers 51, 52 Power semiconductor element chip 53 Control chip 54 Lead frame 55 Wire 56 Resin 61, 61a, 61b Wafer 62 High rigidity tape 62a Thermal foam double-sided tape pressure sensitive adhesive 63 Thermal foam tape 63a Reinforcing material 64 Tape 64a part to peel off Minute 64b Connection portion 65 Dicing frame 66 Probing stage 67, 68 Surface measurement terminal 67a Gate forcing pin 67b Gate sensing pin 68a Emitter forcing pin 68b Emitter sensing pin 69 Dicing tape 70 Grinding wheel 71 Holder 72 Vacuum 73 Mask 76 Constant current source 77 constant voltage source 78 voltmeter 81 tape 81a opening 82 tape 91 substrate 92 well region 93 well region 94 base electrode 95 emitter electrode

Claims (13)

(A) forming a plurality of semiconductor elements on the wafer;
(B) attaching a first holding member to the surface of the wafer;
(C) measuring the electrical characteristics of the semiconductor element;
(D) peeling the first holding member attached to the front surface of the wafer, attaching a second holding member to the back surface of the wafer, and cutting into individual semiconductor chips;
(E) housing the semiconductor chip and assembling a semiconductor device,
The first holding member used in the step (b) has a first opening,
The step (b) is pasted so that the first electrode and the second electrode provided on the surface of the wafer are exposed from the first opening of the first holding member,
In the step (c), the first measurement terminal and the second measurement terminal are electrically connected to the first electrode and the second electrode through the first opening of the first holding member, respectively, A method of manufacturing a semiconductor device, wherein the third measurement terminal is electrically connected to a third electrode provided on the back surface of the wafer . The method of manufacturing a semiconductor device according to claim 1, wherein a dimension of the first opening is smaller than an outer dimension of the wafer . 3. The method of manufacturing a semiconductor device according to claim 2, wherein, in the step (b), the first holding member is attached only to an invalid area on an outer peripheral portion of the surface of the wafer . 2. The frame having a second opening is attached to the side of the first holding member on which the wafer is attached so that the wafer is positioned in the second opening. The manufacturing method of the semiconductor device as described in 2. above . The third electrode of the wafer is a back surface of the wafer;
Furthermore, the third measurement terminal is a probing stage,
The step (c) includes a step of mounting the wafer on the probing stage so that the back surface of the wafer faces the probing stage, and the entire back surface of the wafer is in contact with the probing stage. The method for manufacturing a semiconductor device according to claim 1, wherein electrical characteristics of the semiconductor element are measured . The semiconductor device according to claim 1, wherein the semiconductor element is a power MOSFET, the first electrode is a gate electrode, the second electrode is a source electrode, and the third electrode is a drain electrode. Method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor element is an IGBT, the first electrode is a gate electrode, the second electrode is an emitter electrode, and the third electrode is a collector electrode. . The method of manufacturing a semiconductor device according to claim 1, wherein the measurement of the electrical characteristics of the semiconductor element is measurement of on-resistance. The method for manufacturing a semiconductor device according to claim 1, wherein the measurement of the electrical characteristics of the semiconductor element includes any one of on-resistance, breakdown voltage, leakage current, and Gm. The method for manufacturing a semiconductor device according to claim 1, wherein the first measurement terminal includes a forcing pin and a sensing pin. The method of manufacturing a semiconductor device according to claim 10, wherein the second measurement terminal includes a forcing pin and a sensing pin. The method of manufacturing a semiconductor device according to claim 1, wherein the wafer has a thickness of 120 μm or less. (A) forming a plurality of semiconductor elements on the wafer;
(B) a step of attaching a measurement holding member to the surface of the wafer;
(C) measuring the electrical characteristics of the semiconductor element;
(D) peeling off the measurement holding member attached to the front surface of the wafer, attaching the cutting holding member to the back surface of the wafer, and cutting into individual semiconductor chips;
(E) housing the semiconductor chip and assembling a semiconductor device,
The measurement holding member used in the step (b) has an opening,
In the step (b), the surface electrode provided on the surface of the wafer is attached so as to be exposed from the opening of the measurement holding member.
In the step (c), the front surface measurement terminal is electrically connected to the front surface electrode through the opening of the measurement holding member, and the back surface measurement terminal is connected to the back surface electrode provided on the back surface of the wafer. A method for manufacturing a semiconductor device, which is performed by electrical connection.

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