JP2008270270A - Process for manufacturing semiconductor device - Google Patents

Process for manufacturing semiconductor device Download PDF

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Publication number
JP2008270270A
JP2008270270A JP2007107256A JP2007107256A JP2008270270A JP 2008270270 A JP2008270270 A JP 2008270270A JP 2007107256 A JP2007107256 A JP 2007107256A JP 2007107256 A JP2007107256 A JP 2007107256A JP 2008270270 A JP2008270270 A JP 2008270270A
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Japan
Prior art keywords
capillary
wire
bonding
semiconductor device
lead
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JP2007107256A
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Japanese (ja)
Inventor
Tominori Takahashi
富視 高橋
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Renesas Technology Corp
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Renesas Technology Corp
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2007107256A priority Critical patent/JP2008270270A/en
Publication of JP2008270270A publication Critical patent/JP2008270270A/en
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the yield and quality of product by preventing poor bonding such as peeling of wire, and to enhance work efficiency while reducing the manufacturing cost of semiconductor device. <P>SOLUTION: When wire bonding reaches predetermined conditions in wire bonding process, dirt adhered to a capillary 20 can be transferred to a capillary cleaning tool 36 by performing dummy bonding above the capillary cleaning tool 36 provided on a heat stage 30 by using the capillary 20. Reliable wire bonding is achieved by cleaning dirt of the capillary 20 automatically, and the labor of a worker for replacing the capillary 20 manually is lessened by decreasing the number of times the capillary 20 is replaced. Consequently, the yield and quality of product are enhanced by preventing poor bonding such as peeling of wire, and the work efficiency can be enhanced while reducing the manufacturing cost of semiconductor device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置の製造技術に関し、特に、キャピラリを用いて半導体チップとリードとをワイヤで接続する半導体装置の製造技術に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a semiconductor device manufacturing technique in which a semiconductor chip and a lead are connected by a wire using a capillary.

キャピラリを用いてボンデイングするワイヤボンデイング装置において、キャピラリの先端へのＳＭＤ実装工程での汚れの偏った付着及び不均等な磨耗を低減し、ボンデイングの信頼性とキャピラリの耐用ボンデイング回数を向上させるために、清掃パットを予め設け、予め定めたボンデイング回数毎に、キャピラリを清掃パットの上方に移動させて先端表面への汚れを清掃する技術がある（例えば、特許文献１参照）。
特開２０００−２３２１２５号公報（図５） In a wire bonding apparatus for bonding using a capillary, in order to reduce uneven adhesion and uneven wear in the SMD mounting process on the tip of the capillary, and to improve the bonding reliability and the number of durable bonding of the capillary There is a technique in which a cleaning pad is provided in advance and the capillary is moved above the cleaning pad for every predetermined number of bondings to clean dirt on the tip surface (for example, see Patent Document 1).
Japanese Unexamined Patent Publication No. 2000-232125 (FIG. 5)

以下に説明する技術は、本発明を研究、完成するのに際して、本発明者によって検討されたものであり、その概要は次のとおりである。   The technology described below has been studied by the present inventors in researching and completing the present invention, and the outline thereof is as follows.

半導体装置の製造におけるワイヤボンディング工程では、半導体チップの電極と、リードフレームのリード又はベース基板の配線リード（電極）とを、ボンディングツールであるキャピラリから出される金線等で接続するワイヤボンディングが行われる。   In the wire bonding process in the manufacture of a semiconductor device, wire bonding is performed by connecting a lead of a semiconductor chip and a lead of a lead frame or a wiring lead (electrode) of a base substrate with a gold wire or the like emitted from a capillary as a bonding tool. Is called.

このワイヤボンディングでは、最初に一方にワイヤを接続するファーストボンディングと、ファーストボンディングの後で他方にワイヤを接続するセカンドボンディングがある。例えば、ファーストボンディングとして行う半導体チップとワイヤとの接続は、キャピラリ先端から少し出ているワイヤを、トーチにより溶融してボールを形成し、このボールを超音波を用いながら半導体チップの電極に圧着するボールボンディングにより行う。   This wire bonding includes first bonding in which a wire is first connected to one side and second bonding in which a wire is connected to the other after the first bonding. For example, the connection between the semiconductor chip and the wire, which is performed as first bonding, is performed by melting a wire slightly protruding from the tip of the capillary with a torch to form a ball, and crimping the ball to the electrode of the semiconductor chip using ultrasonic waves. Performed by ball bonding.

また、セカンドボンディングとして行うリードフレーム（又はベース基板）とワイヤとの接続は、ファーストボンディングでボールボンディングを行った後、引き続きキャピラリからワイヤを引き出しながらワイヤループを作り、リードフレーム（又はベース基板）側においてキャピラリの周囲でワイヤを潰すようにして圧着するステッチボンディングにより行う。   In addition, the lead frame (or base substrate) and the wire connected as the second bonding are connected to the lead frame (or base substrate) side by making a wire loop while continuously drawing the wire from the capillary after performing the ball bonding with the first bonding. In this step, stitch bonding is performed in which the wire is crushed and crimped around the capillary.

ところで、このようなワイヤボンディングにおいて、半導体チップやリードフレーム等のボンディング対象物の本体、メッキ、ソルダレジスト等の影響により、キャピラリの先端には、金（Ａｕ）、銀（Ａｇ）、シリコン（Ｓｉ）、ソルダレジスト（ＳＲ）等の異物が汚れとして溜まっていく。そして、異物が溜まった結果、キャピラリの先端形状が大きく変化した場合には、正常なワイヤボンディングを行うことができず、ワイヤ剥がれ等のボンディング不良の発生要因となる。   By the way, in such wire bonding, the tip of the capillary has gold (Au), silver (Ag), silicon (Si) due to the influence of the main body of a bonding object such as a semiconductor chip and a lead frame, plating, solder resist, and the like. ), Foreign matters such as solder resist (SR) accumulate as dirt. If the tip shape of the capillary changes greatly as a result of the accumulation of foreign matter, normal wire bonding cannot be performed, which causes a bonding failure such as wire peeling.

ここで、先端に異物が溜まったキャピラリを新しいものと交換したり、一旦取り外して薬液等につけて清掃したりすると、コストが掛かる他、キャピラリの取り外しや交換、取り付けによりボンディング条件が変わってしまい、その調整に多大な作業を必要とし、生産効率が落ちるという問題が生じる。   Here, if a capillary with foreign matter accumulated at the tip is replaced with a new one, or once removed and attached to a chemical solution etc., it will be costly, and bonding conditions will change due to removal, replacement, and attachment of the capillary, The adjustment requires a large amount of work, resulting in a problem that the production efficiency is lowered.

そのため、できるだけキャピラリの交換や取り外しを伴う清掃を避けて、キャピラリの先端に付着した汚れを落とす作業を行う必要があり、種々の検討を行った結果、本発明に至った。   For this reason, it is necessary to perform the operation of removing dirt attached to the tip of the capillary while avoiding cleaning involving replacement and removal of the capillary as much as possible. As a result of various studies, the present invention has been achieved.

なお、前記特許文献１（特開２０００−２３２１２５号公報）の図５に記載されているワイヤボンディング装置は、清掃パットを設けることにより、キャピラリの取り外しを伴わないでキャピラリの清掃を行うことが可能な装置ではある。しかし、前記特許文献１では、清掃パットの表面がダイヤモンドの粉により粗面化されており、このように粗面化された清掃パットの表面でキャピラリを超音波振動させることにより、当該振動によるキャピラリと清掃パッドとの摩擦でキャピラリに付着した汚れを削り落とすようになっている。そのため、キャピラリに傷を付ける場合もあり、逆にキャピラリの寿命を短くしてしまう場合もある。よって、前記した問題は特許文献１によって解消されるものではない。   In addition, the wire bonding apparatus described in FIG. 5 of the said patent document 1 (Unexamined-Japanese-Patent No. 2000-232125) can clean a capillary without the removal of a capillary by providing a cleaning pad. It is a device. However, in Patent Document 1, the surface of the cleaning pad is roughened with diamond powder, and the capillary is ultrasonically vibrated on the surface of the cleaning pad roughened in this way, thereby generating a capillary due to the vibration. The dirt adhering to the capillary is scraped off by friction with the cleaning pad. Therefore, the capillary may be damaged, and conversely, the life of the capillary may be shortened. Therefore, the above-described problem is not solved by Patent Document 1.

本発明の目的は、キャピラリの汚れを清掃することで確実なワイヤボンディングを実現し、これにより、ワイヤ剥がれ等のボンディング不良を防止して製品の歩留りを向上させることができる技術を提供することにある。   An object of the present invention is to provide a technique capable of realizing reliable wire bonding by cleaning dirt on a capillary, thereby preventing bonding failure such as wire peeling and improving product yield. is there.

また、本発明の他の目的は、ワイヤ剥がれ等のボンディング不良を防止して製品の品質を向上させることができる技術を提供することにある。   Another object of the present invention is to provide a technique capable of improving the quality of a product by preventing bonding failure such as wire peeling.

また、本発明の他の目的は、キャピラリの汚れを清掃することでキャピラリの交換回数を減らし、半導体装置の製造における製造コストを抑えることができる技術を提供することにある。   Another object of the present invention is to provide a technique capable of reducing the number of times of replacement of the capillary by cleaning dirt on the capillary and suppressing the manufacturing cost in manufacturing the semiconductor device.

また、本発明の他の目的は、自動でキャピラリの汚れを清掃することで作業者が手作業でキャピラリの交換を行う等の手間を軽減し、半導体装置の製造における作業効率を向上させることができる技術を提供することにある。   Another object of the present invention is to automatically remove the dirt on the capillaries, thereby reducing the trouble of manually replacing the capillaries and the like, and improving the working efficiency in manufacturing the semiconductor device. It is to provide a technology that can be used.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

すなわち、本発明は、ボンディングツールであるキャピラリを用いて、ヒートステージ上に配置された半導体チップと半導体チップに隣接して配置されたリードとをワイヤで接続するワイヤボンディング工程を有するものである。そして、ワイヤボンディング工程において、一定条件に到達した場合に、キャピラリを用いて、ヒートステージに設けられたキャピラリ清掃ツール上で空ボンディングを行うことで、キャピラリに付着した汚れをキャピラリ清掃ツールに転写させるキャピラリ清掃工程を有するものである。   That is, the present invention includes a wire bonding step of connecting a semiconductor chip arranged on a heat stage and a lead arranged adjacent to the semiconductor chip with a wire using a capillary as a bonding tool. Then, when a certain condition is reached in the wire bonding process, by using the capillary and performing empty bonding on the capillary cleaning tool provided on the heat stage, the dirt adhering to the capillary is transferred to the capillary cleaning tool. It has a capillary cleaning process.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下のとおりである。   Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

ワイヤボンディング工程において、ワイヤボンディングが一定条件に到達した場合に、キャピラリを用いて、ヒートステージに設けられたキャピラリ清掃ツール上で空ボンディングを行うことで、キャピラリに付着した汚れをキャピラリ清掃ツールに転写させることができる。その結果、キャピラリの汚れを清掃して確実なワイヤボンディングを実現し、これにより、ワイヤ剥がれ等のボンディング不良を防止して製品の歩留りを向上させることができる。また、ワイヤ剥がれ等のボンディング不良を防止して製品の品質を向上させることができる。また、キャピラリの汚れを清掃することでキャピラリの交換回数を減らし、半導体装置の製造における製造コストを抑えることができる。また、自動でキャピラリの汚れを清掃することで作業者が手作業でキャピラリの交換を行う等の手間を軽減し、半導体装置の製造における作業効率を向上させることができる。   In the wire bonding process, when wire bonding reaches a certain condition, using the capillary, empty bonding is performed on the capillary cleaning tool provided on the heat stage to transfer the dirt adhering to the capillary to the capillary cleaning tool. Can be made. As a result, the dirt on the capillary is cleaned to realize reliable wire bonding, thereby preventing bonding defects such as wire peeling and improving product yield. Moreover, bonding defects such as wire peeling can be prevented and the product quality can be improved. In addition, cleaning the capillaries can reduce the number of times the capillaries are replaced, thereby reducing the manufacturing cost in manufacturing the semiconductor device. Also, by automatically cleaning the dirt on the capillaries, it is possible to reduce the time and labor required for the operator to manually replace the capillaries, and to improve the working efficiency in manufacturing the semiconductor device.

以下の実施の形態では特に必要なとき以外は同一または同様な部分の説明を原則として繰り返さない。   In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

さらに、以下の実施の形態では便宜上その必要があるときは、複数のセクションまたは実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに無関係なものではなく、一方は他方の一部または全部の変形例、詳細、補足説明などの関係にある。   Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

また、以下の実施の形態において、要素の数など（個数、数値、量、範囲などを含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される場合などを除き、その特定の数に限定されるものではなく、特定の数以上でも以下でも良いものとする。   Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

また、実施の形態で用いる図面においては、断面図であっても図面を見易くするためにハッチングを省略する場合もある。さらに、実施の形態で用いる図面においては、実施の形態の特徴部分を強調するため、実際の構造を簡略化して表す場合もある。   In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Furthermore, in the drawings used in the embodiments, the actual structure may be simplified in order to emphasize the characteristic portions of the embodiments.

（実施の形態）
図１は本発明の実施の形態の半導体装置（ＱＦＰ）の構造の一例を示す断面図、図２は図１に示す半導体装置の組み立て手順の一例を示す製造プロセスフロー図である。また、図３は本発明の実施の形態のワイヤボンダの構造の一例を示す斜視図、図４は図３に示すワイヤボンダのヒートステージの構造の一例を示す拡大平面図、図５は図４に示すヒートステージをＡ−Ａ線に沿って切断した構造の一例を示す拡大断面図である。また、図６は本実施の形態のワイヤボンディング工程の手順の一例を示す製造プロセスフロー図、図７はワイヤボンディング時のヒートステージ等の様子の一例を示す拡大平面図、図８は図７に示すヒートステージ等をＢ−Ｂ線に沿って切断した構造の一例を示す拡大断面図である。また、図９は本発明の実施の形態のキャピラリ清掃工程の手順の一例を示す製造プロセスフロー図、図１０は本発明の実施の形態のキャピラリ清掃工程の手順の他の例を示す製造プロセスフロー図である。 (Embodiment)
FIG. 1 is a sectional view showing an example of the structure of a semiconductor device (QFP) according to an embodiment of the present invention, and FIG. 2 is a manufacturing process flow chart showing an example of an assembly procedure of the semiconductor device shown in FIG. 3 is a perspective view showing an example of the structure of the wire bonder according to the embodiment of the present invention, FIG. 4 is an enlarged plan view showing an example of the structure of the heat stage of the wire bonder shown in FIG. 3, and FIG. 5 is shown in FIG. It is an expanded sectional view which shows an example of the structure which cut | disconnected the heat stage along the AA line. 6 is a manufacturing process flow chart showing an example of the procedure of the wire bonding process of the present embodiment, FIG. 7 is an enlarged plan view showing an example of the state of the heat stage, etc. during wire bonding, and FIG. It is an expanded sectional view which shows an example of the structure which cut | disconnected the heat stage etc. which are shown along a BB line. FIG. 9 is a manufacturing process flow chart showing an example of the procedure of the capillary cleaning process of the embodiment of the present invention, and FIG. 10 is a manufacturing process flow showing another example of the procedure of the capillary cleaning process of the embodiment of the present invention. FIG.

まず、図１を用いて、本発明の実施の形態の半導体装置の一例の構成を説明する。本実施の形態の半導体装置１は、樹脂封止形で、面実装形の半導体パッケージであり、例えばＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）形態の半導体装置である。   First, the configuration of an example of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. The semiconductor device 1 according to the present embodiment is a resin-encapsulated and surface-mounted semiconductor package, for example, a QFP (Quad Flat Package) semiconductor device.

図１に示すように、本実施の形態の半導体装置１は、封止樹脂部２と、封止樹脂部２によって封止された半導体チップ（半導体素子）３と、導電体によって形成された複数のリード４と、封止樹脂部２によって封止されかつ複数のリード４と半導体チップ３の表面の複数の電極（パッド）３ａとを電気的に接続する複数のワイヤ６と、半導体チップ３が搭載されたチップ搭載部であるタブ（ダイパッド）７とを備えている。また、タブ７に接続された複数の吊りリード８（図７に図示）を備えている。   As shown in FIG. 1, the semiconductor device 1 of the present embodiment includes a sealing resin portion 2, a semiconductor chip (semiconductor element) 3 sealed with the sealing resin portion 2, and a plurality of conductors. A plurality of wires 6 that are sealed by the sealing resin portion 2 and electrically connect the plurality of leads 4 and the plurality of electrodes (pads) 3a on the surface of the semiconductor chip 3, and the semiconductor chip 3 A tab (die pad) 7 which is a mounted chip mounting portion is provided. Further, a plurality of suspension leads 8 (shown in FIG. 7) connected to the tab 7 are provided.

封止樹脂部２は、例えば、シリコン樹脂やエポキシ樹脂などの絶縁性樹脂材料からなる。この封止樹脂部２により、半導体チップ３、リード４、ワイヤ６、タブ７および吊りリード８が封止され、保護される。また、封止樹脂部２の裏面２ａが、半導体装置１の実装面である。   The sealing resin portion 2 is made of, for example, an insulating resin material such as silicon resin or epoxy resin. With this sealing resin portion 2, the semiconductor chip 3, the lead 4, the wire 6, the tab 7 and the suspension lead 8 are sealed and protected. Further, the back surface 2 a of the sealing resin portion 2 is a mounting surface of the semiconductor device 1.

半導体チップ３は、例えば、単結晶シリコンなどからなる半導体基板（半導体ウエハ）に種々の半導体素子または半導体集積回路を形成した後、必要に応じて半導体基板の裏面研削を行ってから、ダイシングなどにより半導体基板を各半導体チップ３に分離したものである。半導体チップ３は、その表面（半導体素子形成側の主面）が上方を向くようにタブ７上に搭載され、半導体チップ３の裏面が導電体からなるタブ７に、例えば銀ペーストまたは絶縁ペーストなどの接合材（図示省略）を介して接合されている。   For example, the semiconductor chip 3 is formed by forming various semiconductor elements or semiconductor integrated circuits on a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like, and then grinding the back surface of the semiconductor substrate as necessary, followed by dicing or the like. The semiconductor substrate is separated into each semiconductor chip 3. The semiconductor chip 3 is mounted on the tab 7 so that the surface (main surface on the semiconductor element forming side) faces upward, and the back surface of the semiconductor chip 3 is placed on the tab 7 made of a conductor, for example, silver paste or insulating paste. Are joined via a joining material (not shown).

半導体チップ３の表面には、アルミニウムなどからなる複数の電極（パッド）３ａが形成されている。電極３ａは、半導体チップ３に形成された半導体素子または半導体集積回路に電気的に接続されている。半導体チップ３の表面の各電極３ａは、当該半導体チップ３に隣接して配置された各リード４の上面４ａに、例えば金（Ａｕ）線などの金属細線などからなるワイヤ６を介して電気的に接続されている。   A plurality of electrodes (pads) 3 a made of aluminum or the like are formed on the surface of the semiconductor chip 3. The electrode 3a is electrically connected to a semiconductor element or a semiconductor integrated circuit formed on the semiconductor chip 3. Each electrode 3a on the surface of the semiconductor chip 3 is electrically connected to the upper surface 4a of each lead 4 arranged adjacent to the semiconductor chip 3 via a wire 6 made of a metal thin wire such as a gold (Au) wire. It is connected to the.

リード４はタブ７の周囲に、その一端がタブ７に対向するように配置されている。リード４は、封止樹脂部２に埋め込まれたインナリードと、封止樹脂部２の側面２ｂに露出するアウタリードとの両者の機能を兼ねている。すなわち、封止樹脂部２によって封止され、リード４のボンディング部として機能し得るリード４の上面４ａにワイヤ６が接合され、封止樹脂部２の側面２ｂに外部接続端子として機能し得るリード４が、例えばガルウイング状に露出している。なお、リード４の上面４ａには、ワイヤ６の接続を容易にするためにメッキ層（例えば銀メッキ層）を形成することもできる。   The lead 4 is arranged around the tab 7 so that one end thereof faces the tab 7. The lead 4 has both functions of an inner lead embedded in the sealing resin portion 2 and an outer lead exposed on the side surface 2b of the sealing resin portion 2. That is, the wire 6 is bonded to the upper surface 4a of the lead 4 which is sealed by the sealing resin portion 2 and can function as a bonding portion of the lead 4, and the lead which can function as an external connection terminal on the side surface 2b of the sealing resin portion 2. 4 is exposed in a gull wing shape, for example. A plating layer (for example, a silver plating layer) can be formed on the upper surface 4a of the lead 4 in order to facilitate the connection of the wire 6.

リード４と半導体チップ３との間は封止樹脂部２を構成する材料で満たされており、リード４と半導体チップ３とが接触しないようになっている。また、隣り合うリード４間は封止樹脂部２を構成する材料により満たされており、互いに接触しないようになっている。   The space between the lead 4 and the semiconductor chip 3 is filled with the material constituting the sealing resin portion 2 so that the lead 4 and the semiconductor chip 3 do not come into contact with each other. Further, the space between the adjacent leads 4 is filled with the material constituting the sealing resin portion 2 so as not to contact each other.

封止樹脂部２の裏面２ａに対応する半導体装置１の裏面が、半導体装置１の実装面となり、封止樹脂部２の側面２ｂから露出した各リード４が、封止樹脂部２の裏面２ａ（すなわち半導体装置１の裏面）と略面一となるようにガルウイング状に曲げ成形されて外部接続端子を構成する。また、封止樹脂部２から露出するリード４の下面にはメッキ層（例えば半田メッキ層）が形成されているが、理解を簡単にするために、メッキ層の図示を省略している。リード４の下面にメッキ層が形成されていることで、半導体装置１を基板（外部基板、マザーボード）に実装する際に、基板上の端子または導体パターンと半導体装置１の端子（リード４の下面）との間の電気的接続の信頼性を向上することができる。   The back surface of the semiconductor device 1 corresponding to the back surface 2a of the sealing resin portion 2 is the mounting surface of the semiconductor device 1, and each lead 4 exposed from the side surface 2b of the sealing resin portion 2 is the back surface 2a of the sealing resin portion 2. The external connection terminal is formed by being bent into a gull wing shape so as to be substantially flush with (that is, the back surface of the semiconductor device 1). Further, although a plating layer (for example, a solder plating layer) is formed on the lower surface of the lead 4 exposed from the sealing resin portion 2, the illustration of the plating layer is omitted for easy understanding. Since the plating layer is formed on the lower surface of the lead 4, when the semiconductor device 1 is mounted on the substrate (external substrate, motherboard), the terminal or conductor pattern on the substrate and the terminal of the semiconductor device 1 (the lower surface of the lead 4). ) Can improve the reliability of the electrical connection.

タブ７には、複数（例えば４本）の吊りリード８が接続されている。各吊りリード８は、導電体材料からなり、一端がタブ７に接続され、タブ７の外方に向かって延在している。吊りリード８は、半導体装置１の製造に用いられたリードフレーム５（のフレーム枠）にタブ７を保持または支持するために設けられ、封止樹脂部２の形成後にリードフレーム５から切断され、吊りリード８の切断により生じた側面（すなわちタブ７に接続された側の端部とは逆側の端部）である切断面が封止樹脂部２の側面（切断面）２ｂで露出している。リード４、タブ７および吊りリード８は、いずれも導電体材料からなり、例えば半導体装置の製造の際にリードフレームに用いられた共通の導電体材料からなる。   A plurality of (for example, four) suspension leads 8 are connected to the tab 7. Each suspension lead 8 is made of a conductive material, and has one end connected to the tab 7 and extending outward from the tab 7. The suspension lead 8 is provided to hold or support the tab 7 on the lead frame 5 (frame frame) used for manufacturing the semiconductor device 1, and is cut from the lead frame 5 after the formation of the sealing resin portion 2. A cut surface that is a side surface (that is, an end portion opposite to the end portion connected to the tab 7) generated by cutting the suspension lead 8 is exposed at the side surface (cut surface) 2 b of the sealing resin portion 2. Yes. The lead 4, the tab 7 and the suspension lead 8 are all made of a conductor material, for example, a common conductor material used for a lead frame in manufacturing a semiconductor device.

次に、本実施の形態の半導体装置（ＱＦＰ）１の製造方法の一例の手順を、図２に示す製造プロセスフロー図を用いて説明する。図２における各製造工程の右側には、本実施の形態の半導体装置１の各製造工程における断面図（要部断面図）を示している。また、図２には、リードフレーム５の一つの半導体パッケージに対応する領域（そこから一つの半導体装置１が製造される領域）を示している。   Next, the procedure of an example of the manufacturing method of the semiconductor device (QFP) 1 of the present embodiment will be described with reference to the manufacturing process flow chart shown in FIG. The right side of each manufacturing process in FIG. 2 shows a cross-sectional view (main part cross-sectional view) in each manufacturing process of the semiconductor device 1 of the present embodiment. FIG. 2 shows a region corresponding to one semiconductor package of the lead frame 5 (a region from which one semiconductor device 1 is manufactured).

まず、図２のステップＳ１に示すように、半導体装置１の製造に用いられるリードフレーム５を準備する（フレーム準備工程）。リードフレーム５は、例えば、銅または銅合金、あるいは４２−アロイなどの導電体材料からなるプレス加工フレーム（エッチング加工フレームでも良い）で構成されている。また、リードフレーム５は、半導体チップ３を搭載するためのタブ７と、その一端がタブ７と離間して対向するように配置され、他端がリードフレーム５のフレーム枠（図示省略）と接続するリード４とを有している。また、タブ７の四隅に吊りリード８（図７に図示）の一端が接続し、吊りリード８の他端がフレーム枠に接続して、タブ７がリードフレーム５のフレーム枠に保持または支持されている。   First, as shown in step S1 of FIG. 2, the lead frame 5 used for manufacturing the semiconductor device 1 is prepared (frame preparation process). The lead frame 5 is configured by a press-worked frame (or an etching-worked frame) made of a conductive material such as copper, a copper alloy, or 42-alloy, for example. The lead frame 5 is arranged so that the tab 7 for mounting the semiconductor chip 3 and one end of the lead frame 5 are separated from the tab 7 and face each other, and the other end is connected to a frame frame (not shown) of the lead frame 5. And leads 4 to be used. Further, one end of the suspension lead 8 (shown in FIG. 7) is connected to the four corners of the tab 7, the other end of the suspension lead 8 is connected to the frame frame, and the tab 7 is held or supported by the frame frame of the lead frame 5. ing.

また、その他、半導体装置１の組み立てに必要な、半導体チップ３、金（Ａｕ）線などの金属細線からなるワイヤ６、樹脂封止部２となるシリコン樹脂やエポキシ樹脂などの絶縁性樹脂材料などを準備する。半導体チップ３は、単結晶シリコンなどからなる半導体基板上に形成されたＡＳＩＣ（Ａｐｐｌｉｃａｔｉｏｎ Ｓｐｅｃｉｆｉｃ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）やマイクロコンピュータなどを有し、この表面上にアルミニウムなどの電極（パッド）３ａが形成され、内部に形成されたＡＳＩＣやマイクロコンピュータなどの所定の回路の各端子から表面上の電極３ａまで電気的に接続されたものである。また、半導体チップ３は、ウェハの前工程において、酸化・拡散・不純物導入、配線パターン形成、絶縁層形成、配線層形成などのウエハ処理工程を繰り返して所望の回路が形成され、このウェハを切断してチップ毎に個別に切り離されたものである。   In addition, the semiconductor chip 3, the wire 6 made of a fine metal wire such as a gold (Au) wire, the insulating resin material such as silicon resin or epoxy resin that becomes the resin sealing portion 2 necessary for the assembly of the semiconductor device 1, etc. Prepare. The semiconductor chip 3 has an ASIC (Application Specific Integrated Circuit) or a microcomputer formed on a semiconductor substrate made of single crystal silicon or the like, and an electrode (pad) 3a such as aluminum is formed on the surface, Are electrically connected from each terminal of a predetermined circuit such as an ASIC or microcomputer formed to the electrode 3a on the surface. Further, in the semiconductor chip 3, a desired circuit is formed by repeating wafer processing steps such as oxidation / diffusion / impurity introduction, wiring pattern formation, insulating layer formation, and wiring layer formation in the previous process of the wafer, and this wafer is cut. Thus, each chip is separated individually.

その後、図２のステップＳ２に示すように、リードフレーム５のタブ７上に半導体チップ３を銀ペーストまたは絶縁ペーストなどの接合材（図示省略）を介して接合する（ダイボンディング工程）。   Thereafter, as shown in step S2 of FIG. 2, the semiconductor chip 3 is bonded onto the tab 7 of the lead frame 5 via a bonding material (not shown) such as silver paste or insulating paste (die bonding step).

その後、図２のステップＳ３に示すように、半導体チップ３の複数の電極３ａと、半導体チップ３に隣接して配置されたリードフレーム５の複数のリード４の上面４ａとを複数のワイヤ６を介してそれぞれ電気的に接続する（ワイヤボンディング工程）。この際、ファーストボンディングとしてワイヤ６の一端を半導体チップ３の電極３ａに接続してから、セカンドボンディングとしてワイヤ６の他端をリード４の上面４ａに接続する。なお、このステップＳ３に示すワイヤボンディング工程については、詳細を後述する。   Thereafter, as shown in step S3 of FIG. 2, the plurality of electrodes 3a of the semiconductor chip 3 and the upper surfaces 4a of the plurality of leads 4 of the lead frame 5 arranged adjacent to the semiconductor chip 3 are connected to the plurality of wires 6. Are electrically connected to each other (wire bonding step). At this time, one end of the wire 6 is connected to the electrode 3a of the semiconductor chip 3 as first bonding, and the other end of the wire 6 is connected to the upper surface 4a of the lead 4 as second bonding. Details of the wire bonding process shown in step S3 will be described later.

その後、図２のステップＳ４に示すように、例えばトランスファモールド法により、半導体チップ３、リード４の一部、ワイヤ６およびタブ７を封止樹脂部２によって封止する（モールド工程）。封止樹脂部２は、例えば、シリコン樹脂やエポキシ樹脂などの絶縁性樹脂材料からなる。また、モールド工程では、封止樹脂部２の側面２ｂからリード４が露出するように、封止樹脂部２を形成する。   Thereafter, as shown in step S4 of FIG. 2, the semiconductor chip 3, a part of the lead 4, the wire 6 and the tab 7 are sealed with the sealing resin portion 2 by, for example, a transfer molding method (molding process). The sealing resin portion 2 is made of, for example, an insulating resin material such as silicon resin or epoxy resin. In the molding process, the sealing resin portion 2 is formed so that the lead 4 is exposed from the side surface 2b of the sealing resin portion 2.

その後、必要に応じてリードフレーム５の封止樹脂部２から露出する部分（導電体からなる部分）上にメッキ層（図示省略）を形成した後、図２のステップＳ５に示すように、封止樹脂部２から突出したリードフレーム５のリード４を所定の長さを残して切断し、このリード４をガルウイング状に成形して外部接続端子とする。これにより、図１に示すようなＱＦＰ構造の半導体装置１が完成する（切断・成形工程）。   Thereafter, if necessary, a plating layer (not shown) is formed on a portion exposed from the sealing resin portion 2 of the lead frame 5 (portion made of a conductor), and then sealed as shown in step S5 of FIG. The lead 4 of the lead frame 5 protruding from the stop resin portion 2 is cut leaving a predetermined length, and this lead 4 is formed into a gull wing shape to serve as an external connection terminal. Thereby, the semiconductor device 1 having the QFP structure as shown in FIG. 1 is completed (cutting / molding step).

次に、本実施の形態の半導体装置１の製造方法における図２のステップＳ３に示すワイヤボンディング工程及び当該ワイヤボンディング工程に用いるワイヤボンダについて詳細に説明する。   Next, the wire bonding process shown in step S3 of FIG. 2 and the wire bonder used in the wire bonding process in the method for manufacturing the semiconductor device 1 of the present embodiment will be described in detail.

まず、ワイヤボンディング工程に用いるワイヤボンダ１０について説明する。ワイヤボンダ１０は、リードフレーム５のリード４と、当該リードフレーム５のタブ７にダイボンディングされた半導体チップ３の電極３ａとを、ワイヤ６で電気的に接続する装置である。   First, the wire bonder 10 used for a wire bonding process is demonstrated. The wire bonder 10 is a device that electrically connects the lead 4 of the lead frame 5 and the electrode 3 a of the semiconductor chip 3 die-bonded to the tab 7 of the lead frame 5 with a wire 6.

図３に示すように、本実施の形態のワイヤボンダ１０は、一定の荷重と熱、さらに超音波振動をワイヤ６に伝えて圧接する超音波併用熱圧着方式のワイヤボンダであり、ワイヤボンディングを行うための主要な装置を搭載したボンディングヘッド１１を備えている。このボンディングヘッド１１には、振動源となる振動子（図示省略）、振動振幅を増大させるＵＳホーン１２及び圧着子（ボンディングツール）であるキャピラリ２０等からなる超音波発振子を有している。前記ＵＳホーン１２は略水平方向に延在する略円柱状に形成されており、一端側に前記振動子が取り付けられ、他端側に前記キャピラリ２０が取り付けられている。   As shown in FIG. 3, the wire bonder 10 of this embodiment is a wire bonder of a thermocompression bonding method that uses a pressure and heat, and further transmits ultrasonic vibration to the wire 6 and press-contacts the wire bonder 10 for wire bonding. The bonding head 11 on which the main apparatus is mounted is provided. The bonding head 11 includes an ultrasonic oscillator including a vibrator (not shown) serving as a vibration source, a US horn 12 that increases vibration amplitude, and a capillary 20 serving as a crimping tool (bonding tool). The US horn 12 is formed in a substantially cylindrical shape extending in a substantially horizontal direction, and the vibrator is attached to one end side and the capillary 20 is attached to the other end side.

前記キャピラリ２０は、例えばセラミック等からなり、略円柱状に形成されてその下部先端がテーパ状に細くなるように形成されている。そして、その先端からは、例えば金線等のワイヤ６を繰り出すことができるようになっている。そして、ワイヤボンディング時にキャピラリ２０から超音波を発振することにより、繰り出したワイヤ６の塑性変形が補助されて、半導体チップ３の表面に形成される電極３ａとワイヤ６及び半導体チップ３に隣接して配置されたリードフレーム５のリード４とワイヤ６との融着が促されるようになっている。印加する超音波の振動周波数としては、例えば６０〜１２５ｋＨｚを採用することができる。また、キャピラリ２０を電極３ａに押しつける際に、押さえ（図示省略）によって押圧荷重を負荷することで、電極３ａとワイヤ６及びリード４とワイヤ６との融着が促されるようになっている。荷重としては、例えば５〜１００ｇを採用することができる。   The capillary 20 is made of, for example, ceramic or the like, and is formed in a substantially cylindrical shape so that the lower end thereof is tapered. From the tip, for example, a wire 6 such as a gold wire can be fed out. Then, by oscillating ultrasonic waves from the capillary 20 during wire bonding, plastic deformation of the drawn-out wire 6 is assisted, so that the electrode 3 a formed on the surface of the semiconductor chip 3, the wire 6 and the semiconductor chip 3 are adjacent to each other. Fusion of the lead 4 and the wire 6 of the arranged lead frame 5 is promoted. As the vibration frequency of the applied ultrasonic waves, for example, 60 to 125 kHz can be employed. Further, when the capillary 20 is pressed against the electrode 3a, a pressing load is applied by pressing (not shown) so as to promote fusion between the electrode 3a and the wire 6 and between the lead 4 and the wire 6. As the load, for example, 5 to 100 g can be adopted.

また、ボンディングヘッド１１におけるキャピラリ２０の近くにはワイヤクランパ１３を有しており、キャピラリ２０に通される前のワイヤ６をクランプすることができるようになっている。また、ボンディングヘッド１１はＸＹテーブル１４上に搭載されており、このＸＹテーブル１４によりキャピラリ２０がＸＹ方向に移動して、半導体チップ３の各電極３ａとリードフレーム５の各リード４とをそれぞれワイヤ６で繋ぐようになっている。また、ボンディングヘッド１１にはカメラ１５を搭載しており、このカメラ１５によりワイヤボンディングを行う半導体チップ３の電極３ａやリードフレーム５のリード４の位置を正確に把握するようになっている。また、ボンディングヘッド１１には例えばトーチ（図示省略）を有しており、このトーチ等による高圧放電によってワイヤ６の先端が溶融され、後述するボールが形成されるようになっている。   A wire clamper 13 is provided near the capillary 20 in the bonding head 11 so that the wire 6 before passing through the capillary 20 can be clamped. The bonding head 11 is mounted on an XY table 14, and the capillary 20 is moved in the XY direction by the XY table 14, so that each electrode 3 a of the semiconductor chip 3 and each lead 4 of the lead frame 5 are respectively wired. 6 is connected. In addition, a camera 15 is mounted on the bonding head 11, and the position of the electrode 3 a of the semiconductor chip 3 and the lead 4 of the lead frame 5 on which wire bonding is performed is accurately grasped by the camera 15. In addition, the bonding head 11 has, for example, a torch (not shown), and the tip of the wire 6 is melted by high-pressure discharge by the torch or the like to form a ball to be described later.

また、ワイヤボンダ１０は、ボンディングヘッド１１外に、半導体チップ３がダイボンディングされたリードフレーム５を搬送するフィーダ１６を備えており、当該フィーダ１６上におけるキャピラリ２０の設置位置付近に、搬送されてきたリードフレーム５を配置し、キャピラリ２０を用いたワイヤボンディングを行うヒートステージ３０を備えている。本実施の形態のヒートステージ３０は、図４に示すように、熱伝導率の良いセラミック、金属等の材質からなる例えば平面視略方形状の部材であり、図５に示すように、リードフレーム５を配置してワイヤボンディングを行う箇所は、他の箇所よりも１段高くなった半導体装置搭載エリア３１となっている。この半導体装置搭載エリア３１の略中心位置には、リードフレーム５のタブ７にダイボンディングされた半導体チップ３が配置される半導体チップ搭載エリア３２を有している。当該半導体チップ搭載エリア３２の中心位置は、リードフレーム５の裏面側に突出しているタブ７を収めるタブ逃げ用溝３３を備えている。また、タブ逃げ用溝３３を中心としてＸ字状に、リードフレーム５の裏面側にタブ７と同様に突出している吊りリード８を収める吊りリード逃げ用溝３４を備えている。なお、タブ逃げ用溝３３及び吊りリード逃げ用溝３４は、前記した形状に限るものではなく、タブ７及び吊りリード８の大きさ、形状等に合わせて形成されていれば良い。また、半導体チップ搭載エリア３２におけるタブ逃げ用溝３３及び吊りリード逃げ用溝３４以外の箇所（本実施の形態ではＸ字状のタブ逃げ用溝３３同士の間に１箇所ずつで合計４箇所）に、真空吸着装置（図示省略）に接続された吸引口３５を備えている。この吸引口３５により、配置されたリードフレーム５のタブ７にダイボンディングされた半導体チップ３を真空吸着して固定し、ワイヤボンディング時にワイヤ６を融着しやすくするようになっている。また、ヒートステージ３０は、ワイヤが融着しやすくなるように、例えば１００〜２３０℃に加熱されるようになっている。なお、ヒートステージ３０は、その全体が加熱されるようになっているが、半導体装置搭載エリア３１や後述するキャピラリ清掃ツール３６付近は、ワイヤボンディング時のワイヤ６の融着性を良くしたり、キャピラリ２０の清掃時に汚れを転写し易くしたりするために、ヒートステージ３０の材質を変える等によって、温度が他の箇所と異なる（温度が高い又は低い）ようにしてあっても良い。   In addition, the wire bonder 10 includes a feeder 16 that conveys the lead frame 5 to which the semiconductor chip 3 is die-bonded, outside the bonding head 11, and has been conveyed near the installation position of the capillary 20 on the feeder 16. The lead frame 5 is disposed, and a heat stage 30 for performing wire bonding using the capillary 20 is provided. As shown in FIG. 4, the heat stage 30 of the present embodiment is a member having, for example, a substantially rectangular shape in plan view and made of a material such as ceramic or metal having a high thermal conductivity. As shown in FIG. A portion where 5 is disposed and wire bonding is performed is a semiconductor device mounting area 31 which is one step higher than other portions. The semiconductor device mounting area 31 has a semiconductor chip mounting area 32 in which the semiconductor chip 3 die-bonded to the tab 7 of the lead frame 5 is disposed at a substantially central position. The center position of the semiconductor chip mounting area 32 is provided with a tab escape groove 33 for receiving the tab 7 protruding on the back surface side of the lead frame 5. Further, a suspension lead escape groove 34 for receiving the suspension lead 8 protruding in the same manner as the tab 7 is provided on the back surface side of the lead frame 5 in an X shape centering on the tab relief groove 33. The tab escape groove 33 and the suspension lead relief groove 34 are not limited to the shapes described above, and may be formed in accordance with the size, shape, and the like of the tab 7 and the suspension lead 8. Further, locations other than the tab escape groove 33 and the suspension lead escape groove 34 in the semiconductor chip mounting area 32 (in this embodiment, one location between the X-shaped tab relief grooves 33 is a total of four locations). And a suction port 35 connected to a vacuum suction device (not shown). By this suction port 35, the semiconductor chip 3 die-bonded to the tab 7 of the arranged lead frame 5 is fixed by vacuum suction so that the wire 6 can be easily fused at the time of wire bonding. Further, the heat stage 30 is heated to, for example, 100 to 230 ° C. so that the wires are easily fused. The entire heat stage 30 is heated, but the vicinity of the semiconductor device mounting area 31 and the capillary cleaning tool 36 described later can improve the fusion property of the wire 6 during wire bonding, In order to facilitate transfer of dirt during cleaning of the capillary 20, the temperature may be different from other parts (temperature is high or low) by changing the material of the heat stage 30.

また、図４及び図５に示すように、ヒートステージ３０は、当該ヒートステージ３０の表面上における半導体装置搭載エリア３１とは異なる位置に、キャピラリ清掃ツール（異物除去シート）３６を有している。本実施の形態のキャピラリ清掃ツール３６は、ヒートステージ３０の表面の一部に形成した凹部３７を有している。本実施の形態の凹部３７は、平面視略方形状の凹部であり、ヒートステージ３０におけるリードフレーム５の搬送方向（例えば、図４及び図５の右から左に向かう方向）Ｃの前方側の端部付近に形成されている。また、キャピラリ清掃ツール３６の凹部３７の中には、所定厚みのメッキ層３８が形成されている。メッキ層３８としては、銀メッキ、パラジウムメッキを施したものでも良いが、金線からなるワイヤ６との接着性の良さ等から、本実施の形態では金メッキを施したメッキ層（金メッキ層）３８が形成されている。   As shown in FIGS. 4 and 5, the heat stage 30 has a capillary cleaning tool (foreign substance removal sheet) 36 at a position different from the semiconductor device mounting area 31 on the surface of the heat stage 30. . The capillary cleaning tool 36 of the present embodiment has a recess 37 formed in a part of the surface of the heat stage 30. The concave portion 37 of the present embodiment is a concave portion having a substantially square shape in plan view, and is located on the front side of the lead frame 5 in the heat stage 30 in the conveyance direction C (for example, the direction from right to left in FIGS. 4 and 5). It is formed near the end. A plating layer 38 having a predetermined thickness is formed in the recess 37 of the capillary cleaning tool 36. The plated layer 38 may be silver-plated or palladium-plated, but in the present embodiment, a plated layer (gold-plated layer) 38 that is gold-plated due to its good adhesion to the wire 6 made of gold wire. Is formed.

また、キャピラリ清掃ツール３６の凹部３７の深さ及び大きさとメッキ層３８の厚みは、後述するキャピラリ清掃工程において当該メッキ層３８に対して清掃用の空ボンディングが複数回行われても、製品組立ての際のワイヤボンディング時にフィーダ１６上を搬送されるリードフレーム５の裏面に、清掃用の空ボンディングの際のワイヤ６が接触しないような深さ、大きさ及び厚みに調整されている。なお、キャピラリ清掃ツール３６は、前記したような位置、大きさ及び形状に必ずしも形成されていなくても良い。例えば、本実施の形態より小さめに形成された凹部３７が、ヒートステージ３０におけるワイヤボンディング時に邪魔にならない複数箇所（例えば、ヒートステージ３０の四隅等）に形成されていても良い。また、本発明において空ボンディングとは、製品組立ての際のワイヤボンディング工程以外でキャピラリ清掃用に行うボンディング動作全般を指し、キャピラリ２０からワイヤ６を出す出さないに関わらず空ボンディングと称するものとする。   Further, the depth and size of the concave portion 37 of the capillary cleaning tool 36 and the thickness of the plating layer 38 can be obtained even when the empty cleaning for bonding is performed a plurality of times on the plating layer 38 in the capillary cleaning step described later. The depth, size, and thickness are adjusted so that the back surface of the lead frame 5 conveyed on the feeder 16 at the time of wire bonding does not come into contact with the wire 6 at the time of empty bonding for cleaning. Note that the capillary cleaning tool 36 does not necessarily have to be formed in the position, size, and shape as described above. For example, the recesses 37 formed smaller than the present embodiment may be formed at a plurality of locations (for example, four corners of the heat stage 30) that do not interfere with wire bonding in the heat stage 30. In the present invention, the term “empty bonding” refers to all bonding operations performed for capillary cleaning other than the wire bonding process at the time of product assembly, and is referred to as “empty bonding” regardless of whether the wire 6 is not taken out from the capillary 20. .

次に、前記ワイヤボンダ１０を用いて行う図２のステップＳ３に示すワイヤボンディング工程について詳述する。図６は、本実施の形態のワイヤボンディング工程（半導体チップ３の電極３ａとリード４との間をワイヤ６で接続する工程）の手順の一例を示す製造プロセスフロー図、図７はワイヤボンディング時のヒートステージ等の様子の一例を示す拡大平面図、図８は図７に示すヒートステージ等をＢ−Ｂ線に沿って切断した構造の一例を示す拡大断面図である。   Next, the wire bonding process shown in step S3 of FIG. 2 performed using the wire bonder 10 will be described in detail. FIG. 6 is a manufacturing process flow chart showing an example of the procedure of the wire bonding step (step of connecting the electrode 3a of the semiconductor chip 3 and the lead 4 with the wire 6) according to the present embodiment, and FIG. FIG. 8 is an enlarged sectional view showing an example of a structure obtained by cutting the heat stage shown in FIG. 7 along the line BB.

まず、ワイヤボンダ１０のヒートステージ３０（少なくとも、半導体装置搭載エリア３１）を所定の温度（例えば、１００〜２３０℃）に加熱する。それから、図２のステップＳ２に示すダイボンディング工程を行ったリードフレーム５を、図７及び図８に示すように、加熱されたヒートステージ３０の半導体装置搭載エリア３１に配置して加熱する。その際、半導体装置搭載エリア３１の略中心位置の半導体チップ搭載エリア３２に、リードフレーム５のタブ７にダイボンディングされた半導体チップ３を配置する。また、タブ７及び吊りリード８を、半導体チップ搭載エリア３２におけるタブ逃げ用溝３３及び吊りリード逃げ用溝３４（図４に図示）に収める。また、当該リードフレーム５におけるタブ７にダイボンディングされた半導体チップ３を吸引口３５により真空吸着して半導体装置搭載エリア３１の半導体チップ搭載エリア３２に固定する。また、リードクランパ（リード押さえ）３９により所定の荷重を加えて、リードフレーム５のリード４をヒートステージ３０の半導体装置搭載エリア３１に固定する。   First, the heat stage 30 (at least the semiconductor device mounting area 31) of the wire bonder 10 is heated to a predetermined temperature (for example, 100 to 230 ° C.). Then, the lead frame 5 subjected to the die bonding process shown in step S2 of FIG. 2 is placed and heated in the semiconductor device mounting area 31 of the heated heat stage 30 as shown in FIGS. At that time, the semiconductor chip 3 die-bonded to the tab 7 of the lead frame 5 is disposed in the semiconductor chip mounting area 32 at a substantially central position of the semiconductor device mounting area 31. Further, the tab 7 and the suspension lead 8 are stored in the tab escape groove 33 and the suspension lead relief groove 34 (shown in FIG. 4) in the semiconductor chip mounting area 32. Further, the semiconductor chip 3 die-bonded to the tab 7 in the lead frame 5 is vacuum-sucked by the suction port 35 and fixed to the semiconductor chip mounting area 32 of the semiconductor device mounting area 31. Further, a predetermined load is applied by a lead clamper (lead presser) 39 to fix the lead 4 of the lead frame 5 to the semiconductor device mounting area 31 of the heat stage 30.

また、トーチ等による高圧放電によってその先端を溶融してボール６ａを形成した、金（Ａｕ）線等からなるワイヤ６を、図６のステップＳ３１に示すように、ワイヤボンダ１０のボンディングツールであるキャピラリ２０に保持して、半導体チップ３の電極３ａ上に待機させる（ボール形成工程）。なお、ワイヤ６の直径は例えば２５〜３０μｍ程度である。   Further, as shown in step S31 of FIG. 6, a capillary 6 which is a bonding tool of the wire bonder 10 is used to form a wire 6 made of gold (Au) wire, etc., which has a ball 6a formed by melting its tip by high-pressure discharge with a torch or the like. 20 is made to stand by on the electrode 3a of the semiconductor chip 3 (ball formation process). In addition, the diameter of the wire 6 is about 25-30 micrometers, for example.

それから、図６のステップＳ３２に示すように、キャピラリ２０を下降させ、待機させていたワイヤ６を半導体チップ３の電極３ａ上に適切な荷重をもって接触させる（ファーストボンディング工程）。そして、ワイヤ６のボール６ａが電極３ａに接触した後、キャピラリ２０を超音波振動させ、このときの荷重や印加された超音波による振動エネルギーでボール６ａと電極３ａとを接合させる。   Then, as shown in step S32 of FIG. 6, the capillary 20 is lowered and the waiting wire 6 is brought into contact with the electrode 3a of the semiconductor chip 3 with an appropriate load (first bonding step). Then, after the ball 6a of the wire 6 comes into contact with the electrode 3a, the capillary 20 is ultrasonically vibrated, and the ball 6a and the electrode 3a are joined by the load at this time and the vibration energy by the applied ultrasonic wave.

それから、図６のステップＳ３３に示すように、キャピラリ２０からワイヤ６を繰り出しながら、当該キャピラリ２０を適切な軌跡を描いて移動させ、リード４の上面４ａに移動させる。この軌跡によって、ワイヤ６の適切なループ形状が得られる。そして、キャピラリ２０を下降させて当該キャピラリ２０に保持されたワイヤ６をリード４の上面４ａに対して適切な荷重をもって押し付けると共に、キャピラリ２０を超音波振動させ、このときの荷重や印加された超音波による振動エネルギーでワイヤ６とリード４の上面４ａとを接合させる（セカンドボンディング工程）。   Then, as shown in step S <b> 33 of FIG. 6, while drawing the wire 6 from the capillary 20, the capillary 20 is moved along an appropriate locus and moved to the upper surface 4 a of the lead 4. By this locus, an appropriate loop shape of the wire 6 is obtained. Then, the capillary 20 is lowered and the wire 6 held by the capillary 20 is pressed against the upper surface 4a of the lead 4 with an appropriate load, and the capillary 20 is ultrasonically vibrated. The wire 6 and the upper surface 4a of the lead 4 are bonded with vibration energy by sound waves (second bonding step).

その後、図６のステップＳ３４に示すように、キャピラリ２０を上昇させ、その過程でワイヤクランパ１３でワイヤ６を保持し、ワイヤ６をセカンドボンディング点（接合部）から切断する（ワイヤ切断工程）。このようにして、半導体チップ３の電極３ａとリード４の上面４ａとの間をワイヤ６（ボール６ａを含むワイヤ６）で電気的に接続する。なお、図６のステップＳ３４に示すリード４の先端部近傍の上面４ａには、ワイヤ６の接続を容易にするためにメッキ層（例えば銀メッキ層）が形成されている。   Thereafter, as shown in step S34 of FIG. 6, the capillary 20 is raised, and in the process, the wire 6 is held by the wire clamper 13, and the wire 6 is cut from the second bonding point (joining portion) (wire cutting step). In this way, the wire 6 (the wire 6 including the ball 6a) is electrically connected between the electrode 3a of the semiconductor chip 3 and the upper surface 4a of the lead 4. A plating layer (for example, a silver plating layer) is formed on the upper surface 4a in the vicinity of the tip of the lead 4 shown in step S34 in FIG.

これを繰り返すことにより、半導体チップ３の複数の電極３ａとリードフレーム５の複数のリード４の上面４ａとを複数のワイヤ６を介してそれぞれ電気的に接続することができる。   By repeating this, the plurality of electrodes 3 a of the semiconductor chip 3 and the upper surfaces 4 a of the plurality of leads 4 of the lead frame 5 can be electrically connected through the plurality of wires 6, respectively.

ここで、ワイヤボンディング工程において、ワイヤボンディング（製品組立ての際のワイヤボンディング）が一定条件に到達した場合には、キャピラリ２０に付着した汚れを落とすためのキャピラリ清掃工程を行うようになっている。本実施の形態では、ワイヤボンディングが一定条件に到達した場合とは、キャピラリ２０が行ったボンディング回数（ワイヤ６を半導体チップ３の電極３ａ又はリード４の上面４ａに接合させた回数）が所定回数（例えば、ワイヤ６における半導体チップ３の電極３ａへの接合とリード４の上面４ａへの接合を合わせて１００万回）に達した場合となっている。また、本実施の形態におけるキャピラリ清掃工程は、キャピラリ２０を用いて、前記ヒートステージ３０に設けられた前記キャピラリ清掃ツール３６上で空ボンディングを行うことで、キャピラリ２０に付着した汚れをキャピラリ清掃ツール３６に転写させるものである。   Here, in the wire bonding process, when wire bonding (wire bonding at the time of product assembly) reaches a certain condition, a capillary cleaning process for removing dirt attached to the capillary 20 is performed. In the present embodiment, the case where the wire bonding reaches a certain condition means that the number of times of bonding performed by the capillary 20 (the number of times the wire 6 is bonded to the electrode 3a of the semiconductor chip 3 or the upper surface 4a of the lead 4) is a predetermined number of times. (For example, the bonding of the wire 6 to the electrode 3a of the semiconductor chip 3 and the bonding of the lead 4 to the upper surface 4a are combined 1,000,000 times). Further, in the capillary cleaning process in the present embodiment, the capillary 20 is used to perform empty bonding on the capillary cleaning tool 36 provided on the heat stage 30, thereby removing dirt adhered to the capillary 20. 36 is transferred.

以下、キャピラリ清掃工程の詳細について、図６〜図１０を用いて説明する。前記したような一連のワイヤボンディングが終了したら、図６のステップＳ３５に示すように、リードフレーム５において必要分のワイヤボンディングが終了したか否か（リードフレーム５において電気的に接続する必要のある半導体チップ３の電極３ａとリード４の上面４ａとのワイヤボンディングが全て終了したか否か）の判定を行う。ここで、必要分のワイヤボンディングが終了した場合には、次に、図６のステップＳ３６に示すように、キャピラリ２０が行ったボンディング回数が所定回数（例えば１００万回）を超えているか否かの判定を行う。ここで、ボンディング回数が所定回数を超えていない場合は、次のリードフレーム５のワイヤボンディングを行うが、ボンディング回数が所定回数を超えている場合には、図６のステップＳ３７に示すように、キャピラリ清掃工程を行う。   Hereinafter, the details of the capillary cleaning step will be described with reference to FIGS. When the series of wire bonding as described above is completed, as shown in step S35 of FIG. 6, whether or not the necessary wire bonding is completed in the lead frame 5 (it is necessary to be electrically connected in the lead frame 5). It is determined whether or not all the wire bonding between the electrode 3a of the semiconductor chip 3 and the upper surface 4a of the lead 4 has been completed. Here, when the necessary amount of wire bonding is completed, next, as shown in step S36 of FIG. 6, whether or not the number of bonding performed by the capillary 20 exceeds a predetermined number (for example, 1 million). Judgment is made. Here, when the number of bondings does not exceed the predetermined number, the next lead frame 5 is wire bonded. When the number of bondings exceeds the predetermined number, as shown in step S37 of FIG. Capillary cleaning process is performed.

以下、本実施の形態のキャピラリ清掃工程の一例について、図９を用いて説明する。この例は、セカンドボンディング工程の制御を利用してキャピラリ２０の清掃を行うものである。このキャピラリ清掃工程では、まず、ヒートステージ３０を加熱しておく。   Hereinafter, an example of the capillary cleaning process of the present embodiment will be described with reference to FIG. In this example, the capillary 20 is cleaned using the control of the second bonding process. In this capillary cleaning step, first, the heat stage 30 is heated.

また、図９のステップＳ３７１に示すように、キャピラリ２０をヒートステージ３０に設けられたキャピラリ清掃ツール３６上に移動させる。そして、図９のステップＳ３７２に示すように、キャピラリ２０の先端をキャピラリ清掃ツール３６の凹部３７の中に形成されたメッキ層（本実施の形態では金メッキ層）３８に接触させ、その状態で平行移動させてキャピラリ２０の先端をメッキ層３８に擦り付ける。その際、キャピラリ２０から超音波を発振することにより、キャピラリ２０の先端に付着した汚れがメッキ層３８に転写されるように促す。   Further, as shown in step S371 of FIG. 9, the capillary 20 is moved onto the capillary cleaning tool 36 provided in the heat stage 30. Then, as shown in step S372 of FIG. 9, the tip of the capillary 20 is brought into contact with a plating layer (in this embodiment, a gold plating layer) 38 formed in the concave portion 37 of the capillary cleaning tool 36, and in this state, parallel. The tip of the capillary 20 is rubbed against the plating layer 38 by being moved. At this time, ultrasonic waves are oscillated from the capillary 20 to urge the dirt attached to the tip of the capillary 20 to be transferred to the plating layer 38.

なお、キャピラリ清掃工程におけるキャピラリ２０の超音波出力は、キャピラリ２０の先端に付着した汚れを落ち易くするため、製品組立ての際のワイヤボンディング時以上に設定しておく。例えば、製品組立ての際のワイヤボンディング時よりも超音波出力を０〜５０％程度大きくしておくのが好ましく（超音波出力を０％大きくするというのは出力を変化させないのと同意）、さらには製品組立ての際のワイヤボンディング時よりも超音波出力を３０％程度大きくしておくのがより好ましい。   Note that the ultrasonic output of the capillary 20 in the capillary cleaning step is set more than at the time of wire bonding at the time of product assembly in order to easily remove dirt attached to the tip of the capillary 20. For example, it is preferable to increase the ultrasonic output by about 0 to 50% compared to wire bonding at the time of product assembly (increasing the ultrasonic output by 0% agrees that the output does not change). More preferably, the ultrasonic output is set to be about 30% larger than that during wire bonding at the time of product assembly.

そして、キャピラリ２０の先端を、超音波を発振しながら一定距離又は一定時間メッキ層３８に擦り付けた後、図９のステップＳ３７３に示すように、キャピラリ２０をキャピラリ清掃ツール３６から離間させる。キャピラリ２０のメッキ層３８への擦り付け方などは適宜の方法で行われれば良く、直線状に擦り付けたり、円弧状に擦り付けたり、ジグザグに擦り付けたり、ランダムに擦り付けたりする場合が挙げられる。その後、キャピラリ２０の先端からボール形成に必要な量のワイヤ６を繰り出し、ワイヤ６の先端に製品組立ての際のワイヤボンディング用のボール６ａを形成する等、製品組立てのワイヤボンディングの準備を行い、製品組立てのワイヤボンディングに戻る。このようにして、キャピラリ清掃工程によりキャピラリ２０の先端に付着した汚れを落とす（転写させる）清掃を行う。   Then, the tip of the capillary 20 is rubbed against the plating layer 38 for a certain distance or for a certain time while oscillating ultrasonic waves, and then the capillary 20 is separated from the capillary cleaning tool 36 as shown in step S373 in FIG. The capillary 20 may be rubbed against the plating layer 38 by an appropriate method, such as linear rubbing, arc rubbing, zigzag rubbing, or random rubbing. Thereafter, the wire 6 in an amount necessary for ball formation is fed out from the tip of the capillary 20, and a wire bonding ball 6a for product assembly is formed at the tip of the wire 6 to prepare for wire bonding for product assembly. Return to wire bonding for product assembly. In this way, cleaning is performed to remove (transfer) dirt adhered to the tip of the capillary 20 in the capillary cleaning step.

次に、本実施の形態のキャピラリ清掃工程の他の例について、図１０を用いて説明する。前記例がセカンドボンディング工程の制御を利用してキャピラリ２０の清掃を行うのに対し、この例は、ファーストボンディング工程の制御を利用してキャピラリ２０の清掃を行うものである。このキャピラリ清掃工程では、まず、キャピラリ２０に保持された、切断後のワイヤ６の先端をトーチ等による高圧放電によって溶融して、製品組立ての際のワイヤボンディングで形成するボール６ａよりも小さなボールを形成する。また、ヒートステージ３０を加熱しておく。   Next, another example of the capillary cleaning process of the present embodiment will be described with reference to FIG. In the above example, the capillary 20 is cleaned using the control of the second bonding process, whereas in this example, the capillary 20 is cleaned using the control of the first bonding process. In this capillary cleaning process, first, the tip of the cut wire 6 held by the capillary 20 is melted by high-pressure discharge using a torch or the like, and a ball smaller than the ball 6a formed by wire bonding at the time of product assembly is obtained. Form. Moreover, the heat stage 30 is heated.

ここで、製品組立ての際のボール６ａより小さなボールを形成するのは、以下の理由による。すなわち、製品組立ての際のボール６ａを形成するとボール６ａが大き過ぎて邪魔になり、キャピラリ清掃ツール３６のメッキ層３８にキャピラリ２０が接触し難くなって、キャピラリ２０の汚れを転写する効果が落ちてしまう。また、ボール６ａを形成しないと、ワイヤ６がキャピラリ２０の中に引っ込んでしまい、キャピラリ清掃工程の作業中にワイヤ６をキャピラリ清掃ツール３６のメッキ層３８にボンディングすることができなくなる。ワイヤ６のボール６ａをメッキ層３８にボンディングしていないと、清掃後にキャピラリ２０からワイヤ６を繰り出すのに時間が掛かるため、製品組立てのワイヤボンディングを行うのに支障を来す可能性がある。このため、キャピラリ２０がキャピラリ清掃ツール３６のメッキ層３８に接触し易く、かつワイヤ６がキャピラリ２０の中に引っ込まないようにするために製品組立ての際のボール６ａより小さなボールを形成するのである。   Here, the reason why the ball smaller than the ball 6a at the time of product assembly is formed is as follows. That is, when the ball 6a is formed during product assembly, the ball 6a is too large to obstruct the capillaries 20, making it difficult for the capillaries 20 to contact the plating layer 38 of the capillary cleaning tool 36, and the effect of transferring dirt on the capillaries 20 is reduced. End up. If the ball 6a is not formed, the wire 6 is retracted into the capillary 20, and the wire 6 cannot be bonded to the plating layer 38 of the capillary cleaning tool 36 during the capillary cleaning process. If the ball 6a of the wire 6 is not bonded to the plated layer 38, it takes time to unwind the wire 6 from the capillary 20 after cleaning, which may hinder wire bonding for product assembly. Therefore, in order to prevent the capillary 20 from coming into contact with the plating layer 38 of the capillary cleaning tool 36 and to prevent the wire 6 from being pulled into the capillary 20, a ball smaller than the ball 6a at the time of product assembly is formed. .

その後、図１０のステップＳ３８１に示すように、小さなボール６ａを形成したワイヤ６を保持したキャピラリ２０を、キャピラリ清掃ツール３６上に移動させる。そして、図１０のステップＳ３８２に示すように、キャピラリ２０の先端をキャピラリ清掃ツール３６の凹部３７の中に形成されたメッキ層（本実施の形態では金メッキ層）３８に接触させ、キャピラリ２０から超音波を発振することにより、キャピラリ２０の先端に形成されたボール６ａをメッキ層３８にボンディングする。   Thereafter, as shown in step S381 of FIG. 10, the capillary 20 holding the wire 6 on which the small ball 6a is formed is moved onto the capillary cleaning tool. Then, as shown in step S382 of FIG. 10, the tip of the capillary 20 is brought into contact with a plating layer (in this embodiment, a gold plating layer) 38 formed in the concave portion 37 of the capillary cleaning tool 36, and the capillary 20 By oscillating the sound wave, the ball 6 a formed at the tip of the capillary 20 is bonded to the plating layer 38.

本実施の形態では、ワイヤ６が金線からなり、メッキ層３８が金メッキ層であるため、ボンディングした際の接着性が良いという利点がある。つまり、キャピラリ２０の汚れを転写させる目的としては、金メッキ、銀メッキ、パラジウムメッキ等であれば同等の効果を有するが、金線と金メッキのようにワイヤ６とメッキ層３８との接着性が良いと、清掃用のボンディングを行った後にワイヤクランパ１３でワイヤ６を保持して当該ワイヤ６を切断する際にボンディング箇所が剥がれないため切断し易く、好ましい。また、ボンディングの際に、キャピラリ２０の先端のできるだけ多くの部分がメッキ層３８に接触するように、キャピラリ２０が変形などの支障を来さない程度にキャピラリ２０をメッキ層３８に押し付けて超音波を発振し、キャピラリ２０の先端に付着した汚れがメッキ層３８に転写されるように促す。   In this embodiment, since the wire 6 is made of a gold wire and the plating layer 38 is a gold plating layer, there is an advantage that the adhesiveness when bonding is good. In other words, the purpose of transferring dirt on the capillary 20 is equivalent to the effect of gold plating, silver plating, palladium plating, etc., but the adhesion between the wire 6 and the plating layer 38 is good like gold wire and gold plating. When the wire 6 is held by the wire clamper 13 after the cleaning bonding is performed and the wire 6 is cut, the bonding portion does not peel off, which is preferable. Further, at the time of bonding, the capillary 20 is pressed against the plating layer 38 to the extent that the capillary 20 does not interfere with deformation so that as much of the tip of the capillary 20 as possible contacts the plating layer 38. Oscillates to urge the dirt attached to the tip of the capillary 20 to be transferred to the plating layer 38.

なお、この例においても、前記したセカンドボンディング工程の制御を利用してキャピラリ２０の清掃を行う例の場合と同様に、キャピラリ清掃工程におけるキャピラリ２０の超音波出力は、製品組立ての際のワイヤボンディング時以上に設定しておく。   Also in this example, as in the case of cleaning the capillary 20 using the control of the second bonding process, the ultrasonic output of the capillary 20 in the capillary cleaning process is wire bonding at the time of product assembly. Set more than the hour.

そして、キャピラリ２０の先端を、超音波を発振しながら一定距離又は一定時間メッキ層３８に押し付けた後、図１０のステップＳ３８３に示すように、キャピラリ２０をキャピラリ清掃ツール３６から離間させる。そして、キャピラリ２０の先端からボール形成に必要な量のワイヤ６を繰り出した位置でワイヤ６をワイヤクランパ１３で保持し、ワイヤ６を切断する。その後、ワイヤ６の先端に製品組立ての際のワイヤボンディング用のボール６ａを形成する等、製品組立てのワイヤボンディングの準備を行い、製品組立てのワイヤボンディングに戻る。このようにして、キャピラリ清掃工程によりキャピラリ２０の先端に付着した汚れを落とす（転写させる）清掃を行う。   Then, after the tip of the capillary 20 is pressed against the plating layer 38 for a certain distance or for a certain time while oscillating ultrasonic waves, the capillary 20 is separated from the capillary cleaning tool 36 as shown in step S383 in FIG. Then, the wire 6 is held by the wire clamper 13 at a position where the amount of the wire 6 necessary for ball formation is drawn from the tip of the capillary 20, and the wire 6 is cut. Thereafter, the wire bonding ball 6a for product assembly is formed at the tip of the wire 6 to prepare for the product assembly wire bonding, and the process returns to the product assembly wire bonding. In this way, cleaning is performed to remove (transfer) dirt adhered to the tip of the capillary 20 in the capillary cleaning step.

なお、前記したキャピラリ清掃工程の２つの例において、ワイヤボンダ１０に、キャピラリ２０の先端に付着した汚れがキャピラリ清掃工程によって落ちたか否かを検査するためのカメラ又はセンサ等を設置しておき、キャピラリ清掃工程で空ボンディングを一定量行った後で当該検査を行うようになっていても良い。この場合、汚れが落ちていればキャピラリ清掃工程を終了して製品組立てのワイヤボンディングに戻り、汚れが落ちていなければキャピラリ清掃工程を続行し、汚れが落ちるまで（汚れが落ちたと判断されるまで）繰り返し清掃を行う。これにより、確実にキャピラリ２０の清掃を行うことができる。   In the two examples of the capillary cleaning process described above, the wire bonder 10 is provided with a camera or a sensor for inspecting whether dirt attached to the tip of the capillary 20 has been removed by the capillary cleaning process. The inspection may be performed after performing a certain amount of empty bonding in the cleaning process. In this case, if the dirt is removed, the capillary cleaning process is terminated and the process returns to wire bonding for product assembly. If the dirt is not removed, the capillary cleaning process is continued until the dirt is removed (until the dirt is judged to be removed). ) Repeat cleaning. Thereby, the capillary 20 can be reliably cleaned.

また、本実施の形態では、キャピラリ清掃工程として、ファーストボンディング工程の制御を利用した例と、セカンドボンディング工程の制御を利用した例を記載したが、ファーストボンディング工程とセカンドボンディング工程の双方の制御を利用したキャピラリ清掃工程を行っても良い。すなわち、前記したようなファーストボンディング工程の制御を利用したキャピラリ清掃工程を行った後、そのまま前記したようなセカンドボンディング工程の制御を利用したキャピラリ清掃工程を行うのである。双方のキャピラリ清掃工程を行うことで、より確実なキャピラリの清掃を行うことができる。   Further, in the present embodiment, as the capillary cleaning process, the example using the control of the first bonding process and the example using the control of the second bonding process are described, but the control of both the first bonding process and the second bonding process is performed. You may perform the capillary cleaning process utilized. That is, after performing the capillary cleaning process using the control of the first bonding process as described above, the capillary cleaning process using the control of the second bonding process as described above is performed as it is. By performing both capillary cleaning steps, the capillary can be more reliably cleaned.

本実施の形態の半導体装置１の製造方法によれば、ワイヤボンディング工程において、ワイヤボンディング（製品組立ての際のワイヤボンディング）が一定条件に到達した場合に、キャピラリ２０を用いて、ヒートステージに設けられたキャピラリ清掃ツール３６上で空ボンディングを行うことで、キャピラリ２０に付着した汚れをキャピラリ清掃ツール３６に転写させることができる。その結果、キャピラリ２０の汚れを清掃して確実なワイヤボンディングを実現することができる。これにより、ワイヤ剥がれ等のボンディング不良を防止して製品の歩留りを向上させることができる。また、ワイヤ剥がれ等のボンディング不良を防止して製品の品質を向上させることができる。また、キャピラリ２０の汚れを清掃することでキャピラリ２０の交換回数を減らし、半導体装置１の製造における製造コストを抑えることができる。また、自動でキャピラリ２０の汚れを清掃することで作業者が手作業でキャピラリ２０の交換を行う等の手間を軽減し、半導体装置１の製造における作業効率を向上させることができる。   According to the manufacturing method of the semiconductor device 1 of the present embodiment, when wire bonding (wire bonding at the time of product assembly) reaches a certain condition in the wire bonding process, the capillary 20 is used to provide the heat stage. By performing the empty bonding on the capillary cleaning tool 36 thus obtained, dirt attached to the capillary 20 can be transferred to the capillary cleaning tool 36. As a result, dirt on the capillary 20 can be cleaned and reliable wire bonding can be realized. As a result, bonding defects such as wire peeling can be prevented and the product yield can be improved. Moreover, bonding defects such as wire peeling can be prevented and the product quality can be improved. In addition, by cleaning dirt on the capillary 20, the number of replacements of the capillary 20 can be reduced, and the manufacturing cost in manufacturing the semiconductor device 1 can be suppressed. In addition, by automatically cleaning the dirt of the capillary 20, it is possible to reduce the trouble of an operator manually replacing the capillary 20, and to improve the work efficiency in manufacturing the semiconductor device 1.

以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

例えば、前記実施の形態では、半導体装置１としてＱＦＰを用いて説明したが、これに限るものではなく、製造過程でワイヤボンディングを行うものであれば、ＱＦＮ等の他のリードフレームタイプの半導体装置や、ＢＧＡ、ＣＳＰ等の基板タイプの半導体装置であっても良い。なお、基板タイプの半導体装置におけるワイヤボンディングでは、半導体チップとベース基板のリード（配線リード、電極）とをワイヤで電気的に接続することになる。   For example, in the above-described embodiment, the QFP is used as the semiconductor device 1. However, the present invention is not limited to this, and other lead frame type semiconductor devices such as QFN may be used as long as wire bonding is performed in the manufacturing process. Alternatively, it may be a substrate type semiconductor device such as BGA or CSP. In the wire bonding in the substrate type semiconductor device, the semiconductor chip and the leads (wiring leads, electrodes) of the base substrate are electrically connected by wires.

また、前記実施の形態では、キャピラリ清掃工程を行うために到達すべきワイヤボンディング工程における一定条件として、キャピラリ２０が行ったボンディング回数が所定回数に達することを挙げていたが、これに限るものではなく、他の条件に応じてキャピラリ清掃工程を行うようになっていても良い。例えば、ワイヤボンダ１０を稼働させた時間が所定時間を超えた場合にキャピラリ清掃工程を行うようになっていても良い。また、ワイヤボンダ１０に、キャピラリ２０の先端の汚れ具合を監視するカメラやセンサ等を設置しておき、当該カメラやセンサの監視に基づき、キャピラリ２０の先端の汚れ具合が一定状態を超えたと判断された場合にキャピラリ清掃工程を行うようになっていても良い。当該監視用のカメラやセンサは、例えば前記したようなキャピラリ清掃工程において汚れが落ちたか否かを検査するためのカメラやセンサと兼用しても良い。   In the above embodiment, the fixed condition in the wire bonding process that should be reached to perform the capillary cleaning process is that the number of bonding performed by the capillary 20 reaches a predetermined number of times. However, the present invention is not limited to this. Alternatively, the capillary cleaning process may be performed according to other conditions. For example, the capillary cleaning process may be performed when the time for operating the wire bonder 10 exceeds a predetermined time. In addition, a camera, a sensor, or the like that monitors the state of contamination at the tip of the capillary 20 is installed in the wire bonder 10, and based on the monitoring of the camera or sensor, it is determined that the state of contamination at the tip of the capillary 20 has exceeded a certain state. In this case, the capillary cleaning process may be performed. The monitoring camera or sensor may also be used as a camera or sensor for inspecting whether dirt has been removed in the capillary cleaning step as described above, for example.

本発明は、半導体チップとリードとをワイヤで接続する半導体装置の製造技術に好適である。   The present invention is suitable for a manufacturing technique of a semiconductor device in which a semiconductor chip and a lead are connected by a wire.

本発明の実施の形態の半導体装置（ＱＦＰ）の構造の一例を示す断面図である。It is sectional drawing which shows an example of the structure of the semiconductor device (QFP) of embodiment of this invention. 図１に示す半導体装置の組み立て手順の一例を示す製造プロセスフロー図である。FIG. 2 is a manufacturing process flow diagram illustrating an example of an assembly procedure of the semiconductor device illustrated in FIG. 1. 本発明の実施の形態のワイヤボンダの構造の一例を示す斜視図である。It is a perspective view which shows an example of the structure of the wire bonder of embodiment of this invention. 図３に示すワイヤボンダのヒートステージの構造の一例を示す拡大平面図である。It is an enlarged plan view which shows an example of the structure of the heat stage of the wire bonder shown in FIG. 図４に示すヒートステージをＡ−Ａ線に沿って切断した構造の一例を示す拡大断面図である。It is an expanded sectional view which shows an example of the structure which cut | disconnected the heat stage shown in FIG. 4 along the AA line. 本実施の形態のワイヤボンディング工程の手順の一例を示す製造プロセスフロー図である。It is a manufacturing process flowchart which shows an example of the procedure of the wire bonding process of this Embodiment. ワイヤボンディング時のヒートステージ等の様子の一例を示す拡大平面図である。It is an enlarged plan view showing an example of a state of a heat stage or the like during wire bonding. 図７に示すヒートステージ等をＢ−Ｂ線に沿って切断した構造の一例を示す拡大断面図である。It is an expanded sectional view which shows an example of the structure which cut | disconnected the heat stage etc. shown in FIG. 7 along the BB line. 本発明の実施の形態のキャピラリ清掃工程の手順の一例を示す製造プロセスフロー図である。It is a manufacturing process flowchart which shows an example of the procedure of the capillary cleaning process of embodiment of this invention. 本発明の実施の形態のキャピラリ清掃工程の手順の他の例を示す製造プロセスフロー図である。It is a manufacturing process flowchart which shows the other example of the procedure of the capillary cleaning process of embodiment of this invention.

符号の説明Explanation of symbols

１ 半導体装置（ＱＦＰ）
２ 封止樹脂部
２ａ 裏面
２ｂ 側面
３ 半導体チップ
３ａ 電極（パッド）
４ リード
４ａ 上面
５ リードフレーム
６ ワイヤ
６ａ ボール
７ タブ（ダイパッド）
８ 吊りリード
１０ ワイヤボンダ
１１ ボンディングヘッド
１２ ＵＳホーン
１３ ワイヤクランパ
１４ ＸＹテーブル
１５ カメラ
１６ フィーダ
２０ キャピラリ（ボンディングツール）
３０ ヒートステージ
３１ 半導体装置搭載エリア
３２ 半導体チップ搭載エリア
３３ タブ逃げ用溝
３４ 吊りリード逃げ用溝
３５ 吸引口
３６ キャピラリ清掃ツール（異物除去シート）
３７ 凹部
３８ メッキ層（金メッキ層）
３９ リードクランパ（リード押さえ）
Ｃ リードフレームの搬送方向 1 Semiconductor device (QFP)
2 Sealing resin part 2a Back surface 2b Side surface 3 Semiconductor chip 3a Electrode (pad)
4 Lead 4a Upper surface 5 Lead frame 6 Wire 6a Ball 7 Tab (die pad)
8 Suspended lead 10 Wire bonder 11 Bonding head 12 US horn 13 Wire clamper 14 XY table 15 Camera 16 Feeder 20 Capillary (bonding tool)
30 Heat Stage 31 Semiconductor Device Mounting Area 32 Semiconductor Chip Mounting Area 33 Tab Escape Groove 34 Suspended Lead Escape Groove 35 Suction Port 36 Capillary Cleaning Tool (Foreign Substance Removal Sheet)
37 Recess 38 Plated layer (gold plated layer)
39 Lead clamper (lead presser)
C Lead frame transport direction

Claims (5)

ボンディングツールであるキャピラリを用いて、ヒートステージ上に配置された半導体チップと前記半導体チップに隣接して配置されたリードとをワイヤで接続するワイヤボンディング工程を有し、
前記ワイヤボンディング工程において、ワイヤボンディングが一定条件に到達した場合に、前記キャピラリを用いて、前記ヒートステージに設けられたキャピラリ清掃ツール上で空ボンディングを行うことで、前記キャピラリに付着した汚れを前記キャピラリ清掃ツールに転写させるキャピラリ清掃工程を有することを特徴とする半導体装置の製造方法。 Using a capillary as a bonding tool, and having a wire bonding step of connecting a semiconductor chip disposed on a heat stage and a lead disposed adjacent to the semiconductor chip with a wire;
In the wire bonding step, when wire bonding reaches a certain condition, by using the capillary, empty bonding is performed on a capillary cleaning tool provided on the heat stage, so that dirt attached to the capillary is removed. A method for manufacturing a semiconductor device, comprising: a capillary cleaning step for transferring to a capillary cleaning tool. 請求項１記載の半導体装置の製造方法において、前記ワイヤボンディング工程において、ワイヤボンディングが一定条件に到達した場合とは、前記キャピラリが行ったボンディング回数が所定回数に達した場合であることを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the wire bonding step, the wire bonding reaches a certain condition when the number of bonding performed by the capillary reaches a predetermined number. A method for manufacturing a semiconductor device. 請求項１記載の半導体装置の製造方法において、前記キャピラリ清掃ツールは、前記ヒートステージの一部に設けられた凹部と、当該凹部に施された金メッキ層とで構成されることを特徴とする半導体装置の製造方法。   2. The semiconductor device manufacturing method according to claim 1, wherein the capillary cleaning tool includes a recess provided in a part of the heat stage, and a gold plating layer applied to the recess. Device manufacturing method. 請求項１記載の半導体装置の製造方法において、前記キャピラリ清掃工程での前記空ボンディングでは、製品組立ての際のワイヤボンディング時よりも超音波出力を大きくしてボンディングを行うことを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the empty bonding in the capillary cleaning step, bonding is performed with a higher ultrasonic output than in wire bonding at the time of product assembly. Manufacturing method. 請求項１記載の半導体装置の製造方法において、前記キャピラリ清掃工程では、前記空ボンディングを行った後で前記キャピラリの汚れ具合を検査し、当該検査で前記キャピラリの汚れが落ちていないと判断された場合には、汚れが落ちるまで前記空ボンディングを行うことを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the capillary cleaning step, after the empty bonding is performed, the contamination of the capillary is inspected, and it is determined that the capillary is not contaminated by the inspection. In such a case, the empty bonding is performed until the dirt is removed.
JP2007107256A 2007-04-16 2007-04-16 Process for manufacturing semiconductor device Pending JP2008270270A (en)

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