KR100949443B1 - A wire bonder having wire tail cutting area and method for wire bonding thereof - Google Patents

A wire bonder having wire tail cutting area and method for wire bonding thereof Download PDF

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KR100949443B1
KR100949443B1 KR1020070120997A KR20070120997A KR100949443B1 KR 100949443 B1 KR100949443 B1 KR 100949443B1 KR 1020070120997 A KR1020070120997 A KR 1020070120997A KR 20070120997 A KR20070120997 A KR 20070120997A KR 100949443 B1 KR100949443 B1 KR 100949443B1
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wire
bonder
semiconductor package
capillary
tail cutting
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KR20090054237A (en
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이원상
손종명
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에스티에스반도체통신 주식회사
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
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Abstract

반도체 패키징 공정중 와이어 본딩 공정에서 잘려진 와이어에 의한 반도체 패키지 내부의 합선(short)을 방지할 수 있는 와이어 본더 및 와이어 본딩방법을 제공한다. 이를 위해 본 발명은 와이어 본더 내부에 있는 윈도우 클램프 위에 와이어 테일 커팅부를 별도로 마련하여 초기 와이어 볼 형성전에 와이어를 커팅한다. 따라서, 잘려진 와이어가 반도체 패키지 내부에 잔류할 수 있는 여지를 제거하여 반도체 패키지 내부에서의 합선을 예방할 수 있다. Provided are a wire bonder and a wire bonding method capable of preventing short circuits in a semiconductor package due to wires cut in a wire bonding process during a semiconductor packaging process. To this end, the present invention provides a separate wire tail cutting portion on the window clamp inside the wire bonder to cut the wire before initial wire ball formation. Therefore, it is possible to prevent the short circuit inside the semiconductor package by removing the possibility that the cut wire may remain inside the semiconductor package.

와이어 본더, 초기 볼 형성, 커팅, 와이어. Wire bonder, initial ball formation, cutting, wire.

Description

와이어 테일 커팅부를 갖는 와이어 본더 및 이를 이용한 와이어 본딩방법{A wire bonder having wire tail cutting area and method for wire bonding thereof}A wire bonder having a wire tail cutting portion and a wire bonding method using the same

본 발명은 반도체 패키지 제조공정에 사용되는 와이어 본딩 장치 및 이를 이용한 와이어 본딩 방법에 관한 것으로, 더욱 상세하게는 캐필러리(capillary)를 사용하는 와이어 본더 및 와이어 본딩 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding apparatus used in a semiconductor package manufacturing process and a wire bonding method using the same, and more particularly, to a wire bonder and a wire bonding method using capillary.

와이어 본딩 장치인 와이어 본더는 반도체 칩의 본딩 패드(bonding pad)와 리드 프레임에 혹은 인쇄회로기판에 있는 인너 리드(inner lead) 혹은 본드 핑거(bond finger)를 와이어, 예컨대 금선(gold wire)으로 연결시키는 반도체 패키지 조립공정에 사용되는 자동화 장치를 말한다.A wire bonder, a wire bonding device, connects a bonding pad and a lead frame of a semiconductor chip to an inner lead or a bond finger on a printed circuit board using a wire, for example, a gold wire. Refers to an automated device used in a semiconductor package assembly process.

일반적으로 반도체 칩을 반도체 패키지용 기본 프레임인 리드프레임(leadframe) 혹은 인쇄회로기판과 연결시키는 방식은, 와이어 본딩을 이용하는 방법 및 반도체 칩의 본딩패드 표면에 범프를 형성하여 곧바로 부착시키는 플립칩 본딩 방식이 있으나, 아직 대부부의 반도체 패키지에서는 와이어 본딩을 통하여 반도체 칩과 반도체 패키지용 기본 프레임을 전기적으로 연결시키고 있는 실정이다.In general, a method of connecting a semiconductor chip with a leadframe or a printed circuit board, which is a basic frame for a semiconductor package, includes a method using wire bonding and a flip chip bonding method in which bumps are formed on a surface of a bonding pad of a semiconductor chip and immediately attached thereto. However, in most semiconductor packages, the semiconductor chip and the base frame for the semiconductor package are electrically connected through wire bonding.

도 1은 종래 기술에 의한 와이어 본더의 윈도우 클램프(window clamp)를 설명하기 위한 사시도이다.1 is a perspective view illustrating a window clamp of a wire bonder according to the prior art.

도 1을 참조하면, 와이어 본더에는 리드프레임에 탑재된 반도체 칩을 고정시킬 수 있는 윈도우 클램프(15)가 존재한다. 상기 윈도우 클램프(15)는 내부에 창(20)이 마련되어 있어, 그 창(20)을 통하여 리드프레임의 인너리드(inner lead)와 반도체 칩을 노출시켜, 캐필러리(capillary)를 이용하여 와이어를 통한 본딩(bonding)을 진행하도록 되어 있다.Referring to FIG. 1, there is a window clamp 15 that can fix a semiconductor chip mounted on a lead frame. The window clamp 15 is provided with a window 20 therein, and exposes the inner lead and the semiconductor chip of the lead frame through the window 20, and uses a capillary to wire Bonding is to proceed through.

한편, 와이어 본딩 공정에 원자재로 사용되는 와이어는 도전성이 높으며 매우 미세한 크기이다. 그러므로 와이어 본딩 공정에서 발생하는 와이어의 일부분이 반도체 패키지 내부에 잔류할 경우, 반도체 패키지 내부에서 합선(short)을 일으킬 수 있기 때문에 반도체 패키지의 전기적 기능에 치명적인 결함으로 작용할 수 있다.On the other hand, the wire used as a raw material in the wire bonding process is highly conductive and very fine size. Therefore, if a part of the wire generated in the wire bonding process remains in the semiconductor package, it may cause a short circuit in the semiconductor package, which may cause a fatal defect in the electrical function of the semiconductor package.

따라서, 와이어 본더의 제조업자나 반도체 패키지 제조업체에서는 이러한 결함을 사전에 방지하기 위하여 와이어 본더를 새롭게 변화시키고, 와이어 본딩방법을 지속적으로 개선해 나가고 있다.Accordingly, manufacturers of wire bonders and semiconductor package manufacturers are continuously changing wire bonders and improving wire bonding methods to prevent such defects in advance.

본 발명이 이루고자 하는 기술적 과제는 와이어 본딩 공정에서 발생한 와이어 찌거기가 반도체 패키지 내부에 잔류할 가능성을 제거할 수 있는 와이어 본더를 제공하는데 있다.An object of the present invention is to provide a wire bonder that can eliminate the possibility that the wire residue generated in the wire bonding process remains in the semiconductor package.

본 발명이 이루고자 하는 다른 기술적 과제는 와이어 본딩 공정에서 발생한 와이어 찌거기가 반도체 패키지 내부에 잔류할 가능성을 제거할 수 있는 와이어 본딩 방법을 제공하는데 있다.Another object of the present invention is to provide a wire bonding method that can eliminate the possibility that the wire residue generated in the wire bonding process remains in the semiconductor package.

상기 기술적 과제를 달성하기 위해 본 발명에 의한 와이어 본더는, 와이어 본더 본체와, 상기 와이어 본더 본체 내부에 설치된 윈도우 클램프 및 상기 윈도우 클램프 내에 설치된 와이어 테일 커팅부를 포함하는 것을 특징으로 한다.In order to achieve the above technical problem, the wire bonder according to the present invention includes a wire bonder body, a window clamp provided in the wire bonder body, and a wire tail cutting part provided in the window clamp.

본 발명의 바람직한 실시예에 의하면, 상기 와이어 테일 커팅부는, 상기 윈도우 클램프 표면에 마련된 도금코팅부 혹은 도금테이프일 수 있으며, 상기 도금의 재질은 와이어와 접착이 용이한 물질로서, 바람직하게는 금-니켈의 합금인 것이 적합하다.According to a preferred embodiment of the present invention, the wire tail cutting portion may be a plating coating or a plating tape provided on the window clamp surface, the material of the plating is a material that is easy to bond with the wire, preferably gold- It is suitable that it is an alloy of nickel.

상기 다른 기술적 과제를 달성하기 위하여 본 발명은, 와이어 본더의 캐필러리(capillary)에 와이어를 끼우는 단계와, 상기 캐필러리 끝단에서 외부로 돌출된 와이어를 상기 와이어 본더 본체의 윈도우 클램프에 마련된 와이어 테일 커팅부에서 절단하는 단계와, 상기 캐필러리의 와이어를 사용하여 반도체 칩의 칩패드에 볼 본드를 형성하는 단계와, 상기 캐필러리의 와이어를 사용하여 반도체 패키지용 기본 프레임에 스티치 본드(stitch bond)를 형성하는 단계를 포함하는 와이어 본딩방법을 제공한다.In order to achieve the above another technical problem, the present invention, the step of inserting a wire into the capillary (capillary) of the wire bonder, the wire protruding outward from the capillary end wire provided in the window clamp of the wire bonder body Cutting at a tail cutting part, forming a ball bond on a chip pad of a semiconductor chip using wires of the capillary, and stitch bonds to a base frame for a semiconductor package using the wires of the capillary It provides a wire bonding method comprising the step of forming a).

본 발명의 바람직한 실시예에 의하면, 상기 반도체 패키지용 기본 프레임은 리드프레임 혹은 인쇄회로기판인 것이 적합하다. According to a preferred embodiment of the present invention, the base frame for the semiconductor package is preferably a lead frame or a printed circuit board.

바람직하게는, 상기 와이어 테일 커팅부는 와이어가 접착이 용이한 물질이 형성된 영역인 것이 적합하다.Preferably, the wire tail cutting portion is preferably a region where the wire is formed of a material that is easy to adhere.

따라서, 상술한 본 발명에 따르면, 초기 와이어 볼을 형성하기 전에 필연적으로 발생하는 와이어 찌거기를 리드프레임이나 인쇄회로기판 위에 방치하지 않고, 반도체 패키지 외부에 있는 와이어 본더의 왼도우 클램프 위에 잔류시켜 와이어 찌꺼기가 반도체 패키지에 잔류하여 합선을 야기하는 문제를 해결할 수 있다. Therefore, according to the present invention described above, the wire residue, which is inevitably generated before the initial wire ball is formed, is left on the left clamp of the wire bonder outside the semiconductor package without leaving the wire residue on the lead frame or the printed circuit board. Can solve the problem of remaining in the semiconductor package causing a short circuit.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 그러나, 아래의 상세한 설명에서 개시되는 실시예는 본 발명을 한정하려는 의미가 아니라, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자에게, 본 발명의 개시가 실시 가능한 형태로 완전해지도록 발명의 범주를 알려주기 위해 제공되는 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments disclosed in the following detailed description are not meant to limit the present invention, but to those skilled in the art to which the present invention pertains, the disclosure of the present invention may be completed in a form that can be implemented. It is provided to inform the category.

도 2는 본 발명의 일 실시예에 의한 와이어 본더 내부의 본딩부를 설명하기 위한 사시도이다.2 is a perspective view illustrating a bonding part inside a wire bonder according to an embodiment of the present invention.

도 2를 참조하면, 와이어 본더(10)는 상호 평행하게 배치된 전후방 레일(11)과, 상기 전후방 레일(11)의 중심부에 상하로 배치된 히터블록(16)과, 윈도우 클램프(15)를 구비한다. 상기 윈도우 클램프(15)는 지지부(13)에 의하여 양단이 지지되어 승강 가능하게 설치된다.Referring to FIG. 2, the wire bonder 10 includes a front and rear rails 11 arranged in parallel with each other, a heater block 16 and a window clamp 15 disposed up and down in the center of the front and rear rails 11. Equipped. Both ends of the window clamp 15 are supported by the support 13 and are installed to be elevated.

따라서 반도체 칩(30)이 탑재된 리드프레임(40)과 같은 가공소재(50)는 상기 전후방 레일(11)에 안내되어 상기 히터블록(16) 위에서 윈도우 클램프(15) 하부에 고정된 채, 와이어 본딩이 수행된다.Therefore, the processing material 50, such as the lead frame 40 on which the semiconductor chip 30 is mounted, is guided to the front and rear rails 11 and fixed to the window clamp 15 under the heater block 16, while being wired. Bonding is performed.

도 3은 본 발명의 바람직한 실시예에 의한 반도체 패키징 공정에서 사용되는 와이어 본더의 왼도우 클램프(window clamp)를 설명하기 위한 사시도이다.3 is a perspective view illustrating a left clamp of a wire bonder used in a semiconductor packaging process according to a preferred embodiment of the present invention.

도 3을 참조하면, 본 발명에 바람직한 실시예에 의한 와이어 본더는, 도 2에 도시된 것과 같은 와이어 본더 본체(10), 상기 와이어 본더 내부에 설치된 윈도우 클램프(15) 및 상기 윈도우 클램프 내에 설치된 와이어 테일 커팅부(wire tail cutting portion, 20)로 이루어진다.Referring to FIG. 3, the wire bonder according to the preferred embodiment of the present invention includes a wire bonder main body 10 as shown in FIG. 2, a window clamp 15 installed in the wire bonder, and a wire installed in the window clamp. A tail tail cutting portion 20.

상기 와이어 테일 커팅부(17)는, 상기 윈도우 클램프(15) 표면에 마련된 도금코팅부 혹은 도금테이프일 수 있으며, 상기 도금의 재질은 와이어와 접착이 용이한 물질로서, 바람직하게는 금-니켈(Au-Ni)의 합금일 수 있다. The wire tail cutting part 17 may be a plating coating part or a plating tape provided on the surface of the window clamp 15. The material of the plating is a material that is easily adhered to the wire, and preferably, gold-nickel ( Au-Ni).

상기 도금 테이프를 이용하여 와이어 테일 커팅부(17)를 설치할 경우, 붙였다 떼어내면서, 와이어 테일 커팅부(17)의 표면 상태를 새롭게 변화시킬 수 있기 때문에 와이어 테일 커팅부(17)의 수명을 보다 오래도록 지속시킬 수 있는 장점이 발생한다.When the wire tail cutting portion 17 is installed using the plating tape, the surface state of the wire tail cutting portion 17 can be newly changed while attaching and detaching, so that the life of the wire tail cutting portion 17 is longer. There is an advantage that can be sustained.

따라서, 와이어 본더를 처음 가동할 때, 캐필러리에 처음 와이어를 끼우고 적절한 크기의 와이어 볼을 형성하기 위하여 수행하는 와이어 커팅을 일반적으로 본딩이 진행될 리드프레임의 리드나, 더미 리드(dummy lead) 혹은 운용자가 지정하는 표시점에서 진행하였다. 이 경우, 잘려진 와이어 찌꺼기가 리드프레임이나 반도체 칩 위에 잔류하여 반도체 패키지 내부에서 합선을 일으키는 원인으로 작용하 였다.Therefore, when the wire bonder is first operated, wire cutting, which is performed to first insert the wire into the capillary and form a wire ball of an appropriate size, generally leads to a lead frame or a dummy lead or Progress was made at the marking point designated by the operator. In this case, the cut wire residue remained on the leadframe or the semiconductor chip, causing short circuits in the semiconductor package.

그러나, 본 발명에서는 초기 와이어 볼 형성을 위한 와이어 커팅을 와이어 본더에 있는 왼도우 클램프(15)의 와이어 테일 커팅부(17)에서 수행함으로 말미암아 잘려진 와이어 찌꺼기가 반도체 패키지 내부로 들어갈 수 있는 것을 방지하기 때문에 신뢰성이 높은 와이어 본딩을 구현할 수 있다.However, in the present invention, wire cutting for initial wire ball formation is performed at the wire tail cutting portion 17 of the left clamp 15 in the wire bonder to prevent the wire debris from entering the semiconductor package. As a result, highly reliable wire bonding can be realized.

도 4 내지 도 11은 본 발명의 바람직한 실시예에 의한 반도체 패키징 공정의 와이어 본딩방법을 설명하기 위한 단면도들이다.4 to 11 are cross-sectional views illustrating a wire bonding method of a semiconductor packaging process according to a preferred embodiment of the present invention.

도 4 내지 도 11을 참조하면, 먼저 와이어 본더를 처음 가동할 때, 캐필러리(60)에 와이어(70)를 처음 끼우면 캐필러리 끝단(62)에서 외부로 돌출되는 와이어(70)의 길이(L)는 매번 달라진다. 그러나 처음 와이어 볼(도7의 72) 형성을 위해 필요로 하는 와이어(70)의 길이는 일정하기 때문에, 그 일정한 길이를 확보하기 위하여 와이어 테일에 대한 커팅을 실시한다. 4 to 11, when the wire bonder is first operated, when the wire 70 is first inserted into the capillary 60, the length of the wire 70 protrudes outward from the capillary end 62. (L) is different each time. However, since the length of the wire 70 required for forming the first wire ball (72 of FIG. 7) is constant, the wire tail is cut to secure the constant length.

본 발명에서는 도 4와 같이 윈도우 클램프(15)의 표면에 마련된 왼도우 테일 커팅부(17)에서 처음 와이어 볼 형성을 위한 커팅을 실시한다. 이에 따라 와이어 찌꺼기(18)가 리드프레임이나 반도체 칩 위에 잔류하지 않고, 와이어 본더에 있는 윈도우 클램프 위에 잔류한다. 그리고 캐필러리(60)는 전기적 스파크를 발생시키는 영역(66)으로 이동하여 와이어 볼(72)을 도 5와 같이 형성한다. 이에 따라 일정한 크기를 갖는 와이어 볼(72)이 형성되어 반도체 칩에 있는 본딩패드(80)로 도6 내지 도 8과 같이 볼 본드(74, 76)를 형성한다. In the present invention, as shown in FIG. 4, the left tail cutting unit 17 provided on the surface of the window clamp 15 performs cutting for the first wire ball formation. As a result, the wire dregs 18 do not remain on the leadframe or the semiconductor chip, but remain on the window clamp in the wire bonder. In addition, the capillary 60 moves to an area 66 that generates an electrical spark to form a wire ball 72 as shown in FIG. 5. Accordingly, a wire ball 72 having a predetermined size is formed to form ball bonds 74 and 76 using the bonding pads 80 of the semiconductor chip as shown in FIGS. 6 to 8.

그 후 캐필리리(60)는 리드프레임의 인너리드(90) 위로 이동하여 와이 어(70)를 끊으면서 스티치 본드(78)를 형성한 후, 도 11과 같이 다시 전기적 스파크를 일으키는 영역(66)으로 이동하여 일정한 크기의 와이어 볼(72)을 형성하는 공정을 반복하게 된다.Thereafter, the capillary 60 moves over the inner lead 90 of the leadframe to form the stitch bond 78 while cutting off the wire 70, and then again causes an electrical spark as shown in FIG. ) To repeat the process of forming a wire ball 72 of a constant size.

한편, 반도체 패키지가 BGA(Ball Grid Array) 패키지인 경우, 상기 리드프레임 대신에 인쇄회로기판을 사용할 수 있으며, 이때는 스티치 본드(78)가 형성되는 지점이 인쇄회로기판에 마련된 본드 핑거(bond finger)가 될 수 있다.On the other hand, when the semiconductor package is a ball grid array (BGA) package, a printed circuit board may be used instead of the lead frame. In this case, a bond finger having a point where the stitch bond 78 is formed is provided on the printed circuit board. Can be

본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

도 1은 종래 기술에 의한 와이어 본더의 윈도우 클램프(window clamp)를 설명하기 위한 사시도이다.1 is a perspective view illustrating a window clamp of a wire bonder according to the prior art.

도 2는 본 발명의 일 실시예에 의한 와이어 본더 내부의 본딩부를 설명하기 위한 사시도이다.2 is a perspective view illustrating a bonding part inside a wire bonder according to an embodiment of the present invention.

도 3은 본 발명의 바람직한 실시예에 의한 반도체 패키징 공정에서 사용되는 와이어 본더의 왼도우 클램프(window clamp)를 설명하기 위한 사시도이다.3 is a perspective view illustrating a left clamp of a wire bonder used in a semiconductor packaging process according to a preferred embodiment of the present invention.

도 4 내지 도 11은 본 발명의 바람직한 실시예에 의한 반도체 패키징 공정의 와이어 본딩방법을 설명하기 위한 단면도들이다.4 to 11 are cross-sectional views illustrating a wire bonding method of a semiconductor packaging process according to a preferred embodiment of the present invention.

Claims (9)

와이어 본더 본체;Wire bonder body; 상기 와이어 본더 본체 내부에 설치된 윈도우 클램프; 및A window clamp installed inside the wire bonder body; And 상기 윈도우 클램프 내에 설치되고 금-니켈의 합금으로 된 도금테이프로 이루어진 와이어 테일 커팅부를 포함하는 것을 특징으로 하는 와이어 본더.And a wire tail cutting portion formed in the window clamp and made of a plating tape made of an alloy of gold-nickel. 삭제delete 삭제delete 삭제delete 삭제delete 와이어 본더의 캐필러리(capillary)에 와이어를 끼우는 단계;Inserting the wire into the capillary of the wire bonder; 상기 캐필러리 끝단에서 외부로 돌출된 와이어를 상기 와이어 본더 본체의 윈도우 클램프에 마련되고 금-니켈의 합금으로 된 도금테이프로 이루어진 와이어 테일 커팅부에서 절단하는 단계;Cutting the wire protruding from the end of the capillary at a wire tail cutting part provided in a window clamp of the wire bonder body and made of a plating tape made of a gold-nickel alloy; 상기 캐필러리의 와이어를 사용하여 반도체 칩의 칩패드에 볼 본드를 형성하는 단계; 및Forming a ball bond on a chip pad of a semiconductor chip using the wire of the capillary; And 상기 캐필러리의 와이어를 사용하여 반도체 패키지용 기본 프레임에 스티치 본드(stitch bond)를 형성하는 단계를 포함하는 와이어 본딩방법.And forming a stitch bond in the base frame for the semiconductor package by using the wire of the capillary. 제6항에 있어서, The method of claim 6, 상기 반도체 패키지용 기본 프레임은 리드프레임인 것을 특징으로 하는 와이어 본딩방법.The base frame for a semiconductor package is a wire bonding method, characterized in that the lead frame. 제6항에 있어서, The method of claim 6, 상기 반도체 패키지용 기본 프레임은 인쇄회로기판인 것을 특징으로 하는 와이어 본딩방법.The base frame for a semiconductor package is a wire bonding method, characterized in that the printed circuit board. 삭제delete
KR1020070120997A 2007-11-26 2007-11-26 A wire bonder having wire tail cutting area and method for wire bonding thereof KR100949443B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050065248A (en) * 2003-12-23 2005-06-29 삼성전자주식회사 Wire bonding apparatus and method for forming auto ball using the same
JP2006202941A (en) * 2005-01-20 2006-08-03 Seiko Instruments Inc Wire bonder apparatus and its usage

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050065248A (en) * 2003-12-23 2005-06-29 삼성전자주식회사 Wire bonding apparatus and method for forming auto ball using the same
JP2006202941A (en) * 2005-01-20 2006-08-03 Seiko Instruments Inc Wire bonder apparatus and its usage

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