JPH11154391A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device which can perform common access with different bit width. SOLUTION: A memory cell array 27 is divided into plural region corresponding to bit width and word depth of plural arithmetic processing parts accessing a storage device 20. A storage circuit 21 outputs a signal WD in accordance with a signal BW of bit width and word depth of a storage region to which each arithmetic processing unit accesses to an address mapping circuit 24. An address multiplexer 22 selects address signals AD11-AD13 of the arithmetic processing section accessing the storage device 20. The address mapping circuit 24 inputs an address signal AD through an address input buffer 23, and converts the address signal AD to an internal address signal based on the signal BW and the signal WD. A X decoder 28 and a Y decoder 29 decode the internal address signal and select the prescribed memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a storage device used for storing various data.

[0002]

2. Description of the Related Art FIG. 11 shows a schematic configuration of a conventional system for performing arithmetic processing. The system 60 includes logic circuits 61 and 62 for performing arithmetic processing and an MPU 63. The logic circuits 61 and 62 and the MPU 63 use a storage device including a memory such as a DRAM or an SRAM as a data storage unit for reading data used for the arithmetic processing and storing the processed data. In general, the bit widths of the data used by the plurality of logic circuits 61 and 62 and the MPU 63 for the calculation are often different, and dedicated storage devices 64 and 65 having the bit widths of the data used so that each can be easily used. , 66 are used. Therefore, usually, separate memory devices 64, 65, and 66 having different bit widths are required to configure the system 60. When the system 60 is configured on a motherboard, a plurality of semiconductor packages are required. When a system is configured on an LSI, a plurality of storage devices are required.

[0003]

However, having the above-mentioned storage devices separately requires a plurality of semiconductor packages to be mounted on the motherboard when the system 60 is configured on the motherboard. ,
This causes an increase in power consumption and an increase in cost. Also, L
When a system is configured on the SI, a required number of different storage devices having a required bit width and capacity are designed as many as necessary, which causes an increase in development period and an increase in cost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to enable a common access with different bit widths, thereby shortening the development period and reducing the cost. It is to provide a storage device.

[0005]

In order to achieve the above object, according to the present invention, a storage means having a predetermined storage capacity and an address designated based on bit width information of an access signal are stored. The gist of the present invention is a storage device including an address mapping means for mapping to an internal address of the storage means.

According to a second aspect of the present invention, based on a storage means having a predetermined storage capacity, an address designated based on bit width information and used capacity information of an access signal is mapped to an internal address of the storage means. The gist is a storage device including an address mapping unit.

According to a third aspect of the present invention, in the storage device according to the second aspect, the storage area is divided in advance based on the used capacity information of a plurality of types of access signals, and the address mapping means Is to convert the specified address into its internal address in accordance with the divided storage area of the storage means.

[0008] The invention described in claim 4 is the invention according to claim 2 or 3.
The gist of the storage device described in (1) is that it further includes an address switching means for selectively taking in each address information of a plurality of types of access signals.

According to a fifth aspect of the present invention, in the storage device according to any one of the second to fourth aspects, input data switching means for selectively inputting input data corresponding to a plurality of types of access signals is further provided. The point is to prepare.

According to a sixth aspect of the present invention, in the storage device according to any one of the second to fifth aspects, output data switching means for selectively outputting output data corresponding to a plurality of types of access signals is provided. The point is to provide further.

According to a seventh aspect of the present invention, in the storage device according to any one of the first to sixth aspects, the storage means comprises:
A plurality of memory cell blocks corresponding to a minimum bit width of an access signal, and an XY decoder for individually accessing each unit cell of the plurality of memory cell blocks based on an mapped internal address. Is the gist.

According to an eighth aspect of the present invention, in the storage device according to the first aspect, a storage circuit for storing bit width information of an access signal and outputting the bit width information to an address mapping means; Address input means for holding the address information and outputting it to the address mapping means, data input means for capturing input data corresponding to the access signal, and data output means for outputting data corresponding to the access signal. Make a summary.

According to a ninth aspect of the present invention, in the storage device according to the fourth aspect, the bit width information and the used capacity information of the access signal are stored, and the bit width information and the used capacity information are output to the address mapping means. Memory circuit
An address input unit that holds the address information captured by the address switching unit and outputs the address information to the address mapping unit.

According to a tenth aspect of the present invention, in the storage device according to the second or third aspect, the bit width information and the used capacity information of the access signal are stored, and the bit width information and the used capacity information are stored in the address mapping means. A storage circuit that outputs address data of an access signal to an address mapping unit; and an input data switching unit that selectively takes in input data corresponding to a plurality of types of access signals. And output data switching means for selectively outputting output data corresponding to the access signal.

According to an eleventh aspect of the present invention, in the storage device of the fourth aspect, address input means for holding the address information fetched by the address switching means and outputting the address information to the address mapping means; The gist of the invention is to provide input data switching means for selectively taking in input data corresponding to a signal and output data switching means for selectively outputting output data corresponding to a plurality of types of access signals.

According to a twelfth aspect of the present invention, in the storage device according to the eleventh aspect, the bit width information and the used capacity information of the access signal are stored, and the bit width information and the used capacity information are output to the address mapping means. The gist of the present invention is to further include a storage circuit for performing the above.

According to a thirteenth aspect of the present invention, in the storage device according to the second or third aspect, the bit width information and the used capacity information of the access signal are stored, and the bit width information and the used capacity information are stored in the address mapping means. A memory circuit that outputs the address information of a plurality of types of access signals; and an address mapping unit that selectively captures each piece of address information of the plurality of types of access signals held by the address input unit. Address switching means for outputting, input data switching means for selectively capturing input data corresponding to a plurality of access signals, output data switching means for selectively outputting output data corresponding to a plurality of access signals, The point is to provide

[0018]

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 4 shows a schematic configuration of a system using the storage device of the present embodiment. The system 10 includes logic circuits 11 and 12 and an MPU 13 as operation processing units.
One storage device 20 is provided as data storage means for reading data used by the logic circuits 11 and 12 and the MPU 13 for operation processing, and writing data subjected to operation processing. In the present embodiment, the logic circuits 11 and 12
And the bit width of the data used by the MPU 13 for the calculation is different from each other. For example, the logic circuit 11 uses 8-bit data Di11 and Do11, the logic circuit 12 uses 16-bit data Di12 and Do12, and the MPU 13 uses the 24-bit data Di1.
3, Do13. Also, the logic circuit 11
Is an address signal AD for accessing the storage device 20.
11, the logic circuit 12 outputs an address signal AD12 to access the storage device 20, and the MPU 13
Is an address signal AD for accessing the storage device 20.
12 is output. The storage device 20 enables access with different bit widths, such as 8-bit width, 16-bit width, and 24-bit width, and different word depths (capacities).

When any of the arithmetic processing units (the logic circuits 11 and 12 and the MPU 13) accesses the storage device 20, the MPU 13 outputs a selection signal SL corresponding to the arithmetic processing unit to the storage device 20 and accesses the storage device 20. The information of the arithmetic processing unit that is present is given to the storage device 20. In the present embodiment, the selection signals SL1 and SL1 correspond to the logic circuits 11 and 12, respectively.
SL2 is output and the selection signal SL corresponding to the MPU 13 is output.
3 is output.

Next, the storage device 20 will be described in detail with reference to FIGS. The storage device 20 is, for example, a DRAM
(Dynamic Random Access Memory), a storage circuit 21 having a register and its write circuit, an address multiplexer 22 as address switching means, an address input buffer 23 as address input means, and an address mapping circuit 2 as address mapping means
4, a data input multiplexer 25 as input data switching means, a data output multiplexer 26 as output data switching means, a memory cell array 27 as storage means, an X decoder 28, a Y decoder 29 and a sense amplifier 30.

As shown in FIG. 2, the memory cell array 27
Is divided into a plurality of (four in the present embodiment) blocks 31 to 34. Each of the blocks 31 to 34 includes a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and is capable of inputting and outputting data having a predetermined bit width (8 bit width in this embodiment). Each of the blocks 31 to 34 has a bit width and a word depth (capacity) of the logic circuits 11 and 12 and the MPU 13 (FIG. 4) for accessing the storage device 20.
Corresponding to three regions 311 to 313 and 321 respectively.
To 323, 331 to 333, and 341 to 343 are set.

The storage circuit 21 shown in FIG.
After the power is turned on, the bit width information and the word depth information of the storage area accessed by the arithmetic processing units (the logic circuits 11 and 12 and the MPU 13) are written from the MPU 13 and the like according to a certain protocol. Then, the storage circuit 21 outputs to the address mapping circuit 24 a signal BW indicating a bit width and a signal WD indicating a word depth (capacity) corresponding to an area accessed by each arithmetic processing unit (the logic circuits 11, 12 and the MPU 13). I do.

The address multiplexer 22 is an arithmetic processing unit (logic circuits 11, 1) accessing the storage device 20.
2 and MPU 13), based on selection signals SL (SL1 to SL3) output from MPU 13, address signals AD (AD11 to AD1) corresponding to the arithmetic processing unit.
Select 3).

The address input buffer 23 holds the address signal AD selected by the address multiplexer 22 and outputs it to the address mapping circuit 24. The address mapping circuit 24 includes an address input buffer 23
Signal AD (external address signal) input from
With the signals BW and WD output from the storage circuit 21
Is converted to an internal address signal based on This is because each arithmetic processing unit (the logic circuits 11, 12 and the MPU 13) outputs the address signal AD using the storage device 20 as one independent storage device. That is, the logic circuit 1
The address signal AD11 of 1 is from address 0 to the word depth, and the address signal AD12 of the logic circuit 12 is also 0.
From address to its word depth, and MPU1
The address signal AD13 of No. 3 also extends from address 0 to its word depth. However, as the address space in the storage device 20, as shown in FIG. 3, addresses from address 0 ($ 0) to addresses corresponding to the used capacity ($ xxxx) are used. Therefore, it is necessary for the storage device 20 to perform conversion to an internal address assigned to an access area set for each arithmetic processing unit.

For example, if the logic circuit 12 accesses the storage device 20 and the external address signal AD12 output from the logic circuit 12 is at address 0, then
Inside the storage device 20, an address uniquely determined by the bit width and the word depth of the areas 311, 321, 331, 341 used by the logic circuit 11 is added to the external address, and the internal address is shown in FIG. ♯aaaa.

If the external address signal AD13 output from the MPU 13 is at address 0 when the MPU 13 accesses the storage device 20, in this case, in the storage device 20, the area 31 used by the logic circuit 11 is used.
An address uniquely determined by the bit width and the word depth of 1,321,331,341, and an address uniquely determined by the bit width and the word depth of the regions 312,322,332,342 used by the logic circuit 12 Is added to the external address, and the internal address is {bbb} also shown in FIG.
b.

The X decoder 28 and the Y decoder 29 decode internal address signals output from the address mapping circuit 24 and select predetermined memory cells of the blocks 31 to 34. Therefore, for example, when the logic circuit 11 accesses the storage device 20, the logic circuit 11 uses 8-bit width data.
1 in the regions 311, 321, 331, and 341 shown in FIG.
Only one area is selected. In this case, the address signal A
As D11 is incremented, for example, areas are selected in order from the head area of areas 311, 321, 331, and 341.

When the logic circuit 12 accesses the storage device 20, since the logic circuit 12 uses 16-bit width data, each of the areas 312 and 322 shown in FIG. Alternatively, one region in each of the regions 332 and 342 is selected. In this case, as the address signal AD12 is incremented, for example, the area 312 and the area 322
And the region 332 and the region 342 are sequentially selected from the head region of each region.

Further, when the MPU 13 accesses the storage device 20, since the MPU 13 uses 24-bit data, the MPU 13 uses one of the four areas 313, 323, 333 and 343 shown in FIG. One of each of the three regions is selected. In this case, when the address signal AD13 is at address 0, for example, first, three areas 313A, 323A, and 333A are selected, and when the address signal AD13 is incremented, the areas 343A, 313B, and 323B are selected.
Thereafter, as the address signal AD13 is incremented, the area 333B, 343B, 313C, and the area 3
Three regions are sequentially selected like 23C, 333C, and 343C.

Also, the sense amplifier 30 shown in FIG. 1 amplifies the data of the selected memory cell and outputs it to the data output multiplexer 26 when reading the data. The data output multiplexer 26 controls the selection signal SL output from the MPU 13 when reading data.
Arithmetic processing unit (logic circuit 1) corresponding to (SL1 to SL3)
1, 12 and the MPU 13) and select the sense amplifier 30
Are output as output data Do11 to Do13 to the selected processing unit.

The data input multiplexer 25 selects an arithmetic processing unit (logic circuits 11, 12 and MPU 13) corresponding to the selection signals SL (SL1 to SL3) output from the MPU 13 at the time of writing data, and selects the selected processing unit. Write data Di11 to Di1 corresponding to the arithmetic processing unit
Import 3

Next, the system 1 configured as described above
The operation of accessing the storage device 20 at 0 will be described. First, after the power supply to the storage device 20 is turned on, the arithmetic processing unit (the logic circuits 11 and 12 and the MP
The bit width information and the word depth information of the storage area accessed by U13) are written by MPU13.
As a result, from the storage circuit 21, each operation processing unit (logic circuit 1)
A signal BW indicating a bit width and a signal WD indicating a word depth (capacity) corresponding to a region where the MPU 13 accesses the memory cell array 27 are output to the address mapping circuit 24.

Next, for example, the logic circuit 11
When an access signal is output for 0, the selection signal SL1 corresponding to the logic circuit 11 is output from the MPU 13 to the address multiplexer 22, the address mapping circuit 24, the data input multiplexer 25, and the data output multiplexer 26.

The address multiplexer 22 outputs a selection signal S
The address signal AD11 output from the logic circuit 11 is selected and taken in based on L1.
11 is held in the address input buffer 23 and output to the address mapping circuit 24.

The address mapping circuit 24 outputs a selection signal S
Based on L1, the address signal AD11 is stored in the storage circuit 2
1 is converted into an internal address signal corresponding to the signal BW and the signal WD output from the signal 1. In this case, the address signal A
D11 is directly converted to an internal address signal.

The X decoder 28 and the Y decoder 29 decode the internal address signal (address signal AD11) output from the address mapping circuit 24 and block 3
1 to 34 predetermined memory cells are selected. In this case, the regions 311, 321, 33 are based on the internal address signal.
1, the memory cells in one area are selected. As the address signal AD11 is incremented, the areas 311A, 321A, 331A, 341
A, 321B, 331B...

At the time of reading data, the data of the selected memory cell is amplified by the sense amplifier 30. Then, the data output multiplexer 26 selects the logic circuit 11 corresponding to the selection signal SL1, and the output data of the sense amplifier 30 is output to the logic circuit 11 as the output data Do11.

When writing data, the data input multiplexer 25 selects the write data Di11 of the logic circuit 11 based on the selection signal SL1 and selects the write data Di11 for the storage device 20.
Take in. The fetched write data Di11 is written to a memory cell in an area selected by the X decoder 28 and the Y decoder 29.

When the logic circuit 12 outputs an access signal to the storage device 20, the MPU 13 outputs a selection signal SL2 corresponding to the logic circuit 12 to the address multiplexer 22, the address mapping circuit 24, the data input multiplexer 25, and the data output multiplexer 25. Output to the multiplexer 26.

The address multiplexer 22 outputs a selection signal S
Based on L2, an address signal AD12 output from the logic circuit 12 is selected and taken in.
12 is held in the address input buffer 23 and output to the address mapping circuit 24.

The address mapping circuit 24 selects the selection signal S
Based on L2, the address signal AD12 is stored in the storage circuit 2
1 is converted into an internal address signal corresponding to the signal BW and the signal WD output from the signal 1. In this case, the storage device 20
, Regions 311, 321, 3 used by the logic circuit 11 for an external address (address signal AD12)
By adding addresses uniquely determined by the bit widths and word depths of the bits 31 and 341, the addresses are converted to internal addresses. Therefore, the internal address corresponding to the address 0 of the address signal AD12 is $ aaa.

The X decoder 28 and the Y decoder 29 decode internal address signals output from the address mapping circuit 24 and select predetermined memory cells of the blocks 31 to 34. In this case, since the logic circuit 12 uses data having a width of 16 bits, one of the four areas 313, 323, 333, and 343 is selected based on the internal address. And
When the address signal AD12 is at address 0, first, the memory cells in the two areas 312A and 322A are selected.
As the address signal AD12 is incremented, the areas 332A and 342A and the areas 312B and 322
B, memory cells in two regions are sequentially selected as in regions 332B and 342B.

At the time of reading data, the data of the selected memory cell is amplified by the sense amplifier 30. Then, the data output multiplexer 26 selects the logic circuit 12 corresponding to the selection signal SL2, and the output data of the sense amplifier 30 is output to the logic circuit 12 as the output data Do12.

At the time of data writing, the data input multiplexer 25 selects the write data Di12 of the logic circuit 12 based on the selection signal SL2, and
Take in. The fetched write data Di12 is written to the memory cells in the area selected by the X decoder 28 and the Y decoder 29.

Further, when the MPU 13 outputs an access signal to the storage device 20, the MPU 13
The selection signal SL3 corresponding to 13 is output to the address multiplexer 22, the address mapping circuit 24, the data input multiplexer 25, and the data output multiplexer 26.

The address multiplexer 22 outputs a selection signal S
Based on L3, an address signal AD13 output from the MPU 13 is selected and taken in.
3 is held in the address input buffer 23 and output to the address mapping circuit 24.

The address mapping circuit 24 selects the selection signal S
Based on L3, the address signal AD13 is stored in the storage circuit 2
1 is converted to an internal address signal corresponding to the signal BW and the signal WD input from the input terminal 1. In this case, the storage device 20
, Regions 311, 321, 3 used by the logic circuit 11 for an external address (address signal AD13)
Addresses uniquely determined by the bit widths and word depths of the bits 31 and 341 and the areas 312 and 3 used by the logic circuit 12
The address is converted into an internal address by adding an address uniquely determined by the bit width of 22, 332, 342 and the word depth. Therefore, the internal address corresponding to address 0 of the address signal AD13 is $ bbbb.

The X decoder 28 and the Y decoder 29 decode internal address signals output from the address mapping circuit 24 and select predetermined memory cells of the blocks 31 to 34. In this case, since the MPU 13 uses data of a 24-bit width, one of each of the three areas 313, 323, 333, and 343 is selected based on the internal address. When the address signal AD13 is at address 0, first, the memory cells in the three areas 313A, 323A, and 333A are selected. As the address signal AD13 is incremented, the areas 343A, 313B, 323B, the areas 333B, 343B, 313C, and the areas 323C, 333
Memory cells in three regions are sequentially selected as in C and 343C.

At the time of reading data, the data of the selected memory cell is amplified by the sense amplifier 30. Then, the data output multiplexer 26 selects the MPU 13 corresponding to the selection signal SL3, and outputs the output data of the sense amplifier 30 as the output data Do13.
3 is output.

At the time of writing data, the data input multiplexer 25 outputs the MP signal based on the selection signal SL3.
The write data Di13 of U13 is selected and taken into the storage device 20. The fetched write data Di13 is written to a memory cell in an area selected by the X decoder 28 and the Y decoder 29.

As described in detail above, according to the storage device of the present embodiment, the following effects can be obtained. -The memory cell array 27 is divided into four blocks 31 to 34, and the logic circuits 11, 12 and the MPU 1 that access the memory cell array 27 with respect to each of the blocks 31 to 34.
3 areas 311 to 313, 321 to 323, and 331 corresponding to a bit width and a word depth (capacity) of 3 respectively.
333, 341-343 were set. Then, the address signals AD11,
AD12 and AD13 are connected to logic circuits 11 and 12 and MPU1.
3 is provided with an address mapping circuit 24 for converting to an internal address signal based on the bit width and word depth (capacity) of the area to be accessed, and the logic circuits 11, 1
2 and a data input multiplexer 25 for selectively inputting bit width data used by the MPU 13 and a data output multiplexer 26 for selectively outputting data.
Therefore, a plurality of bit widths and capacities can be simultaneously realized in one storage device 20.
It is possible to reduce the cost by suppressing the size of the system 10 using, and to shorten the development period.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. In order to avoid redundant description, the same elements as those described in FIG. 1 are denoted by the same reference numerals.

The storage device 40 of the present embodiment is also used for the system 10 (FIG. 4) of the first embodiment. The storage device 40 is different from the configuration of the storage device 20 in that an address input buffer 23 is provided in a preceding stage and an address multiplexer 22 is provided in a following stage. The address input buffer 23 is provided in the logic circuit 1
1, 12 and the address signal A input from the MPU 13
D11, AD12, and AD13, and these address signals AD11 to AD13 are transferred to the address multiplexer 2
Output to 2. The address multiplexer 22 responds to an arithmetic processing unit accessing the storage device 40 based on a selection signal SL (SL1 to SL3) output from the MPU 13 to generate an address signal AD (AD) corresponding to the arithmetic processing unit.
11 to AD13).

With the storage device 40 of the present embodiment configured as described above, the same effects as those of the storage device 20 of the first embodiment can be obtained. (Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. In order to avoid redundant description, the same elements as those described in FIG. 1 are denoted by the same reference numerals.

The storage device 42 of the present embodiment is also used for the system 10 (FIG. 4) of the first embodiment. The storage device 42 omits the storage circuit 21 in the storage device 20 of the first embodiment, and outputs a signal of bit width information of a storage area accessed by an arithmetic processing unit (logic circuits 11, 12 and the MPU 13) from outside the storage device 42. The WD and the word depth information signal BW are directly input to the address mapping circuit 24.

With the storage device 42 of the present embodiment configured as described above, the same effects as those of the storage device 20 of the first embodiment can be obtained. In addition, the storage device 42 can be reduced in size by omitting the storage circuit 21.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. In order to avoid redundant description, the same elements as those described in FIG. 1 are denoted by the same reference numerals.

The storage device 44 of this embodiment is also used for the system 10 (FIG. 4) of the first embodiment. In the storage device 44, the address multiplexer 22 in the storage device 20 of the first embodiment is omitted, and any one of the address signals AD11 to AD13 of the arithmetic processing units (the logic circuits 11, 12 and the MPU 13) is provided outside the storage device 44. And the address signal AD is directly input to the address input buffer 23.

With the storage device 44 of the present embodiment configured as described above, the same effects as those of the storage device 20 of the first embodiment can be obtained. Further, the storage device 44 can be downsized by the amount of omitting the address multiplexer 22.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to FIG. In order to avoid redundant description, the same elements as those described in FIG. 1 are denoted by the same reference numerals.

The storage device 46 of this embodiment is also used for the system 10 (FIG. 4) of the first embodiment. In the storage device 46, the data input multiplexer 25 and the data output multiplexer 26 in the storage device 20 of the first embodiment are omitted, and an external circuit has the function.

With the storage device 46 of the present embodiment configured as described above, the same effects as those of the storage device 20 of the first embodiment can be obtained. In addition, the storage device 46 can be reduced in size by omitting the data input multiplexer 25 and the data output multiplexer 26.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described with reference to FIGS. In order to avoid redundant description, the same elements as those described in FIG. 1 are denoted by the same reference numerals.

One storage device 48 according to the present embodiment is provided for one arithmetic processing unit constituting the system. FIG.
As shown in the figure, the storage device 48 is composed of a DRAM, a storage circuit 49 having a register and its write circuit, an address input buffer 23, an address mapping circuit 50 as address mapping means, a data input buffer 51 as data input means, It comprises a data output buffer 52 as data output means, a memory cell array 53 as storage means, an X decoder 28, a Y decoder 29 and a sense amplifier 30.

As shown in FIG. 10, the memory cell array 5
3 is a plurality (four in this embodiment) of blocks 54 to 57
Is divided into Each of these blocks 54 to 57 has a plurality of areas that can input and output data having a predetermined bit width (8 bit width in this embodiment).

After the power of the storage device 48 is turned on, information on the bit width of the data used by the arithmetic processing unit accessing the storage device 48 is written into the storage circuit 49 from an MPU or the like (not shown) by a predetermined protocol. Then, the storage circuit 49 outputs a signal BW indicating the bit width to the address mapping circuit 50.

The address input buffer 23 is provided in the storage device 4
8 holds the address signal AD input from the arithmetic processing unit for accessing the address 8 and outputs the address signal AD to the address mapping circuit 50. The address mapping circuit 50 converts the address signal AD input from the address input buffer 23 into the storage circuit 4
9 is mapped to an internal address signal based on the signal BW input from.

X decoder 28 and Y decoder 29 decode the internal address signal output from address mapping circuit 50 and select a predetermined memory cell of memory cell array 53. Therefore, when the bit width signal BW is an 8-bit width signal, only one area in the blocks 54, 55, 56, 57 is selected based on the internal address. In this case, as the address signal AD (internal address) is incremented, the block 5
4, 55, 56, and 57 are selected in order from the first area. When the bit width signal BW is a 16-bit width signal, one area in each of the blocks 54 and 55 or one area in each of the blocks 56 and 57 is selected based on the internal address. In this case, as the address signal AD (internal address) is incremented, blocks are selected in order from the first area of the blocks 54 and 55 and the blocks 56 and 57. If the bit width signal BW is a 24-bit width signal, the four blocks 54, 5
One region in each of the three blocks is selected from 5, 56, and 57. In this case, the address signal A
When D (internal address) is address 0, first, three areas 54A, 55A, 56A are selected, and when the address signal AD is incremented, the areas 57A, 54B,
55B is selected. Thereafter, as the address signal AD is incremented, the areas 56B, 57B, 54
Three regions are sequentially selected, such as C, regions 55C, 56C, and 57C. Further, when the bit width signal BW is a signal having a 32-bit width, 4 bits are output based on the internal address.
One area in each of the blocks 54, 55, 56, and 57 is sequentially selected.

At the time of data reading, sense amplifier 30 amplifies the data of the selected memory cell and outputs it to data output multiplexer 26. The data output buffer 52 outputs the output data of the sense amplifier 30 as the output data Do when reading the data.

The data input buffer 51 takes in write data Di input from the outside (arithmetic processing unit) when writing data. Next, an access operation to the storage device 48 configured as described above will be described.

First, after the power to the storage device 48 is turned on, information on the bit width of the data used by the arithmetic processing unit is written into the storage circuit 49 by the MPU or the like. as a result,
A signal BW indicating a bit width is output from storage circuit 49 to address mapping circuit 50.

Next, the address signal AD from the arithmetic processing unit
Is input, the address signal AD is held in the address input buffer 23 and output to the address mapping circuit 50.

Address mapping circuit 50 maps address signal AD to an internal address signal based on signal BW. The address signal AD is directly mapped to the internal address signal in the above-described manner.

The X decoder 28 and the Y decoder 29 decode the internal address signal (address signal AD) output from the address mapping circuit 50, and
57 predetermined memory cells are selected.

At the time of reading data, the data of the selected memory cell is amplified by the sense amplifier 30. The output data of the sense amplifier 30 is output as output data Do via the data output buffer 52.

At the time of data writing, externally input write data Di is fetched by the data input buffer 51, and the fetched write data Di is stored in the memory of the area selected by the X decoder 28 and the Y decoder 29. Written to the cell.

According to the storage device of this embodiment configured as described above, the following effects can be obtained. The memory cell array 53 is simply divided into four blocks 54 to 5
7, and an address mapping circuit 50 for mapping an address signal to an internal address signal based on information on a bit width of data used by an arithmetic processing unit that accesses the storage device 48. Therefore, according to the storage device 48, a storage device having a required bit width can be realized only by setting the bit width of data.
The development period can be shortened and the cost can be reduced. The embodiment is not limited to the above,
It may be changed as follows.

According to the fifth embodiment, a storage device having a configuration in which only one of the data input multiplexer 25 and the data output multiplexer 26 is omitted. According to the fourth and fifth embodiments, a storage device having a configuration in which all of the address multiplexer 22, the data input multiplexer 25, and the data output multiplexer 26 are omitted.

In the sixth embodiment, the storage device is such that the storage circuit 49 is omitted. In the first to sixth embodiments, the case where three arithmetic processing units access one storage device has been described, but the number of arithmetic processing units accessing the storage device is set to an arbitrary number of 2 or more. May be. In this case, the same effects as those of the first to fifth embodiments can be obtained.

In the first to fifth embodiments, the memory cell array 27 or 53 is provided with a plurality of blocks 31 to 34 or 54 capable of inputting and outputting 8-bit data.
However, the bit width of the block may be changed to any other number (for example, 4 bits). Also,
The number of blocks is also arbitrary. In these cases, the same effects as in the first to sixth embodiments can be obtained.

In the above embodiments, the storage device is constituted by a DRAM. However, the present invention is not limited to this, and may be constituted by an SRAM, a ROM, or the like. The storage device according to the present invention can be applied to all RAMs and ROMs.

[0083]

As described above in detail, according to any one of the first to thirteenth aspects of the present invention, common access with different bit widths is enabled, thereby shortening the development period and reducing the cost. Can be realized.

According to the fourth or ninth aspect of the present invention, it is possible to selectively take in address information of a plurality of types of address signals. According to the invention described in claim 5, input data corresponding to a plurality of types of address signals can be selectively captured.

According to the present invention, data corresponding to a plurality of types of address signals can be selectively output. According to the seventh or eighth aspect of the present invention, access with a bit width that is an integral multiple of the minimum bit width becomes possible.

According to the tenth aspect, input data corresponding to a plurality of types of address signals can be selectively taken in, and data corresponding to a plurality of types of address signals can be selectively output. Can be.

According to the invention as set forth in any one of claims 11 to 13, address information of a plurality of types of address signals is selectively captured, and input data corresponding to a plurality of types of address signals is selectively captured. And data corresponding to a plurality of types of address signals can be selectively output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a storage device according to a first embodiment;

FIG. 2 is a block diagram showing a memory cell array.

FIG. 3 is an explanatory diagram showing an address space of the storage device.

FIG. 4 is a schematic diagram showing a system using the storage device of the first embodiment;

FIG. 5 is a block diagram illustrating a storage device according to a second embodiment;

FIG. 6 is a block diagram illustrating a storage device according to a third embodiment;

FIG. 7 is a block diagram showing a storage device according to a fourth embodiment;

FIG. 8 is a block diagram illustrating a storage device according to a fifth embodiment.

FIG. 9 is a block diagram showing a storage device according to a sixth embodiment;

FIG. 10 is a block diagram showing a memory cell array.

FIG. 11 is a block diagram showing a conventional system.

[Explanation of symbols]

21, 49 ... Storage circuit 22 ... Address multiplexer as address switching means 23 ... Address input buffer 24, 50 ... Address mapping circuit as address mapping means 25 ... Data input multiplexer as input data switching means 26 ... Data output multiplexer 27, 53 as output data switching means Memory cell array 28 as storage means 28 X decoder 29 Y decoder 31-34, 54-57 Block 51 Data input buffer 52 as data input means 52 Data output Data output buffers 311-313, 321-323, 331-333, 3 as means
41 to 343: storage area

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ken Sakai 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (13)

[Claims] 1. A storage device comprising: a storage unit having a predetermined storage capacity; and an address mapping unit that maps an address specified by the bit width information of an access signal to an internal address of the storage unit. 2. A storage unit having a predetermined storage capacity, and an address mapping unit for mapping an address designated by the bit width information and the used capacity information of an access signal to an internal address of the storage unit. Storage device. 3. The storage device according to claim 2, wherein the storage unit divides the storage area in advance based on each used capacity information of a plurality of types of access signals, and wherein the address mapping unit specifies the designated address. Storage device for converting an address to an internal address according to the divided storage area of the storage means. 4. The storage device according to claim 2, further comprising address switching means for selectively taking in each address information of said plurality of types of access signals. 5. The storage device according to claim 2, further comprising input data switching means for selectively taking in input data corresponding to the plurality of types of access signals. 6. The storage device according to claim 2, further comprising output data switching means for selectively outputting output data corresponding to the plurality of types of access signals. 7. The storage device according to claim 1, wherein the storage unit includes a plurality of memory cell blocks corresponding to a minimum bit width of the access signal, and the plurality of memory cell blocks. And an XY decoder for individually accessing each unit cell based on the mapped internal address. 8. The storage device according to claim 1, wherein a storage circuit stores bit width information of the access signal, and outputs the bit width information to the address mapping means, and holds address information of the access signal. A storage device comprising: an address input unit that outputs the data to the address mapping unit; a data input unit that receives input data corresponding to the access signal; and a data output unit that outputs data corresponding to the access signal. 9. The storage device according to claim 4, wherein the storage circuit stores bit width information and used capacity information of the access signal, and outputs the bit width information and used capacity information to the address mapping means. An address input unit that holds the address information captured by the address switching unit and outputs the address information to the address mapping unit. 10. The storage device according to claim 2, wherein the bit width information and the used capacity information of the access signal are stored, and the bit width information and the used capacity information are output to the address mapping unit. Address input means for holding address information of the access signal and outputting the address information to the address mapping means; input data switching means for selectively taking in input data corresponding to a plurality of types of access signals; And output data switching means for selectively outputting output data corresponding to. 11. The storage device according to claim 4, wherein address input means for holding the address information fetched by said address switching means and outputting it to said address mapping means, and input corresponding to a plurality of types of access signals. A storage device comprising: input data switching means for selectively capturing data; and output data switching means for selectively outputting output data corresponding to a plurality of types of access signals. 12. The storage device according to claim 11, further comprising a storage circuit that stores bit width information and used capacity information of the access signal, and outputs the bit width information and used capacity information to the address mapping unit. Storage device. 13. The storage device according to claim 2, wherein bit width information and used capacity information of the access signal are stored, and the bit width information and used capacity information are output to the address mapping unit. Address input means for holding respective address information of the plurality of access signals; and selectively acquiring each address information of the plurality of access signals held in the address input means and outputting the address information to the address mapping means. Address switching means, input data switching means for selectively taking in input data corresponding to a plurality of types of access signals, and output data switching means for selectively outputting output data corresponding to a plurality of types of access signals Storage device.