JPH11150213A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11150213A JPH11150213A JP9315148A JP31514897A JPH11150213A JP H11150213 A JPH11150213 A JP H11150213A JP 9315148 A JP9315148 A JP 9315148A JP 31514897 A JP31514897 A JP 31514897A JP H11150213 A JPH11150213 A JP H11150213A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor device
- resin
- notch
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関す
るものであり、更に詳しくは、樹脂により封止される半
導体装置に関する。The present invention relates to a semiconductor device, and more particularly, to a semiconductor device sealed with a resin.
【０００２】[0002]
【従来の技術】半導体装置の封止は、プラスチックパッ
ケージなどの樹脂を用いた、いわゆる樹脂封止が低コス
トのため、主流となっている。この樹脂封止では、通
常、半導体チップ１１’及びこれが載置された図４に示
すような四角形のダイパッド２を、封止樹脂が覆ってい
る。しかしながら樹脂封止では、半導体装置の実装時に
おける加熱時、例えばリフロー（予めアウタリードなど
に半田を施し、赤外線による輻射熱またはフッ素系不活
性液体によって、半導体装置及びこれが仮固定される回
路基板全体を半田付け温度に加熱し、その半田を再溶融
させて半田付けする方法）を行う際の半導体装置全体の
加熱により、半導体装置の封止樹脂にクラックが発生す
る。これは、金属からなるダイパッド２と封止樹脂との
熱膨張係数が異なり、ダイパッド２と、これを封止して
いる樹脂との界面に剥離が生じることと、及びパッケー
ジである樹脂が周囲の雰囲気中の水分を吸収し、この水
分が内部で拡散することに起因する。すなわち、半導体
装置全体が加熱されると、半導体チップをダイパッドに
接合するための接合材料（例えばＡｇ（銀）ペーストな
ど）や樹脂の中に含まれる水分が気化して、ダイパッド
２と樹脂との界面の剥離した部分に噴出し、遂には、こ
の気化した水分の水蒸気圧で、すなわち水蒸気圧の応力
で樹脂が膨張し、クラックが発生するのである。2. Description of the Related Art In semiconductor device sealing, so-called resin sealing using a resin such as a plastic package has become mainstream because of its low cost. In this resin encapsulation, the encapsulation resin usually covers the semiconductor chip 11 'and the square die pad 2 on which the semiconductor chip 11' is mounted as shown in FIG. However, in the case of resin encapsulation, when the semiconductor device is heated at the time of mounting, for example, reflow (solder is applied to an outer lead in advance, and the semiconductor device and the entire circuit board to which this is temporarily fixed are soldered by radiant heat by infrared rays or a fluorine inert liquid. (The method of heating to the attachment temperature and re-melting the solder to solder)), the sealing resin of the semiconductor device cracks due to the heating of the entire semiconductor device. This is because the die pad 2 made of metal and the sealing resin have different coefficients of thermal expansion, separation occurs at the interface between the die pad 2 and the resin sealing the die pad 2, and the resin that is the package is It is caused by absorbing moisture in the atmosphere and diffusing this moisture inside. That is, when the entire semiconductor device is heated, moisture contained in a bonding material (for example, Ag (silver) paste or the like) or a resin for bonding the semiconductor chip to the die pad is vaporized, and the bonding between the die pad 2 and the resin is performed. The resin is ejected to the separated portion of the interface, and finally the resin expands due to the vapor pressure of the vaporized water, that is, the stress of the vapor pressure, and a crack is generated.
【０００３】このクラックの発生を防止するために、特
開平５−１５２３５５号公報、特開平５−１９８７０２
号公報、特開平５−８２６７５号公報及び特開平６−１
２８３５５号公報の「半導体装置」では、半導体チップ
を封止する樹脂を、ある特定の成分を含有しているエポ
キシ樹脂組成物としている。また、特開昭６１−３９５
５３号公報の「半導体装置」には、半導体チップの角部
を斜めにカットして樹脂封止し、角部に集中する応力を
緩和させている。しかしながら、これらの対策だけで
は、クラックを充分に防止しているとは言えなかった。In order to prevent the occurrence of cracks, Japanese Patent Application Laid-Open No. 5-152355 and Japanese Patent Application Laid-Open No. 5-198702
JP, JP-A-5-82675 and JP-A-6-1
In the "semiconductor device" of JP-A-28355, a resin for encapsulating a semiconductor chip is an epoxy resin composition containing a specific component. Also, JP-A-61-395
In the "semiconductor device" disclosed in Japanese Patent No. 53, a corner of a semiconductor chip is cut obliquely and sealed with a resin to reduce stress concentrated on the corner. However, these measures alone did not sufficiently prevent cracks.
【０００４】[0004]
【発明が解決しようとする課題】本発明は、上述の問題
に鑑みてなされ、樹脂封止される半導体装置の樹脂パッ
ケージのクラックの発生を減少し、信頼性の高い半導体
装置を提供することを課題とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has as its object to provide a highly reliable semiconductor device which reduces the occurrence of cracks in a resin package of a semiconductor device to be resin-sealed. Make it an issue.
【０００５】[0005]
【課題を解決するための手段】以上の課題は、半導体チ
ップを載置し、その周辺部に、切欠及び／又は貫通孔を
形成されたダイパッドを有したリードフレームを用い
て、樹脂封止される半導体装置によって解決される。An object of the present invention is to provide a semiconductor chip on which a semiconductor chip is mounted and which is sealed with a resin by using a lead frame having a die pad formed with a notch and / or a through hole in a peripheral portion thereof. It is solved by a semiconductor device.
【０００６】この構造により、ダイパッドの上方及び下
方にある樹脂が、切欠及び／又は貫通孔を介して一体化
されるので、樹脂とダイパッドとの密着性が向上する。
すなわち、樹脂とダイパッドとの界面の剥離がほとんど
生じないので、半導体装置の樹脂パッケージのクラック
の発生を低減することができる。[0006] With this structure, the resin above and below the die pad is integrated through the notch and / or the through-hole, so that the adhesion between the resin and the die pad is improved.
That is, since the interface between the resin and the die pad hardly peels off, the occurrence of cracks in the resin package of the semiconductor device can be reduced.
【０００７】[0007]
【発明の実施の形態】本発明では、半導体チップを載置
するダイパッドの周辺部に、切欠及び／又は貫通孔を形
成したリードフレームを用い、かつ樹脂封止される半導
体装置とする。これによって、切欠及び／又は貫通孔を
介して、リードフレームの上方及び下方の樹脂が一体化
され、リードフレームと樹脂との密着性が向上する。そ
のため、半導体装置の実装の加熱時においても、リード
フレームと樹脂との界面に生じる剥離を低減することが
できる。従って、通常、この界面の剥離した部分に気化
した水分が噴出することによって生じるクラックを低減
することができる。そのため、本発明の半導体装置は、
アウタリードの先端のみを半田浴に浸漬して半田付けを
行う場合よりも熱条件が過酷なリフローによって半田付
けをする場合にも、信頼性の高い半導体装置とすること
ができる。なお、ダイパッドは半導体装置のリードフレ
ームの一部であるが、これは、通常、金型によって形成
されるので、ダイパッドの周辺部に、切欠及び／又は貫
通孔を形成するといっても、そのリードフレームの製造
が難しくなることもない。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a semiconductor device is formed by using a lead frame in which a notch and / or a through hole is formed around a die pad on which a semiconductor chip is mounted, and which is sealed with a resin. Thereby, the resin above and below the lead frame is integrated via the notch and / or the through-hole, and the adhesion between the lead frame and the resin is improved. Therefore, even at the time of heating the mounting of the semiconductor device, separation occurring at the interface between the lead frame and the resin can be reduced. Therefore, cracks that are usually caused by the spouting of vaporized moisture to the separated portion of the interface can be reduced. Therefore, the semiconductor device of the present invention
Even when soldering is performed by reflow under severer heat conditions than when soldering by immersing only the tip of the outer lead in a solder bath, a highly reliable semiconductor device can be obtained. Note that the die pad is a part of the lead frame of the semiconductor device. Since the die pad is usually formed by a mold, even if a notch and / or a through hole is formed around the die pad, the die pad is not formed. The manufacture of the frame does not become difficult.
【０００８】勿論、ダイパッドにおける切欠及び／又は
貫通孔の面積は、大きい方が、より剥離を生じにくくな
るので好ましく、そのため、複数の切欠及び／又は貫通
孔を設けるとよい。また、その切欠及び／貫通孔を、ダ
イパッドの周縁部から中心に向かって延びる細長いスリ
ット形状とすれば、通常ダイパッドの中心に載置される
半導体チップのダイパッドとの接着性を良好としたま
ま、ダイパッドと樹脂との密着性を向上させることがで
き、かつ、ダイパッドに載置する半導体チップが種々の
大きさのものであっても、その大きさによって、ダイパ
ッドと樹脂との密着性が著しく変化するということがな
い。すなわち、ダイパッドに載置する半導体チップは、
切欠を覆うように配設しても、切欠が設けられていない
部分に配設されても、良好な密着性を得ることができ
る。Of course, it is preferable that the area of the notch and / or through-hole in the die pad is large, since peeling is less likely to occur. Therefore, it is preferable to provide a plurality of notches and / or through-holes. Further, if the notch and / or the through-hole are formed in an elongated slit shape extending from the peripheral portion of the die pad toward the center, the adhesion of the semiconductor chip normally mounted at the center of the die pad to the die pad can be improved. The adhesion between the die pad and the resin can be improved, and even if the semiconductor chip mounted on the die pad is of various sizes, the adhesion between the die pad and the resin significantly changes depending on the size. I never do. That is, the semiconductor chip mounted on the die pad is:
Good adhesion can be obtained regardless of whether the cover is provided so as to cover the cutout or a portion where the cutout is not provided.
【０００９】更に、樹脂とダイパッドとの剥離は、通
常、角が最もに発生し易く、そのため、ダイパッドがほ
ぼ四角形（通常、このような形状をしている）の形状を
している場合には、切欠及び／又は貫通孔をダイパッド
の角に形成するのが好ましい。なお、この場合、より角
における剥離を充分に防止して、クラックの発生を低減
するためには、ダイパッドを支持する吊りピンをダイパ
ッドの（ほぼ四角形状の）辺に接続されるようにするの
が好ましい。Further, the peeling of the resin and the die pad is usually most likely to occur at the corners. Therefore, when the die pad has a substantially square shape (usually such a shape), , Notches and / or through holes are preferably formed at the corners of the die pad. In this case, in order to sufficiently prevent peeling at corners and reduce the occurrence of cracks, it is necessary to connect the suspending pins supporting the die pad to the (substantially square) side of the die pad. Is preferred.
【００１０】[0010]
【実施例】以下、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１１】図１のＡは、本発明の半導体装置の断面図
であり、図１のＢは、図１のＡにおける［Ｂ］−［Ｂ］
線方向の平面図である。この半導体装置は全体として１
０で示されているが、これは、半導体チップ１１（これ
は断面にして図示していない）と、金属から成るダイパ
ッド２１及び、複数（本実施例では、８つ）のリード２
２と、半導体チップ１１上の図示しないボンディングパ
ッドとリード２２とを接続している金線１２と、これら
を封止している樹脂１３（例えばこれはエポキシ樹脂か
ら成る）とから構成されている。FIG. 1A is a cross-sectional view of the semiconductor device of the present invention, and FIG. 1B is [B]-[B] in FIG. 1A.
It is a top view of a line direction. This semiconductor device has 1
0, the semiconductor chip 11 (which is not shown in cross section), a die pad 21 made of metal, and a plurality (eight in this embodiment) of leads 2
2, a gold wire 12 connecting the bonding pad (not shown) on the semiconductor chip 11 and the lead 22, and a resin 13 (for example, this is made of epoxy resin) for sealing these. .
【００１２】ダイパッド２１は、図１のＢに示すよう
に、例えば横Ｘが２．５ｍｍ、縦Ｙが２．８ｍｍの長方
形形状をしており、その上辺と下辺には、後述する吊り
ピン２１ａの一部が接続している。更に、ダイパッド２
１の４つの角には、幅Ｄが０．２ｍｍ、長さＬが０．８
ｍｍ程度の細長いスリット形状の切欠１５が、中心部Ｃ
に延びるように、それぞれ設けられている。なお、ダイ
パッド２１には、例えば公知のＡｇ（銀）ペースト１４
（これには、接合材料としてエポキシ樹脂などの熱硬化
性樹脂が含有されている）を介して半導体チップ１１が
載置されているが、この半導体チップ１１は、本実施例
では、約２〜３ｍｍ角の長方形形状をしている。As shown in FIG. 1B, the die pad 21 has a rectangular shape with a width X of 2.5 mm and a length Y of 2.8 mm, for example. Some are connected. Furthermore, die pad 2
In the four corners of 1, the width D is 0.2 mm and the length L is 0.8
mm slit-like notch 15
Are respectively provided so as to extend. The die pad 21 is provided with, for example, a well-known Ag (silver) paste 14.
(This contains a thermosetting resin such as an epoxy resin as a bonding material.) The semiconductor chip 11 is mounted on the semiconductor chip 11 in this embodiment. It has a rectangular shape of 3 mm square.
【００１３】図２には、本実施例の半導体装置１の製造
工程において用いられたリードフレームＦが示されてい
る。このリードフレームＦは、公知のように、１個のダ
イパッド２１と、これを囲む複数のリード２２とから成
るパターンＰを複数、有している。本実施例の半導体装
置１で用いたリードフレームＦには、このパターンＰ
が、図示のように３つ並んでおり、すなわち吊りピン２
１ａによって３つのダイパッド２１が連結がしており、
これがいくつも（図示、省略されているが例えば１４個
程度）形成されているものである。FIG. 2 shows a lead frame F used in the manufacturing process of the semiconductor device 1 of the present embodiment. As is known, the lead frame F has a plurality of patterns P each including one die pad 21 and a plurality of leads 22 surrounding the die pad 21. The lead frame F used in the semiconductor device 1 of this embodiment has the pattern P
Are arranged side by side as shown in FIG.
The three die pads 21 are connected by 1a,
There are a number of them (not shown, but omitted, for example, about 14).
【００１４】なお、この半導体装置１０は、公知の以下
の方法で形成される。まず、リードフレームＦのダイパ
ッド２１を、リードフレームＦのリード２２より一段低
くした後、Ａｇペースト１４を介して半導体チップ１１
をダイパッド２１に接着する。そして、ボンティングパ
ッドとリード２２のインナーリードとを金線１２によっ
てダイボンディングし、樹脂１３によってパッケージン
グを行う。最後にリード２２を加工して、図１のＡのよ
うな半導体装置１０が完成する。なおまた、本発明の半
導体装置１０は、従来と同様に、リフローによって、す
なわち、半導体装置１０全体を加熱することにより、回
路基板に実装される。The semiconductor device 10 is formed by the following known method. First, after lowering the die pad 21 of the lead frame F by one step from the lead 22 of the lead frame F, the semiconductor chip 11 is put through the Ag paste 14.
Is adhered to the die pad 21. Then, the bonding pad and the inner lead of the lead 22 are die-bonded with the gold wire 12, and packaging is performed with the resin 13. Finally, the lead 22 is processed to complete the semiconductor device 10 as shown in FIG. In addition, the semiconductor device 10 of the present invention is mounted on the circuit board by reflow, that is, by heating the entire semiconductor device 10 as in the related art.
【００１５】次に、本発明の半導体装置１０、すなわ
ち、図３に斜視図で示されているように、上述した形状
のダイパッド２１に半導体チップ１１が載置された半導
体装置１０を、約８５℃の温度、６５％の湿度の雰囲気
中に２４時間入れた後、これを常温に取り出してしばら
く放置し、再びこの条件の雰囲気中に２４時間入れて、
クラックが発生するか否かの試験を行った。なお、比較
のために、図４に斜視図で示されている従来の半導体装
置（すなわち切欠１５がないダイパッド２に半導体チッ
プ１１’が載置されている半導体装置）１についても同
様な条件で試験を行った。なお、これらはぞれぞれ１５
個ずつについて用いた。Next, the semiconductor device 10 of the present invention, that is, the semiconductor device 10 in which the semiconductor chip 11 is mounted on the die pad 21 having the above-mentioned shape as shown in a perspective view in FIG. After placing in an atmosphere of a temperature of 65 ° C. and a humidity of 65% for 24 hours, it was taken out to room temperature and left for a while, and then placed again in an atmosphere of this condition for 24 hours.
A test was performed to determine whether cracks occurred. For comparison, a conventional semiconductor device 1 (that is, a semiconductor device in which a semiconductor chip 11 'is mounted on a die pad 2 having no notch 15) shown in a perspective view in FIG. The test was performed. These are each 15
Used individually.
【００１６】半導体装置１、１０の外観から光学顕微鏡
によって判別できる（これは約０．５〜１ｍｍ程度の長
さを有するクラック）外部クラックは、従来の半導体装
置１では１５個のすべてにおいて発生していたが、本実
施例の半導体装置１０では、１５個中１２個においての
み発生していた。すなわち１５個中３個には、外部クラ
ックが認められなかった。また、外見からわからない内
部クラック（これは、試験されの半導体装置１、１０を
切断することにより、その切断した内部を、外部クラッ
のと同様に光学顕微鏡によって判別した）は、従来の半
導体装置１では、１５個のすべてにおいて発生していた
が、本実施例の半導体装置１０では、１５個中２個にお
いてのみ発生していた。すなわち、１５個中１３個に
は、内部クラックは認められなかった。従って、本発明
の半導体装置１０が、クラックの発生、特に内部クラッ
クの発生を確実に低減していることは明らかである。External cracks which can be discriminated from the appearance of the semiconductor devices 1 and 10 by an optical microscope (this is a crack having a length of about 0.5 to 1 mm) occur in all 15 semiconductor devices in the conventional semiconductor device 1. However, in the semiconductor device 10 of the present embodiment, only 12 out of 15 semiconductor devices occurred. That is, external cracks were not observed in three out of fifteen pieces. Internal cracks that cannot be seen from the outside (this is determined by cutting the tested semiconductor devices 1 and 10 and discriminating the cut interior with an optical microscope in the same manner as the external crack) are the conventional semiconductor device 1 In the semiconductor device 10 of the present embodiment, this occurred in only two of the 15 semiconductor devices. That is, no internal crack was observed in 13 out of 15 pieces. Therefore, it is apparent that the semiconductor device 10 of the present invention reliably reduces the occurrence of cracks, particularly the occurrence of internal cracks.
【００１７】以上、本発明の各実施例について説明した
が、勿論、本発明はこれらに限定されることなく、本発
明の技術的思想に基づいて種々の変形が可能である。Although the embodiments of the present invention have been described above, the present invention is, of course, not limited to these, and various modifications can be made based on the technical concept of the present invention.
【００１８】例えば、上記実施例では、樹脂１３の両側
にリード２２が並んでいるＤＩＰ（Ｄｕａｌ Ｉｎｌｉ
ｎｅ Ｐａｋａｇｅ）について説明したが、その他ＳＯ
Ｐ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）、
ＳＳＯＰ（ＳｈｉｒｉｎｋＳｍａｌｌ Ｏｕｔｌｉｎｅ
Ｐａｃｋａｇｅ）、ＱＦＰ（Ｑｕａｄ ＦｌａｔＰａ
ｃｋａｇｅ）など、半導体チップを載置するダイパッド
を有したリードフレームを用いて樹脂封止される半導体
装置であれば、どのような型の半導体装置であっても本
発明は適用可能である。For example, in the above embodiment, a DIP (Dual Inli) in which the leads 22 are arranged on both sides of the resin 13 is used.
ne Package), but other SO
P (Small Outline Package),
SSOP (ShrinkSmall Outline
Package), QFP (Quad FlatPa)
The present invention is applicable to any type of semiconductor device that is resin-sealed using a lead frame having a die pad on which a semiconductor chip is mounted, such as a semiconductor device.
【００１９】また、上記実施例では、ダイパッド２１の
角から中心部Ｃに向かって延びる切欠１５を設けたが、
更に、図５のＡに示すように、そのダイパッド３１の辺
から中心部Ｃに向かって延びる切欠２５をも設けるよう
にしてもよい。また、例えば図５のＢで示すように、ダ
イパッド３１’の周辺部に長く延びる切欠１５’を設
け、その角に貫通孔３５’を設けるようにしてもよい。
なお、切欠１５、１５’、２５及び／又は貫通孔３５’
の形状は、これに限定される必要はなく、例えば、図５
のＣに示すように、複雑な形状の貫通孔３５を設けたダ
イパッド３１”としてもよい。なお、図５のＢ、Ｃに示
されるように、ダイパッド３１’、３１”を支持する吊
りピン３１ａ’、３１ａ”は、ダイパッド３１’、３
１”の角に接続するようにしてもよい。In the above embodiment, the notch 15 extending from the corner of the die pad 21 toward the center C is provided.
Further, as shown in FIG. 5A, a notch 25 extending from the side of the die pad 31 toward the center C may be provided. Alternatively, as shown in FIG. 5B, for example, a long notch 15 ′ may be provided in the periphery of the die pad 31 ′, and a through hole 35 ′ may be provided at a corner thereof.
Notches 15, 15 ', 25 and / or through holes 35'
Need not be limited to this shape. For example, FIG.
5C, a die pad 31 ″ having a through hole 35 of a complicated shape may be provided. As shown in FIGS. 5B and 5C, suspension pins 31a supporting the die pads 31 ′ and 31 ″ may be used. ', 31a "are the die pads 31', 3
It may be connected to the 1 "corner.
【００２０】また、上記実施例では、封止する樹脂１３
に熱硬化性のエポキシ樹脂を採用したが、これ以外の熱
硬化性樹脂や、熱可塑性の耐熱性樹脂、例えばポリフェ
ニレンサルファイドなども使用してもよい。また、上記
実施例では、半導体チップ１１をダイパッド２１に接合
させるための接合材料として、熱硬化性樹脂であるエポ
キシ樹脂を含有したＡｇペースト１４を挙げたが、その
他、半田やＡｕ−Ｓｉ共晶法などで接合してもよい。更
に、上記実施例では半導体チップ１１の大きさは、２〜
３ｍｍ角の長方形で、図１のＢに示すように、切欠１５
に掛かるような大きさとしたが、この大きさは、半導体
チップが接合するダイパッドより小さいものであれば、
どのような大きさでもよく、切欠１５に掛からない大き
さでもよい。In the above embodiment, the sealing resin 13 is used.
Although a thermosetting epoxy resin is used, other thermosetting resins and thermoplastic heat-resistant resins such as polyphenylene sulfide may be used. In the above-described embodiment, the Ag paste 14 containing an epoxy resin which is a thermosetting resin is used as a bonding material for bonding the semiconductor chip 11 to the die pad 21. However, solder or Au-Si eutectic may be used. It may be joined by a method or the like. Further, in the above embodiment, the size of the semiconductor chip 11 is 2 to 2.
As shown in FIG. 1B, a rectangle of 3 mm square
, But if this size is smaller than the die pad to which the semiconductor chip is bonded,
The size may be any size, and may be a size that does not catch on the notch 15.
【００２１】[0021]
【発明の効果】以上述べたように、本発明の半導体装置
によれば、半導体チップを載置するダイパッドと封止す
る樹脂との密着性を向上させて、ダイパッドと樹脂との
界面における剥離を低減し、封止樹脂に発生するクラッ
クを低減して、信頼性を向上させることができる。As described above, according to the semiconductor device of the present invention, the adhesion between the die pad on which the semiconductor chip is mounted and the sealing resin is improved, and the separation at the interface between the die pad and the resin is prevented. It is possible to reduce the number of cracks generated in the sealing resin and improve the reliability.
【図１】本発明の半導体装置を示す図であり、Ａはその
断面図、ＢはＡにおける［Ｂ］−［Ｂ］線方向の平面図
である。FIG. 1 is a view showing a semiconductor device of the present invention, in which A is a cross-sectional view, and B is a plan view taken along the line [B]-[B] in A.
【図２】本発明の半導体装置に用いられたリードフレー
ムの平面図である。FIG. 2 is a plan view of a lead frame used in the semiconductor device of the present invention.
【図３】本発明の半導体装置に用いられたリードフレー
ムのダイパッドに半導体チップが載置された状態の斜視
図である。FIG. 3 is a perspective view showing a state where a semiconductor chip is mounted on a die pad of a lead frame used in the semiconductor device of the present invention.
【図４】従来の半導体装置に用いられたリードフレーム
のダイパッドに半導体チップが載置された状態の斜視図
である。FIG. 4 is a perspective view showing a state in which a semiconductor chip is mounted on a die pad of a lead frame used in a conventional semiconductor device.
【図５】本発明の半導体装置に用いられるリードフレー
ムの変形例の要部の拡大図であり、Ａは四角形の辺から
中心部に延びる切欠をも形成した形状のダイパッドを示
し、Ｂは四角形の周辺部に設けられた細長い切欠及び角
に貫通孔を形成した形状のダイパッドを示し、Ｃは複数
の貫通孔を有したダイパッドを示している。5 is an enlarged view of a main part of a modified example of the lead frame used in the semiconductor device of the present invention, in which A shows a die pad having a notch extending from the side of the square to the center, and B shows a die pad; FIG. Shows a die pad in the shape of a long cutout and a through hole formed in a corner provided in the peripheral portion of FIG. 1, and C shows a die pad having a plurality of through holes.
１０……半導体装置、１１……半導体チップ、１３……
封止樹脂、１４……Ａｇペースト、１５、１５’……切
欠、２１……ダイパッド、２１ａ……吊りピン、２２…
…リード、２５……切欠、３１、３１’、３１”……ダ
イパッド、３１ａ’、３１ａ”……吊りピン、３５、３
５’……貫通孔、Ｃ……中心部、Ｆ……リードフレー
ム、Ｐ……パターン。10 ... semiconductor device, 11 ... semiconductor chip, 13 ...
Sealing resin, 14 Ag paste, 15, 15 'Notch, 21 Die pad, 21a Hanging pin, 22
... Lead, 25 ... Notch, 31, 31 ', 31 "... Die pad, 31a', 31a" ... Hanging pin, 35, 3
5 ': through-hole, C: central part, F: lead frame, P: pattern.
Claims (6)
したリードフレームを用いて、樹脂により封止される半
導体装置において、 前記ダイパッドの周辺部に、切欠及び／又は貫通孔が形
成されていることを特徴とする半導体装置。1. A semiconductor device sealed with a resin using a lead frame having a die pad on which a semiconductor chip is mounted, wherein a notch and / or a through hole is formed in a peripheral portion of the die pad. A semiconductor device characterized by the above-mentioned.
とを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein there are a plurality of notches and / or through holes.
パッドの周縁部から中心部に向かって延びる細長いスリ
ット形状をしていることを特徴とする請求項２に記載の
半導体装置。3. The semiconductor device according to claim 2, wherein the notch and / or the through-hole has an elongated slit shape extending from a peripheral portion of the die pad toward a center portion.
成されていることを特徴とする請求項２に記載の半導体
装置。4. The semiconductor device according to claim 2, wherein the die pad has a substantially square shape, and the notch and / or the through hole is formed at a corner of the die pad.
状の辺に接続される吊りピンを有しており、 前記切欠が、前記ダイパッドの角から中心部に向かって
延びる細長いスリット形状をしていることを特徴とする
請求項２に記載の半導体装置。5. The die pad has a substantially square shape, the lead frame has a suspension pin connected to the substantially square side of the die pad, and the notch extends from a corner of the die pad. 3. The semiconductor device according to claim 2, wherein the semiconductor device has an elongated slit shape extending toward a center.
実装されることを特徴とする請求項１乃至請求項５の何
れかに記載の半導体装置。6. The semiconductor device according to claim 1, wherein the semiconductor device is mounted on a circuit board by being heated as a whole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9315148A JPH11150213A (en) | 1997-11-17 | 1997-11-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9315148A JPH11150213A (en) | 1997-11-17 | 1997-11-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11150213A true JPH11150213A (en) | 1999-06-02 |
Family
ID=18061999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9315148A Pending JPH11150213A (en) | 1997-11-17 | 1997-11-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11150213A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002110886A (en) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | Lead frame for semiconductor and semiconductor device using the same |
| US6664134B2 (en) * | 2001-02-23 | 2003-12-16 | Koninklijke Philips Electronics N.V. | Method of mounting a semiconductor device with a eutectic layer |
| JP2007150040A (en) * | 2005-11-29 | 2007-06-14 | Mitsubishi Electric Corp | Semiconductor device |
| JP2007311579A (en) * | 2006-05-19 | 2007-11-29 | Matsushita Electric Ind Co Ltd | Lead frame and semiconductor device using the same |
| US7799611B2 (en) * | 2002-04-29 | 2010-09-21 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| US8236612B2 (en) | 2002-04-29 | 2012-08-07 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| US8432031B1 (en) * | 2009-12-22 | 2013-04-30 | Western Digital Technologies, Inc. | Semiconductor die including a current routing line having non-metallic slots |
| TWI427750B (en) * | 2010-07-20 | 2014-02-21 | Siliconix Electronic Co Ltd | Semiconductor packages including die and l-shaper lead and method of manufacturing |
| DE102016113679A1 (en) | 2015-08-21 | 2017-02-23 | Tdk Corporation | Magnetic sensor device |
| WO2022230598A1 (en) * | 2021-04-27 | 2022-11-03 | ローム株式会社 | Semiconductor device |
-
1997
- 1997-11-17 JP JP9315148A patent/JPH11150213A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002110886A (en) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | Lead frame for semiconductor and semiconductor device using the same |
| US6664134B2 (en) * | 2001-02-23 | 2003-12-16 | Koninklijke Philips Electronics N.V. | Method of mounting a semiconductor device with a eutectic layer |
| US7799611B2 (en) * | 2002-04-29 | 2010-09-21 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| US8236612B2 (en) | 2002-04-29 | 2012-08-07 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| JP2007150040A (en) * | 2005-11-29 | 2007-06-14 | Mitsubishi Electric Corp | Semiconductor device |
| JP2007311579A (en) * | 2006-05-19 | 2007-11-29 | Matsushita Electric Ind Co Ltd | Lead frame and semiconductor device using the same |
| JP4738250B2 (en) * | 2006-05-19 | 2011-08-03 | パナソニック株式会社 | Semiconductor device |
| US8432031B1 (en) * | 2009-12-22 | 2013-04-30 | Western Digital Technologies, Inc. | Semiconductor die including a current routing line having non-metallic slots |
| US8779574B1 (en) | 2009-12-22 | 2014-07-15 | Western Digital Technologies, Inc. | Semiconductor die including a current routing line having non-metallic slots |
| TWI427750B (en) * | 2010-07-20 | 2014-02-21 | Siliconix Electronic Co Ltd | Semiconductor packages including die and l-shaper lead and method of manufacturing |
| DE102016113679A1 (en) | 2015-08-21 | 2017-02-23 | Tdk Corporation | Magnetic sensor device |
| WO2022230598A1 (en) * | 2021-04-27 | 2022-11-03 | ローム株式会社 | Semiconductor device |
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