JPH11135723A - 混合電圧チップ用カスコード接続mos esd保護回路 - Google Patents
混合電圧チップ用カスコード接続mos esd保護回路Info
- Publication number
- JPH11135723A JPH11135723A JP10242822A JP24282298A JPH11135723A JP H11135723 A JPH11135723 A JP H11135723A JP 10242822 A JP10242822 A JP 10242822A JP 24282298 A JP24282298 A JP 24282298A JP H11135723 A JPH11135723 A JP H11135723A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- circuit
- contact pad
- power supply
- esd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US5727397P | 1997-08-29 | 1997-08-29 | |
| US60/057273 | 1997-08-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11135723A true JPH11135723A (ja) | 1999-05-21 |
| JPH11135723A5 JPH11135723A5 (enExample) | 2005-10-13 |
Family
ID=22009586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10242822A Pending JPH11135723A (ja) | 1997-08-29 | 1998-08-28 | 混合電圧チップ用カスコード接続mos esd保護回路 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5930094A (enExample) |
| JP (1) | JPH11135723A (enExample) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7746611B2 (en) | 2006-08-10 | 2010-06-29 | Infineon Technologies Ag | ESD protective circuit having low leakage current |
| JP2012524404A (ja) * | 2009-04-15 | 2012-10-11 | インターナショナル・ビジネス・マシーンズ・コーポレーション | トレラント及びフェールセーフ設計のためのロバストなesd保護回路、方法及び設計構造体 |
| JP2013211522A (ja) * | 2012-03-02 | 2013-10-10 | Yokogawa Electric Corp | 入力保護回路 |
| JP2016063031A (ja) * | 2014-09-17 | 2016-04-25 | 株式会社ソシオネクスト | 静電気保護回路および集積回路 |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091594A (en) * | 1998-02-18 | 2000-07-18 | Vlsi Technology, Inc. | Protection circuits and methods of protecting a semiconductor device |
| US6369427B1 (en) * | 1998-11-03 | 2002-04-09 | Vlsi, Technology, Inc. | Integrated circuitry, interface circuit of an integrated circuit device, and cascode circuitry |
| JP3844915B2 (ja) * | 1999-06-29 | 2006-11-15 | 株式会社東芝 | 半導体装置 |
| DE19944488A1 (de) * | 1999-09-16 | 2001-04-19 | Infineon Technologies Ag | ESD-Schutzanordnung für Signaleingänge und -ausgänge mit Überspannungstoleranz |
| JP3926975B2 (ja) * | 1999-09-22 | 2007-06-06 | 株式会社東芝 | スタック型mosトランジスタ保護回路 |
| US6466423B1 (en) * | 2000-01-06 | 2002-10-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electrostatic discharge protection device for mixed voltage application |
| US6327126B1 (en) * | 2000-01-28 | 2001-12-04 | Motorola, Inc. | Electrostatic discharge circuit |
| US6690555B1 (en) * | 2001-03-25 | 2004-02-10 | National Semiconductor Corporation | Electrostatic discharge protection circuit with cascoded trigger-switch suitable for use with over-voltage tolerant CMOS input/output buffers |
| KR100431066B1 (ko) * | 2001-09-27 | 2004-05-12 | 삼성전자주식회사 | 정전 방전 보호 기능을 가진 반도체 장치 |
| US6639782B2 (en) * | 2001-11-01 | 2003-10-28 | Macronix International Co., Ltd. | Protecting circuit of the semiconductor factory automation |
| US6657836B2 (en) | 2001-12-18 | 2003-12-02 | Koninklijke Philips Electronics N.V. | Polarity reversal tolerant electrical circuit for ESD protection |
| US6747857B1 (en) * | 2002-02-01 | 2004-06-08 | Taiwan Semiconductor Manufacturing Company | Clamping circuit for stacked NMOS ESD protection |
| US6809386B2 (en) * | 2002-08-29 | 2004-10-26 | Micron Technology, Inc. | Cascode I/O driver with improved ESD operation |
| US7274544B2 (en) * | 2004-10-21 | 2007-09-25 | Taiwan Semiconductor Manufacturing Company | Gate-coupled ESD protection circuit for high voltage tolerant I/O |
| US20070007597A1 (en) * | 2005-07-07 | 2007-01-11 | Microchip Technology Incorporated | ESD structure having different thickness gate oxides |
| US7791851B1 (en) * | 2006-01-24 | 2010-09-07 | Cypress Semiconductor Corporation | Cascode combination of low and high voltage transistors for electrostatic discharge circuit |
| US7385793B1 (en) * | 2006-01-24 | 2008-06-10 | Cypress Semiconductor Corporation | Cascode active shunt gate oxide project during electrostatic discharge event |
| TW200739872A (en) * | 2006-04-04 | 2007-10-16 | Univ Nat Chiao Tung | Power line electrostatic discharge protection circuit featuring triple voltage tolerance |
| US7642856B1 (en) * | 2006-05-30 | 2010-01-05 | Atheros Communications, Inc. | Amplifier capable of using a power supply voltage higher than its process voltages |
| US7812638B2 (en) * | 2007-09-06 | 2010-10-12 | National Sun Yat-Sen University | Input output device for mixed-voltage tolerant |
| US7626790B2 (en) * | 2007-10-05 | 2009-12-01 | Smartech Worldwide Limited | Electrostatic discharge protection for a circuit capable of handling high input voltage |
| US7692483B2 (en) * | 2007-10-10 | 2010-04-06 | Atmel Corporation | Apparatus and method for preventing snap back in integrated circuits |
| TWI341636B (en) * | 2007-10-17 | 2011-05-01 | Mstar Semiconductor Inc | Circuit for protecting nmos device from voltage stress |
| CN101483032B (zh) * | 2008-01-10 | 2011-06-15 | 瑞鼎科技股份有限公司 | 控制芯片 |
| US8085604B2 (en) * | 2008-12-12 | 2011-12-27 | Atmel Corporation | Snap-back tolerant integrated circuits |
| US9013842B2 (en) | 2011-01-10 | 2015-04-21 | Infineon Technologies Ag | Semiconductor ESD circuit and method |
| US8413101B2 (en) | 2011-07-15 | 2013-04-02 | Infineon Technologies Ag | System and method for detecting parasitic thyristors in an integrated circuit |
| US11056880B1 (en) | 2020-03-31 | 2021-07-06 | Western Digital Technologies, Inc. | Snapback electrostatic discharge protection for electronic circuits |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5473500A (en) * | 1994-01-13 | 1995-12-05 | Atmel Corporation | Electrostatic discharge circuit for high speed, high voltage circuitry |
| US5852375A (en) * | 1997-02-07 | 1998-12-22 | Silicon Systems Research Limited | 5v tolerant I/O circuit |
| US5852540A (en) * | 1997-09-24 | 1998-12-22 | Intel Corporation | Circuit for protecting the input/output stage of a low voltage integrated circuit device from a failure of the internal voltage supply or a difference in the power-up sequencing of supply voltage levels |
-
1998
- 1998-08-26 US US09/140,051 patent/US5930094A/en not_active Expired - Lifetime
- 1998-08-28 JP JP10242822A patent/JPH11135723A/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7746611B2 (en) | 2006-08-10 | 2010-06-29 | Infineon Technologies Ag | ESD protective circuit having low leakage current |
| JP2012524404A (ja) * | 2009-04-15 | 2012-10-11 | インターナショナル・ビジネス・マシーンズ・コーポレーション | トレラント及びフェールセーフ設計のためのロバストなesd保護回路、方法及び設計構造体 |
| JP2013211522A (ja) * | 2012-03-02 | 2013-10-10 | Yokogawa Electric Corp | 入力保護回路 |
| JP2016063031A (ja) * | 2014-09-17 | 2016-04-25 | 株式会社ソシオネクスト | 静電気保護回路および集積回路 |
Also Published As
| Publication number | Publication date |
|---|---|
| US5930094A (en) | 1999-07-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH11135723A (ja) | 混合電圧チップ用カスコード接続mos esd保護回路 | |
| US6147538A (en) | CMOS triggered NMOS ESD protection circuit | |
| CN100481667C (zh) | 使用基底触发硅控整流器的静电放电防护电路 | |
| US5744842A (en) | Area-efficient VDD-to-VSS ESD protection circuit | |
| US6815775B2 (en) | ESD protection design with turn-on restraining method and structures | |
| US6310379B1 (en) | NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors | |
| US8049250B2 (en) | Circuit and method for power clamp triggered dual SCR ESD protection | |
| US6040968A (en) | EOS/ESD protection for high density integrated circuits | |
| EP0740344B1 (en) | Method and apparatus for coupling multiple independent on-chip Vdd busses to an ESD core clamp | |
| US6671153B1 (en) | Low-leakage diode string for use in the power-rail ESD clamp circuits | |
| US7667243B2 (en) | Local ESD protection for low-capicitance applications | |
| US7667936B2 (en) | High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface | |
| US7242561B2 (en) | ESD protection unit with ability to enhance trigger-on speed of low voltage triggered PNP | |
| US5615073A (en) | Electrostatic discharge protection apparatus | |
| US6690066B1 (en) | Minimization and linearization of ESD parasitic capacitance in integrated circuits | |
| US5304839A (en) | Bipolar ESD protection for integrated circuits | |
| US20040051146A1 (en) | ESD protection circuit with high substrate-triggering efficiency | |
| US20050174707A1 (en) | ESD protection circuit | |
| US20110241731A1 (en) | Electro Static Discharge Clamping Device | |
| US7256460B2 (en) | Body-biased pMOS protection against electrostatic discharge | |
| US20040251502A1 (en) | Efficient pMOS ESD protection circuit | |
| Chen et al. | Design methodology for optimizing gate driven ESD protection circuits in submicron CMOS processes | |
| US6323523B1 (en) | N-type structure for n-type pull-up and down I/O protection circuit | |
| TWI877291B (zh) | 靜電放電保護器件及其方法,以及觸發整流器 | |
| US6809915B2 (en) | Gate-equivalent-potential circuit and method for I/O ESD protection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050608 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050608 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070620 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070702 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20071002 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20071005 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20081215 |