JPH11135680A - Electronic component surface mounting board - Google Patents

Electronic component surface mounting board

Info

Publication number
JPH11135680A
JPH11135680A JP30093697A JP30093697A JPH11135680A JP H11135680 A JPH11135680 A JP H11135680A JP 30093697 A JP30093697 A JP 30093697A JP 30093697 A JP30093697 A JP 30093697A JP H11135680 A JPH11135680 A JP H11135680A
Authority
JP
Japan
Prior art keywords
semiconductor element
recess
insulating layer
cavity
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30093697A
Other languages
Japanese (ja)
Other versions
JP3563577B2 (en
Inventor
Norimitsu Fukamizu
則光 深水
Yuzuru Matsumoto
譲 松本
Sentarou Yamamoto
泉太郎 山元
Michinobu Nakamiya
道信 中宮
Shinichi Enami
信一 榎並
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP30093697A priority Critical patent/JP3563577B2/en
Publication of JPH11135680A publication Critical patent/JPH11135680A/en
Application granted granted Critical
Publication of JP3563577B2 publication Critical patent/JP3563577B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To expand the surface area of a board for mounting electronic components by forming a cross-shaped cavity, composed of a recess for mounting a semiconductor element and electrode pad-forming recess having a bottom face higher than that of the element mounting recess. SOLUTION: On an insulation board 11 a cross-shaped cavity 15 for housing a semiconductor element 14 is formed and has a cross shape composed of a rectangular recess 16 for housing this element 14 and electrode pad-forming recess 17 facing opposite crossing that recess 16. A bottom face of the pad- forming recess 17 is higher than that of the element housing recess 16 to result in a min. surface area of the insulation board 11 occupied by the cavity 15 and hence in a max. surface area occupied by electronic components 22, thereby obtaining an electronic components surface mounting board capable of higher density mounting.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子部品表面実装
用基板に関し、特に、基板上に半導体素子と同時にその
他のチップコンデンサ等の小型電子部品を高密度に実装
した電子部品表面実装用基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for mounting electronic components on a surface, and more particularly to a substrate for mounting electronic components on a substrate in which small electronic components such as other chip capacitors are mounted at a high density simultaneously with a semiconductor element. Things.

【0002】[0002]

【従来技術】近年、電子機器は小型軽量化、携帯化が進
んでおり、それに用いられる回路ブロックもその動向に
呼応する形で、小型軽量薄型化、表面実装化、複合化が
押し進められている。
2. Description of the Related Art In recent years, electronic devices have become smaller, lighter and more portable, and the circuit blocks used therein have been reduced in size, weight, and thickness, surface-mounted, and composited in accordance with the trend. .

【0003】このような動向の中で、セラミック回路基
板は、その優れた放熱性や低誘電損失等の特徴から従来
より多用されており、表面実装用ハイブリッドICを中
心にして幅広く応用されてきた。
[0003] In such a trend, ceramic circuit boards have been widely used because of their excellent heat dissipation properties and low dielectric loss, and have been widely applied mainly to hybrid ICs for surface mounting. .

【0004】従来、ハイブリッドICを搭載するセラミ
ック回路基板は平板であることが一般的であったが、基
板の小型化、特に低背化の要求から、これに用いられる
ICチップ(半導体素子)を、キャビティと呼ばれる基
板の一部を正方形状に掘り下げた凹部に収納することが
行なわれている。
Conventionally, a ceramic circuit board on which a hybrid IC is mounted has generally been a flat plate. However, due to a demand for downsizing of the board, particularly, a reduction in height, an IC chip (semiconductor element) used for this is required. A part of a substrate called a cavity is housed in a recess dug into a square shape.

【0005】そして、近年では更なる低背化が要求され
ているため、半導体素子を配置する1段目凹部と、この
1段目凹部の周囲に形成され、かつ1段目凹部の底面よ
りも底面が高い2段目凹部を形成し、この2段目凹部
に、半導体素子からの電気信号を伝える配線を受ける電
極パッドが形成されていた。
In recent years, since further reduction in height has been demanded, a first-stage concave portion in which a semiconductor element is arranged, and a lower portion formed around the first-stage concave portion and lower than the bottom of the first-stage concave portion. A second-stage recess having a high bottom surface is formed, and an electrode pad for receiving a wiring for transmitting an electric signal from the semiconductor element is formed in the second-stage recess.

【0006】このような従来の半導体素子搭載装置を図
7、図8に示す。図7は平面図、図8は図7の断面図で
ある。図において、符号1は、絶縁基体を示している。
この絶縁基体1の表面には半導体素子2を収容する1段
目凹部3が形成されており、この1段目凹部3の周囲に
は環状に2段目凹部4が形成されている。1段目凹部3
および2段目凹部4によりキャビティが構成されてい
る。
FIGS. 7 and 8 show such a conventional semiconductor device mounting apparatus. 7 is a plan view, and FIG. 8 is a sectional view of FIG. In the drawing, reference numeral 1 indicates an insulating base.
On the surface of the insulating base 1, a first-stage recess 3 for housing the semiconductor element 2 is formed. Around the first-stage recess 3, a second-stage recess 4 is formed in an annular shape. First stage recess 3
A cavity is formed by the second-stage recess 4.

【0007】そして、2段目凹部4の表面には、内部配
線に接続された電極パッドが形成され、この電極パッド
には、半導体素子2に接続されたワイヤボンディング6
が接続されている。絶縁基体1の表面には、図7、図8
には図示しなかったが、チップコンデンサや抵抗等の電
子部品が実装されている。尚、図8においては、半導体
素子を省略した。
An electrode pad connected to the internal wiring is formed on the surface of the second recess 4, and a wire bonding 6 connected to the semiconductor element 2 is formed on the electrode pad.
Is connected. 7 and 8 on the surface of the insulating substrate 1.
Although not shown, electronic components such as chip capacitors and resistors are mounted. In FIG. 8, the semiconductor element is omitted.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、上記の
ような電子部品表面実装用基板では、絶縁基体1の表面
に半導体素子2を収納するキャビティを形成し、これに
半導体素子2を収納したため、低背化を促進することが
できるが、各種電子部品を実装することのできる基板表
面の面積がキャビティの占有により少なくなり、そのた
め電子部品の実装効率が低下するという問題があった。
However, in the above electronic component surface mounting substrate, a cavity for accommodating the semiconductor element 2 is formed on the surface of the insulating base 1 and the semiconductor element 2 is accommodated in the cavity. Although the height reduction can be promoted, there is a problem that the area of the substrate surface on which various electronic components can be mounted is reduced due to the occupation of the cavity, and the mounting efficiency of the electronic components is reduced.

【0009】特に2段キャビティを有する電子部品表面
実装用基板では、配線の接続に用いる最低限必要な電極
パッドの面積に対して、必要以上のキャビティ面積を占
有しなければならなかった。これは、従来のテープ積層
方式によって電極パッドのキャビティ(2段目凹部)を
形成する場合、パンチングにより形成するため、その形
状は円及び矩形等の単純形状としなければ形成不能であ
ったことによるものである。
In particular, in the case of an electronic component surface mounting substrate having a two-stage cavity, the cavity area must be occupied more than the minimum required electrode pad area used for wiring connection. This is because when forming the cavity (second concave portion) of the electrode pad by the conventional tape lamination method, the electrode pad is formed by punching, so that the shape cannot be formed unless it is a simple shape such as a circle and a rectangle. Things.

【0010】[0010]

【課題を解決するための手段】本発明の電子部品表面実
装用基板は、セラミックスからなる絶縁層を複数積層し
てなる絶縁基体と、該絶縁基体に形成された半導体素子
収容用のキャビティとを具備し、前記絶縁基体表面に電
子部品が実装される電子部品表面実装用基板において、
前記キャビティが、半導体素子が配置される矩形状の半
導体素子配置用凹部と、この半導体素子配置用凹部の対
向する辺からそれぞれ前記絶縁基体端に向けて延設さ
れ、かつ前記辺よりも短い辺を有する一対の電極パッド
形成用凹部とから構成されるものである。本発明のセラ
ミックスからなる絶縁層において、セラミックとはガラ
スセラミックも含む意味である。
According to the present invention, there is provided a substrate for mounting electronic parts on a surface, comprising: an insulating base formed by laminating a plurality of insulating layers made of ceramics; and a cavity formed in the insulating base for accommodating a semiconductor element. An electronic component surface mounting substrate comprising an electronic component mounted on the insulating substrate surface,
The cavity is a rectangular semiconductor element disposing recess in which a semiconductor element is arranged, and a side extending from an opposite side of the semiconductor element disposing recess toward the end of the insulating base, and shorter than the side. And a pair of electrode pad forming recesses having the following. In the insulating layer made of the ceramic of the present invention, the ceramic includes glass ceramics.

【0011】[0011]

【作用】本発明の電子部品表面実装用基板によれば、半
導体素子を配置する半導体素子配置用凹部と、この半導
体素子配置用凹部の対向する側に形成された電極パッド
形成用凹部とからなる十字状のキャビティを形成したの
で、コンデンサ等の電子部品を実装する基体の表面積を
大幅に拡大することが可能となる。
According to the electronic component surface mounting substrate of the present invention, the electronic component surface mounting substrate includes a semiconductor element arranging concave portion for arranging a semiconductor element and an electrode pad forming concave portion formed on an opposite side of the semiconductor element arranging concave portion. Since the cross-shaped cavity is formed, the surface area of the base on which electronic components such as capacitors are mounted can be greatly increased.

【0012】即ち、本発明は、キャビティを2段の階段
状に形成し、下段を半導体素子の固定部、上段を半導体
素子と絶縁基体との接続に用いる電極パッドの形成部と
した電子部品表面実装用基板であるが、上段のキャビテ
ィ形状が十字形状であるため、電極パッドの面積を必要
最小限に小さくすることが可能となり、絶縁基体表面の
キャビティの占める割合が最小となり、電子部品を実装
可能な表面積の割合が最大となり、より高密度な実装が
可能な電子部品表面実装用基板を提供することが可能と
なる。
That is, the present invention provides an electronic component surface in which a cavity is formed in two steps, and a lower part is a fixing part of a semiconductor element, and an upper part is a part for forming an electrode pad used for connection between the semiconductor element and an insulating base. Although it is a mounting substrate, since the upper cavity shape is a cross shape, the area of the electrode pad can be reduced to the minimum necessary, the ratio of the cavity on the surface of the insulating substrate is minimized, and electronic components are mounted. The ratio of the possible surface area is maximized, and it is possible to provide an electronic component surface mounting substrate capable of mounting at a higher density.

【0013】[0013]

【発明の実施の形態】本発明の電子部品表面実装用基板
を図1に示す。この図1において、符号11は絶縁基体
を示している。この絶縁基体11は、図2に示すよう
に、セラミックまたはガラスセラミックからなる4層の
絶縁層11a〜11dを積層して構成されており、これ
らの絶縁層11a〜11dの間には、内部配線12やビ
アホール導体13が形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a substrate for surface mounting electronic parts according to the present invention. In FIG. 1, reference numeral 11 indicates an insulating base. As shown in FIG. 2, this insulating base 11 is formed by laminating four insulating layers 11a to 11d made of ceramic or glass ceramic, and an internal wiring is provided between these insulating layers 11a to 11d. 12 and via-hole conductors 13 are formed.

【0014】そして、絶縁基体11には、図3に示すよ
うに、半導体素子14を収納する十字状のキャビティ1
5が形成されている。このキャビティ15は、図4およ
び図5に示すように、半導体素子14を収納配置する矩
形状の半導体素子配置用凹部16と、この半導体素子配
置用凹部16の対向する位置に形成された電極パッド形
成用凹部17とからなる十字形状とされ、電極パッド形
成用凹部17の底面は半導体素子配置用凹部16の底面
よりも高く形成されている。
As shown in FIG. 3, a cross-shaped cavity 1 for accommodating a semiconductor element 14 is provided in the insulating base 11.
5 are formed. As shown in FIGS. 4 and 5, the cavity 15 has a rectangular semiconductor element disposing recess 16 for housing and disposing the semiconductor element 14, and an electrode pad formed at a position facing the semiconductor element disposing recess 16. The concave portion 17 for forming an electrode pad is formed to have a cross shape, and the bottom surface of the concave portion 17 for forming an electrode pad is formed higher than the bottom surface of the concave portion 16 for placing a semiconductor element.

【0015】即ち、キャビティ15は、半導体素子14
が配置される矩形状の半導体素子配置用凹部16と、こ
の半導体素子配置用凹部16の対向する辺からそれぞれ
絶縁基体11端に向けて延設され、また導体素子配置用
凹部16の対向する辺よりも短い辺を有する一対の電極
パッド形成用凹部17とから構成されている。
That is, the cavity 15 is
Are arranged to extend from the opposing sides of the semiconductor element disposing recess 16 toward the end of the insulating base 11, and the opposing sides of the conductive element disposing recess 16 are arranged. And a pair of electrode pad forming recesses 17 having shorter sides.

【0016】電極パッド形成用凹部17の底面には、内
部配線12に接続されるワイヤボンディング用の電極パ
ッド19が形成され、図2に示したように、この電極パ
ッド19と半導体素子配置用凹部16の底面に固定され
た半導体素子14とがワイヤボンディング20により接
続されている。電極パッド19が形成される電極パッド
形成用凹部17の底面の面積は、ワイヤボンディングに
必要な最小限の面積があればよい。即ち、電極パッド形
成用凹部17の面積、形状は半導体素子14のサイズよ
り小さくすることが可能である。尚、ワイヤボンディン
グが可能であれば、より複雑な任意の形状とすることも
可能である。
An electrode pad 19 for wire bonding connected to the internal wiring 12 is formed on the bottom surface of the recess 17 for forming an electrode pad. As shown in FIG. The semiconductor element 14 fixed to the bottom surface of the semiconductor device 16 is connected by wire bonding 20. The area of the bottom surface of the electrode pad forming concave portion 17 in which the electrode pad 19 is formed may be a minimum area required for wire bonding. That is, the area and shape of the electrode pad forming recess 17 can be made smaller than the size of the semiconductor element 14. In addition, as long as wire bonding is possible, a more complicated arbitrary shape can be used.

【0017】絶縁基体11の表面には、図1に示したよ
うに、十字形状のキャビティ15が形成された部分以外
の表面には表面配線21が形成され、この表面配線21
には、チップコンデンサや抵抗器等の電子部品22が実
装されている。また、絶縁基体11の側面には入出力端
子、電源端子、グランド端子等の端子が端面電極23と
して示されている。
As shown in FIG. 1, a surface wiring 21 is formed on the surface of the insulating substrate 11 other than the portion where the cross-shaped cavity 15 is formed.
, An electronic component 22 such as a chip capacitor or a resistor is mounted. Terminals such as an input / output terminal, a power supply terminal, and a ground terminal are shown as end surface electrodes 23 on the side surface of the insulating base 11.

【0018】尚、理解を容易にするため、図2において
は、絶縁基体11表面に形成される電子部品については
省略した。図3においては電子部品および表面配線につ
いて省略し、図4および図5については半導体素子、電
子部品および表面配線について省略した。
In FIG. 2, electronic components formed on the surface of the insulating base 11 are omitted for easy understanding. In FIG. 3, the electronic components and the surface wiring are omitted, and in FIGS. 4 and 5, the semiconductor element, the electronic component and the surface wiring are omitted.

【0019】本発明の電子部品表面実装用基板の製造方
法は、セラミックスからなる絶縁層を複数積層してなる
絶縁基体と、表面に半導体素子を実装するためのキャビ
ティを有する電子部品表面実装用基板の製造方法であっ
て、以下の(a)〜(e)の工程を具備する方法により
作製される。
The method for manufacturing a surface mounting board for electronic parts according to the present invention is directed to a surface mounting board for electronic parts having a plurality of insulating layers made of ceramics and a cavity on the surface for mounting a semiconductor element. , Which is manufactured by a method including the following steps (a) to (e).

【0020】(a)セラミックスからなる絶縁層材料、
光硬化可能なモノマー、有機バインダを含有するスリッ
プ材を作製する工程 (b)前記スリップ材を薄層化し乾燥して絶縁層成形体
を形成する工程 (c)該絶縁層成形体に露光処理を施し硬化させる工程 (d)(c)工程で得られた絶縁層成形体に(b)
(c)工程を順次繰り返して絶縁層成形体が複数積層さ
れた積層成形体を作製するとともに、(b)工程で得ら
れた絶縁層成形体に対して、露光現像処理して半導体素
子配置用凹部を形成する位置に貫通孔を形成し、該貫通
孔に光硬化または熱硬化可能な樹脂ペーストを充填し、
硬化する工程の後、前記スリップ材を薄層化し乾燥して
絶縁層成形体を形成し、電極パッド形成用凹部および半
導体素子配置用凹部を形成する位置に貫通孔を形成し、
該貫通孔に前記樹脂ペーストを充填し硬化して、樹脂ペ
ーストが充填されたキャビティを有する積層成形体を作
製する工程 (e)積層成形体を焼成する工程 尚、上記工程では、内部配線、ビアホール導体の形成に
ついては省略したが、必要に応じて形成する必要があ
る。内部配線は、露光処理後の絶縁層成形体に導電性ペ
ーストを塗布することにより、また、ビアホール導体
は、スリップを薄層化し、乾燥した絶縁層成形体に、ビ
アホールの形成位置に露光現像処理しビアホール用の貫
通孔を作製し、この貫通孔に導電性ペーストを充填する
ことにより形成できる。
(A) an insulating layer material made of ceramics,
Step (b) of forming a slip material containing a photocurable monomer and an organic binder; (b) thinning and drying the slip material to form an insulating layer molded product; and (c) subjecting the insulating layer molded product to exposure treatment. Step of applying and curing (b) Applying (b)
The step (c) is sequentially repeated to produce a laminated molded article in which a plurality of insulating layer molded articles are laminated, and the insulating layer molded article obtained in the step (b) is subjected to exposure and development processing to form a semiconductor element arrangement. Form a through-hole at the position where the recess is formed, fill the through-hole with a photo-curable or thermo-curable resin paste,
After the curing step, the slip material is thinned and dried to form an insulating layer molded body, a through hole is formed at a position where a concave portion for forming an electrode pad and a concave portion for forming a semiconductor element are formed,
A step of filling the through-hole with the resin paste and curing to form a laminated molded body having a cavity filled with the resin paste; and (e) a step of firing the laminated molded body. Although the formation of the conductor is omitted, it is necessary to form the conductor as needed. For the internal wiring, a conductive paste is applied to the insulating layer molded body after the exposure processing, and for the via hole conductor, the slip is thinned, and the dried insulating layer molded body is exposed and developed at the via hole forming position. A via hole can be formed by forming a through hole and filling the through hole with a conductive paste.

【0021】本発明の電子部品表面実装用基板の製造方
法について具体的に説明する。先ず、絶縁層となるスリ
ップ材は、ガラスセラミックまたはセラミック材料、光
硬化可能なモノマー、有機バインダと、有機溶剤を均質
混練して得られた溶剤系のスリップ材である。
The method of manufacturing the electronic component surface mounting board of the present invention will be specifically described. First, the slip material serving as the insulating layer is a solvent-based slip material obtained by homogeneously kneading a glass ceramic or ceramic material, a photocurable monomer, an organic binder, and an organic solvent.

【0022】また850〜1050℃で焼成されるいわ
ゆる低温焼成セラミックスを複合回路ブロックとして用
いる場合においては、絶縁層には、セラミック材料とガ
ラス材料(両者を合わせて固形成分という)を一般的に
用いる。
When a so-called low-temperature fired ceramic fired at 850 to 1050 ° C. is used as a composite circuit block, a ceramic material and a glass material (both are called solid components) are generally used for the insulating layer. .

【0023】スリップ材は、例えば、ガラス材料である
SiO2 、Al2 3 、ZnO、MgO、B2 3 を主
成分とする結晶化ガラス粉末70重量%とセラミック材
料であるアルミナ粉末30重量%とからなるセラミック
原料粉末と、光硬化可能なモノマー、例えばポリオキシ
エチル化トリメチロールプロパントリアクリレートと、
有機バインダ、例えばアルキルメタクリレートと、可塑
剤とを、有機溶剤、例えばエチルカルビトールアセテー
トに混合し、ボールミルで約48時間混練して作製され
る。
The slip material is, for example, 70% by weight of a crystallized glass powder mainly composed of glass materials SiO 2 , Al 2 O 3 , ZnO, MgO and B 2 O 3 and 30% by weight of alumina powder as a ceramic material % Of a ceramic raw material powder, and a photocurable monomer such as polyoxyethylated trimethylolpropane triacrylate,
An organic binder, for example, an alkyl methacrylate, and a plasticizer are mixed with an organic solvent, for example, ethyl carbitol acetate, and kneaded in a ball mill for about 48 hours.

【0024】尚、上述の実施例では溶剤系スリップ材を
作製しているが、上述のように親水性の官能基を付加し
た光硬化可能なモノマー、例えば多官能基メタクリレー
トモノマー、有機バインダ、例えばカルボキシル変性ア
ルキルメタクリレートを用いて、イオン交換水で混練し
た水系スリップ材を作成しても構わない。
In the above embodiment, a solvent-based slip material is prepared. However, as described above, a photocurable monomer having a hydrophilic functional group added thereto, for example, a polyfunctional methacrylate monomer, an organic binder, for example, An aqueous slip material kneaded with ion-exchanged water may be prepared by using a carboxyl-modified alkyl methacrylate.

【0025】セラミック原料粉末としては、金属元素と
して少なくともMg、Ti、Caを含有する複合酸化物
であって、その金属元素酸化物による組成式を(1−
x)MgTiO3 −xCaTiO3 (但し、式中xは重
量比を表し、0.01≦x≦0.15)で表される主成
分100重量部に対して、硼素含有化合物をB2 3
算で3〜30重量部、アルカリ金属含有化合物をアルカ
リ金属炭酸塩換算で1〜25重量部添加含有してなるも
のであっても良い。
The ceramic raw material powder is a composite oxide containing at least Mg, Ti, and Ca as metal elements.
x) MgTiO 3 -xCaTiO 3 (where x represents a weight ratio and 0.01 ≦ x ≦ 0.15), and 100 parts by weight of the main component represented by B 2 O 3 3 to 30 parts by weight in terms of conversion, and 1 to 25 parts by weight of an alkali metal-containing compound in terms of alkali metal carbonate may be added.

【0026】また、内部配線12、ビアホール導体13
となる導電性ペーストを作成する。
The internal wiring 12 and the via-hole conductor 13
A conductive paste is prepared.

【0027】導電性ペーストは、低融点で且つ低抵抗の
金属材料である例えば銀粉末と、硼珪酸系低融点ガラ
ス、例えばB2 3 −SiO2 −BaOガラス、CaO
−B2 3 −SiO2 ガラス、CaO−Al2 3 −B
2 3 −SiO2 ガラスと、有機バインダ、例えばエチ
ルセルロースとを、有機溶剤、例えば2,2,4−トリ
メチル−1,3−ペンタジオールモノイソブチレートに
混合し、3本ローラーにより均質混練して作成される。
The conductive paste is a metal material having a low melting point and low resistance, such as silver powder, and a borosilicate low melting point glass, such as B 2 O 3 —SiO 2 —BaO glass, CaO
-B 2 O 3 -SiO 2 glass, CaO-Al 2 O 3 -B
2 O 3 —SiO 2 glass and an organic binder, for example, ethyl cellulose, are mixed with an organic solvent, for example, 2,2,4-trimethyl-1,3-pentadiol monoisobutyrate, and homogenously kneaded with three rollers. Created.

【0028】また、表面配線21となる導体材料の導電
性ペーストは、銀系合金または銅のうち少なくとも1つ
の金属材料の粉末と、低融点ガラス成分と、有機バイン
ダ及び有機溶剤とを均質混練したものが好適に使用され
る。内部配線及びビアホール導体となる導体材料の導電
性ペーストは表面配線のものと同様でもかまわないし、
銀を主成分としたものでもかまわない。これらは、特に
焼成温度が850〜1050℃であるため、金属材料と
しては、比較的低融点であり、且つ低抵抗材料が選択さ
れ、また、低融点ガラス成分も、絶縁層となる絶縁層成
形体(スリップ材を塗布、乾燥したもの)との焼結挙動
を考慮して、その屈伏点が700℃前後となるものが使
用される。
The conductive paste of the conductive material to be the surface wiring 21 is obtained by homogeneously kneading a powder of at least one metal material of a silver alloy or copper, a low-melting glass component, an organic binder and an organic solvent. Are preferably used. The conductive paste of the conductor material to be the internal wiring and via-hole conductor may be the same as that of the surface wiring,
A material containing silver as a main component may be used. Since these materials have a firing temperature of 850 to 1050 ° C. in particular, a metal material having a relatively low melting point and a low resistance material is selected. Taking into account the sintering behavior with a body (one coated with a slip material and dried), one having a deformation point of about 700 ° C. is used.

【0029】次に、図6(a)に示すように、上述の表
面配線21となる導電性ペーストを支持基板24表面に
塗布し、乾燥し導電部材25を形成する。この後、上述
のスリップ材を上記導電部材25を被覆するように塗布
し乾燥を行い、最下層となる絶縁層成形体26aを形成
する。具体的には、まず、支持基板24の導電部材25
上に、上述のスリップ材をドクターブレード法によって
塗布した後乾燥して、焼成後の絶縁層11a〜11dの
最下層である絶縁層11aとなる絶縁層成形体26aを
形成する。
Next, as shown in FIG. 6A, a conductive paste for forming the above-mentioned surface wiring 21 is applied to the surface of the support substrate 24 and dried to form a conductive member 25. Thereafter, the above-mentioned slip material is applied so as to cover the above-mentioned conductive member 25 and dried to form the lowermost insulating layer molded body 26a. Specifically, first, the conductive member 25 of the support substrate 24
The above-mentioned slip material is applied thereon by a doctor blade method and then dried to form an insulating layer molded body 26a to be the lowermost insulating layer 11a of the fired insulating layers 11a to 11d.

【0030】ここで、支持基板24としては、マイラー
フイルムを用い、焼成工程前に取り外される。塗布後の
乾燥条件は、60〜80℃で20分乾燥であり、薄層化
・乾燥された絶縁層成形体26aの厚みは120μmで
ある。
Here, a mylar film is used as the support substrate 24, which is removed before the firing step. Drying conditions after the application are drying at 60 to 80 ° C. for 20 minutes, and the thickness of the thinned and dried insulating layer molded body 26a is 120 μm.

【0031】絶縁層11aには、ピアホール導体13が
形成されているため、図6(b)に示すように、絶縁層
成形体26aに露光現像処理によりビアホールを作製す
る。
Since the peer-hole conductor 13 is formed in the insulating layer 11a, as shown in FIG. 6B, a via hole is formed in the insulating layer molded body 26a by exposure and development.

【0032】露光処理は、例えば、フォトターゲットを
絶縁層成形体26a上に近接または載置して、ビアホー
ルを形成する位置以外の領域に、低圧、高圧、超高圧の
水銀灯系の露光光を照射する。これにより、ビアホール
以外の領域では、光硬化可能なモノマーが光重合反応を
起こす。従って、ビアホール部分のみが現像処理によっ
て除去可能な溶化部となる。
In the exposure process, for example, a photo target is brought close to or placed on the insulating layer molded body 26a, and a region other than the position where a via hole is formed is irradiated with exposure light of a low-pressure, high-pressure, or ultra-high pressure mercury lamp. I do. As a result, in a region other than the via hole, the photocurable monomer causes a photopolymerization reaction. Therefore, only the via hole portion becomes a solubilized portion that can be removed by the development processing.

【0033】具体的には、露光処理は、絶縁層成形体2
6a上にビアホールが形成される領域が遮光されるよう
なフォトターゲットを載置して、超高圧水銀灯(10m
W/cm2 )を光源として用いて露光を行なう。
Specifically, the exposure treatment is performed on the insulating layer molded body 2
6a, a photo target is placed such that a region where a via hole is to be formed is shielded from light, and an ultra-high pressure mercury lamp (10 m
(W / cm 2 ) as a light source.

【0034】これにより、ビアホールが形成される領域
の絶縁層成形体26aにおいては光硬化可能なモノマの
光重合反応がおこらず、ビアホールが形成される領域以
外の絶縁層成形体26aにおいては、光重合反応が起こ
る。ここで光重合反応が起こった部位を不溶化部とい
い、光重合反応が起こらない部位を溶化部という。尚、
120μm程度の絶縁層成形体は、超高圧水銀灯(10
mW/cm2 )を20〜30秒程度照射すれば露光を行
うことができる。
As a result, the photopolymerization reaction of the photocurable monomer does not occur in the insulating layer molded body 26a in the region where the via hole is formed, and the light is not cured in the insulating layer molded body 26a other than the region where the via hole is formed. A polymerization reaction occurs. Here, the part where the photopolymerization reaction has occurred is called an insolubilized part, and the part where the photopolymerization reaction does not occur is called a solubilized part. still,
An insulating layer molded body having a thickness of about 120 μm is formed of an ultra-high pressure mercury lamp
mW / cm 2 ) for about 20 to 30 seconds, the exposure can be performed.

【0035】現像処理は、クロロセン等の溶剤を例えば
スプレー現像法やパドル現像法によって、絶縁層成形体
26aである露光溶化部に接触させ、現像を行う。その
後、必要に応じて洗浄及び乾燥を行なう。現像処理は、
絶縁層成形体26aの溶化部を現像液で除去するもの
で、具体的には1,1,1−トリクロロエタンをスプレ
ー法で現像を行う。
In the developing treatment, a solvent such as chlorocene is brought into contact with the exposed and solubilized portion as the insulating layer molded body 26a by, for example, a spray developing method or a paddle developing method to perform development. Thereafter, washing and drying are performed as necessary. The development process is
This is for removing the solubilized portion of the insulating layer molded body 26a with a developing solution. Specifically, 1,1,1-trichloroethane is developed by a spray method.

【0036】この現像処理により、絶縁層成形体26a
にビアホールの場合は直径100〜200μmの大きさ
の貫通孔を形成することができる。その後、絶縁層成形
体26aを現像によって生じる不要なカスなどを洗浄、
乾燥工程により完全に除去する。
By this developing treatment, the insulating layer molded body 26a
In the case of a via hole, a through hole having a diameter of 100 to 200 μm can be formed. After that, unnecessary debris or the like generated by developing the insulating layer molded body 26a is washed,
It is completely removed by a drying step.

【0037】次に、ビアホール用貫通孔に導体ペースト
を充填し、乾燥する。具体的には、上述の工程で形成し
たビアホール用貫通孔に上述の導電性ペーストを充填
し、乾燥する。ビアホール用貫通孔に相当する部位のみ
に印刷可能なスクリーンを用いる印刷によって、ビアホ
ール導体13となる導電部材27を形成し、その後、5
0℃・10分乾燥する。
Next, the conductive paste is filled in the through holes for via holes and dried. Specifically, the conductive paste is filled in the through-hole for a via hole formed in the above-described process, and dried. The conductive member 27 to be the via-hole conductor 13 is formed by printing using a screen that can be printed only on the portion corresponding to the via-hole through-hole.
Dry at 0 ° C for 10 minutes.

【0038】次に、内部配線12となるパターンを印刷
・乾燥を行う。具体的には、図6(b)に示したように
絶縁層10aと絶縁層10bとの間に配置される内部配
線12となる内部配線パターン28をスクリーン印刷法
にて形成し、乾燥を行う。
Next, a pattern to be the internal wiring 12 is printed and dried. Specifically, as shown in FIG. 6B, an internal wiring pattern 28 that is to be the internal wiring 12 disposed between the insulating layer 10a and the insulating layer 10b is formed by a screen printing method, and dried. .

【0039】そして、前述した絶縁層成形体26aの形
成から、内部配線パターン28の形成までの工程を繰り
返す。このようにして、図6(c)に示すように、絶縁
層成形体26bを積層し、導電部材27と内部配線パタ
ーン28を形成する。
Then, the steps from the formation of the insulating layer molded body 26a to the formation of the internal wiring pattern 28 are repeated. In this way, as shown in FIG. 6C, the insulating layer molded body 26b is laminated, and the conductive member 27 and the internal wiring pattern 28 are formed.

【0040】この後、図6(d)に示すように、絶縁層
成形体26bの表面に絶縁層成形体26cを形成し、露
光現像処理によりビアホールとなる貫通孔および半導体
素子配置用凹部16となる開口部30を形成する。この
後、ビアホールとなる貫通孔に導電性ペーストを充填す
るとともに、開口部30に熱硬化性樹脂または光硬化性
樹脂を充填し、硬化させる。
Thereafter, as shown in FIG. 6D, an insulating layer formed body 26c is formed on the surface of the insulating layer formed body 26b, and a through hole serving as a via hole and a recess 16 for arranging semiconductor elements are formed by exposure and development processing. Opening 30 is formed. Thereafter, a conductive paste is filled into the through-hole serving as a via hole, and a thermosetting resin or a photocurable resin is filled into the opening 30 and cured.

【0041】この後、図6(e)に示すように、絶縁層
成形体26cの表面および開口部30の表面に絶縁層成
形体26dを形成し、露光現像処理によりビアホールと
なる貫通孔および電極パッド形成用凹部17および半導
体素子配置用凹部16となる開口部33を形成する。こ
の後、ビアホールとなる貫通孔に導電性ペーストを充填
するとともに、開口部33に熱硬化性樹脂または光硬化
性樹脂からなる樹脂31を充填し、硬化させる。
Thereafter, as shown in FIG. 6E, an insulating layer formed body 26d is formed on the surface of the insulating layer formed body 26c and on the surface of the opening 30, and through holes and electrodes serving as via holes are formed by exposure and development processing. An opening 33 to be the pad forming recess 17 and the semiconductor element disposing recess 16 is formed. Thereafter, a conductive paste is filled into the through-holes serving as via holes, and a resin 31 made of a thermosetting resin or a photo-setting resin is filled into the openings 33 and cured.

【0042】そして、この絶縁層成形体26dの表面に
表面配線21となる導電性ペーストを塗布し、乾燥する
ことにより、積層成形体が作製される。
Then, a conductive paste to be the surface wiring 21 is applied to the surface of the insulating layer formed body 26d, and dried to produce a laminated formed body.

【0043】次に、必要に応じて、積層成形体の形状を
プレスで整え、分割溝を形成し、支持基板24を取り外
す。
Next, if necessary, the shape of the laminated molded product is adjusted by pressing, a dividing groove is formed, and the support substrate 24 is removed.

【0044】次に、焼成を行う。焼成は、脱バインダ工
程と、本焼成工程からなる。脱バインダ工程は、概ね6
00℃以下の温度領域であり、絶縁層成形体26a〜2
6d及び内部配線パターン28、導電部材27に含まれ
ている有機バインダ、光硬化可能なモノマ、開口部3
0、33に充填された樹脂31を消失する過程であり、
本焼成工程は、ピーク温度850〜1050℃、例え
ば、900℃30分ピークの焼成過程であり、絶縁層と
なる絶縁層成形体26a〜26dおよび内部配線パター
ン28、端面電極23、ビアホール導体13となる導電
部材27を一括的に焼成することにより、本発明の電子
部品表面実装用基板が作製される。
Next, firing is performed. The firing includes a binder removing step and a main firing step. The binder removal process is roughly 6
The temperature range is not higher than 00 ° C.
6d, internal wiring pattern 28, organic binder contained in conductive member 27, photo-curable monomer, opening 3
This is a process of erasing the resin 31 filled in 0, 33,
The main baking process is a baking process with a peak temperature of 850 to 1050 ° C., for example, a peak of 900 ° C. for 30 minutes. By firing the conductive member 27 collectively, the electronic component surface mounting substrate of the present invention is manufactured.

【0045】その後、表面処理として、さらに、厚膜抵
抗膜や厚膜保護膜の印刷・焼きつけ、メッキ処理、さら
に半導体素子を含む電子部品の接合を行う。そして、こ
の後、分割溝に沿って分割することにより、図1に示し
たような電子部品表面実装用基板が得られる。
Thereafter, as a surface treatment, printing and baking of a thick-film resistive film and a thick-film protective film, plating, and bonding of electronic components including semiconductor elements are further performed. After that, by dividing the substrate along the dividing grooves, the electronic component surface mounting substrate as shown in FIG. 1 is obtained.

【0046】本発明の電子部品表面実装用基板によれ
ば、半導体素子14を配置する半導体素子配置用凹部1
6と、この半導体素子配置用凹部16の底面よりも高い
底面を有する電極パッド形成用凹部17とからなる十字
状のキャビティ15を形成したので、絶縁基体11表面
のキャビティ15の占める割合が最小となり、電子部品
22を実装可能な表面積の割合が最大となり、より高密
度な実装が可能な電子部品表面実装用基板を提供するこ
とができる。つまり、従来においては図3に一点鎖線で
示したキャビティが必要であったが、本発明においては
実線で示す通りキャビティを小さくできる。
According to the electronic component surface mounting substrate of the present invention, the semiconductor element disposing recess 1 in which the semiconductor element 14 is disposed
6 and the concave portion 17 for forming an electrode pad having a bottom surface higher than the bottom surface of the concave portion 16 for arranging the semiconductor element, the cross-shaped cavity 15 is formed, so that the proportion of the cavity 15 on the surface of the insulating substrate 11 is minimized. In addition, the ratio of the surface area on which the electronic component 22 can be mounted is maximized, and it is possible to provide an electronic component surface mounting substrate that can be mounted at a higher density. That is, in the related art, the cavity shown by the one-dot chain line in FIG. 3 was necessary, but in the present invention, the cavity can be made smaller as shown by the solid line.

【0047】また、上記のような製造方法によれば、ビ
アホールやキャビティ用貫通溝がフォトターゲットを用
いて、露光・現像処理によって作製されるため、フォト
ターゲットのパターンによっても、種々の大きさのもの
が形成され、従来の製造方法、即ち、金型やNCパンチ
の打ち抜きでは得ることができない形状で且つ相対位置
精度の高い貫通穴の形成が可能であり、十字状のキャビ
ティを有する本発明の電子部品表面実装用基板を容易に
作製できる。
Further, according to the above-described manufacturing method, the via holes and the through-holes for the cavities are formed by exposure and development using a photo target. The present invention has a cross-shaped cavity having a shape that cannot be obtained by a conventional manufacturing method, that is, punching of a mold or an NC punch, and having high relative positional accuracy. A substrate for electronic component surface mounting can be easily manufactured.

【0048】さらに、絶縁層となるスリップ材の塗布に
より絶縁層成形体が形成されるため、絶縁層成形体の表
面が、内部配線の配線パターンの積層状態にかかわら
ず、常に平面状態を維持でき、絶縁層成形体上に配線パ
ターンを形成するにあたって、非常に精度が高くなる。
Furthermore, since the insulating layer molded body is formed by applying the slip material to be the insulating layer, the surface of the insulating layer molded body can always maintain a flat state regardless of the lamination state of the wiring pattern of the internal wiring. In forming the wiring pattern on the insulating layer molded body, the accuracy becomes extremely high.

【0049】上述の実施例では、内部配線12として、
Au系、Ag系、Cu系の低融点金属材料を用いた低温
焼成のセラミック基板の製造方法で説明したが、内部配
線12として、タングステン、モリブデンなどの高融点
金属材料を用いた、1300℃前後で焼成されるセラミ
ック基板に、本発明の製造方法を適用しても構わない。
この場合、スリップ材のガラス材料の組成を所定成分と
し、さらにセラミック材料との混合比率を所定に設定す
る必要がある。
In the above embodiment, the internal wiring 12 is
The method of manufacturing a low-temperature sintering ceramic substrate using Au-based, Ag-based, and Cu-based low-melting metal materials has been described. The manufacturing method of the present invention may be applied to a ceramic substrate fired in the above.
In this case, it is necessary to set the composition of the glass material of the slip material as a predetermined component, and further set the mixing ratio with the ceramic material to a predetermined value.

【0050】[0050]

【発明の効果】本発明によれば、半導体素子を配置する
半導体素子配置用凹部と、この半導体素子配置用凹部の
底面よりも高い底面を有する電極パッド形成用凹部とか
らなる十字状のキャビティを形成したので、コンデンサ
等の電子部品を実装する基体の表面積を大幅に拡大する
ことができる。
According to the present invention, a cross-shaped cavity comprising a semiconductor element disposing recess for disposing a semiconductor element and an electrode pad forming recess having a bottom surface higher than the bottom surface of the semiconductor element disposing recess is formed. As a result, the surface area of the substrate on which electronic components such as capacitors are mounted can be greatly increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の電子部品表面実装用基板に半導体素子
を搭載した斜視図である。
FIG. 1 is a perspective view in which a semiconductor element is mounted on an electronic component surface mounting substrate of the present invention.

【図2】図1の断面図である。FIG. 2 is a sectional view of FIG.

【図3】図1の平面図である。FIG. 3 is a plan view of FIG. 1;

【図4】図3のA−A線に沿う断面図である。FIG. 4 is a sectional view taken along line AA of FIG. 3;

【図5】図3のB−B線に沿う断面図である。FIG. 5 is a sectional view taken along the line BB in FIG. 3;

【図6】本発明の電子部品表面実装用基板の製造方法を
説明するための工程図である。
FIG. 6 is a process chart for explaining the method for manufacturing an electronic component surface mounting board of the present invention.

【図7】従来の電子部品表面実装用基板に半導体素子を
搭載した斜視図である。
FIG. 7 is a perspective view in which a semiconductor element is mounted on a conventional electronic component surface mounting substrate.

【図8】図7のC−C線に沿う断面図である。FIG. 8 is a sectional view taken along line CC of FIG. 7;

【符号の説明】[Explanation of symbols]

11・・・絶縁基体 11a〜11d・・・絶縁層 12・・・内部配線 13・・・ビアホール導体 14・・・半導体素子 15・・・キャビティ 16・・・半導体素子配置用凹部 17・・・電極パッド形成用凹部 19・・・電極パッド 20・・・ワイヤボンディング 22・・・電子部品 DESCRIPTION OF SYMBOLS 11 ... Insulating base 11a-11d ... Insulating layer 12 ... Internal wiring 13 ... Via-hole conductor 14 ... Semiconductor element 15 ... Cavity 16 ... Semiconductor element arrangement recessed part 17 ... Electrode pad forming recess 19: electrode pad 20: wire bonding 22: electronic component

フロントページの続き (72)発明者 中宮 道信 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内 (72)発明者 榎並 信一 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内Continuing from the front page (72) Inventor Michinobu Nakamiya 1-4 Yamashita-cho, Kokubu-shi, Kagoshima Inside the Kyocera Research Institute (72) Inventor Shin-ichi Enami 1-4-1 Yamashita-cho, Kokubu-shi, Kagoshima Kyocera Corporation Inside the company research institute

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】セラミックスからなる絶縁層を複数積層し
てなる絶縁基体と、該絶縁基体に形成された半導体素子
収容用のキャビティとを具備し、前記絶縁基体表面に電
子部品が実装される電子部品表面実装用基板において、
前記キャビティが、半導体素子が配置される矩形状の半
導体素子配置用凹部と、この半導体素子配置用凹部の対
向する辺からそれぞれ前記絶縁基体端に向けて延設さ
れ、かつ前記辺よりも短い辺を有する一対の電極パッド
形成用凹部とから構成されることを特徴とする電子部品
表面実装用基板。
An electronic device comprising: an insulating base formed by laminating a plurality of insulating layers made of ceramics; and a cavity formed in the insulating base for accommodating a semiconductor element, wherein an electronic component is mounted on the surface of the insulating base. In the component surface mounting board,
The cavity is a rectangular semiconductor element disposing recess in which a semiconductor element is arranged, and a side extending from an opposite side of the semiconductor element disposing recess toward the end of the insulating base, and shorter than the side. And a pair of concave portions for forming an electrode pad, comprising: a substrate for mounting electronic components;
JP30093697A 1997-10-31 1997-10-31 Electronic component surface mounting substrate Expired - Fee Related JP3563577B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30093697A JP3563577B2 (en) 1997-10-31 1997-10-31 Electronic component surface mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30093697A JP3563577B2 (en) 1997-10-31 1997-10-31 Electronic component surface mounting substrate

Publications (2)

Publication Number Publication Date
JPH11135680A true JPH11135680A (en) 1999-05-21
JP3563577B2 JP3563577B2 (en) 2004-09-08

Family

ID=17890898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30093697A Expired - Fee Related JP3563577B2 (en) 1997-10-31 1997-10-31 Electronic component surface mounting substrate

Country Status (1)

Country Link
JP (1) JP3563577B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006523964A (en) * 2003-04-18 2006-10-19 フリースケール セミコンダクター インコーポレイテッド At least partially packaged circuit device and method of forming the same
JP2008130618A (en) * 2006-11-16 2008-06-05 Murata Mfg Co Ltd Multilayer wiring board
JP2013070009A (en) * 2011-09-23 2013-04-18 Samsung Electro-Mechanics Co Ltd Printed circuit board and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006523964A (en) * 2003-04-18 2006-10-19 フリースケール セミコンダクター インコーポレイテッド At least partially packaged circuit device and method of forming the same
US8072062B2 (en) 2003-04-18 2011-12-06 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
JP2008130618A (en) * 2006-11-16 2008-06-05 Murata Mfg Co Ltd Multilayer wiring board
JP2013070009A (en) * 2011-09-23 2013-04-18 Samsung Electro-Mechanics Co Ltd Printed circuit board and method for manufacturing the same

Also Published As

Publication number Publication date
JP3563577B2 (en) 2004-09-08

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