JPH1065128A - Semiconductor substrate and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate which is suitable for a high withstand voltage power IC. SOLUTION: In a semiconductor substrate of the structure in which the first insulating layer 5 formed on a semiconductor substrate 1 and the second insulating layer 7 formed on a semiconductor layer 3 are laminated, so that a layer 7A which has a wet-etching rate when wet-etching is conducted using an ammonium fluoride solution, lower than the second insulating layer 7, is formed on the surface of the second insulating layer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor substrate having an SOI structure and a method of manufacturing the same, and more particularly, to a semiconductor substrate suitable for a high-voltage power IC and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the increase in speed and integration of LSI, semiconductors (usually,
Si is used. The SOI technology (Silicon on Insulator, or semiconductor on Insulator when a semiconductor other than Si is used) for forming a single-crystal thin film of (1) has attracted attention.

For example, the following technology is used as an element isolation technology for a high-voltage power IC in which a high-voltage power element and a control element are monolithically integrated.

FIG. 4 is a cross-sectional view showing an element isolation structure using the SOI technique. As shown in FIG.
The active layer 3 is formed on the buried oxide film 9 on the base substrate 1, and a part of the active layer 3 is removed by etching, and the removed portion is filled with the oxide film 11. According to this element structure, a desired element is formed on each of the plurality of island-shaped active layers 13 separated by the oxide film 11 and each element is completely electrically separated, thereby increasing the dielectric strength. Parasitic capacitance between elements can be reduced. Also, as shown in FIG. 3B, the island-shaped active layer 13 may be formed in a mesa shape. Further, FIG.
FIG. 4 is a cross-sectional view of a case where a high-breakdown-voltage power element and a control element are monolithically integrated using the element isolation structure shown in FIG. A lateral power MOSFET (Metal Oxide Semiconductor Fiel) which is a high breakdown voltage power element is formed in the island-shaped active layer 13.
d Effect Transistor) 15 and CMOS as control element
T (Complementary Metal Oxide Semiconductor Transi
(stor) 17 is formed.

When the element isolation structure using the SOI technique is applied to the element isolation of a high-breakdown-voltage power IC as described above, it is necessary to increase the thickness of the buried oxide film 9 to some extent. This is because a high voltage is applied to the high-breakdown-voltage power element, so that the depletion layer of the diffusion layer expands greatly. Therefore, the depletion layer reaches the bottom surface of the active layer 3 (the surface on the base substrate 1 side). As a result, the high voltage may be applied to the buried oxide film 9 in some cases. At this time, if the buried oxide film 9 is too thin, it cannot withstand the high electric field.
As a result, it may be destroyed.

Next, a method for manufacturing a semiconductor substrate having the above-described SOI structure (hereinafter, referred to as “SOI substrate”) will be described with reference to the drawings. FIG. 6 is a process chart for explaining a method for manufacturing the SOI substrate. The same parts as those in FIG. 4 are denoted by the same reference numerals.

First, as shown in FIG. 6A, an oxide film 7 is formed on one main surface of an active layer substrate 3 to be an active layer later. The oxide film 7 becomes the buried oxide film 9 shown in FIG.

[0008] Next, as shown in FIG.
Is mirror-polished to one principal surface (joining surface).

Finally, as shown in FIG. 6C, the active layer substrate 3 and the base substrate 1 are bonded together by thermocompression bonding with the respective bonding surfaces facing each other. Then, the other main surface of the active layer substrate 3 is mirror-polished until it has a predetermined thickness.

Although it is possible to form the SOI substrate in this manner, as described above, the buried oxide film 9 is formed.
Since the oxide film 7 needs to have a certain thickness, the above-described manufacturing method in which the oxide film 7 is formed only on the active layer substrate 3 requires an extremely long oxidation time when the oxide film 7 is formed. As a result, the production efficiency is very poor, and the cost may be increased.

On the other hand, there is the following second manufacturing method as a method for avoiding the disadvantages of the first manufacturing method. FIG. 7 is a process chart for explaining a second method for manufacturing the SOI substrate. The same parts as those in FIG. 4 are denoted by the same reference numerals.

First, as shown in FIG. 7A, an oxide film 7 is formed on one main surface of an active layer substrate 3 to be an active layer later. Here, since the buried oxide film 9 shown in FIG. 4 is composed of the oxide film 7 and the oxide film 5 described later, the thickness of the oxide film 7 can be smaller than that of the above-described manufacturing method, and therefore, the oxidation time can be reduced. can do.

Next, as shown in FIG.
An oxide film 9 is formed on one main surface of the substrate.

Finally, as shown in FIG. 7C, the active layer substrate 3 and the base substrate 1 are bonded together by thermocompression bonding with their bonding surfaces facing each other. Then, the other main surface of the active layer substrate 3 is mirror-polished until it has a predetermined thickness.

As described above, according to the second manufacturing method, an oxide film is formed on each of the base substrate and the active layer substrate.
Since they are combined to form a thick buried oxide film, each oxidation time is shortened, thereby improving production efficiency and suppressing an increase in cost. For this reason,
It is believed that such a second manufacturing method will become mainstream.

However, the SOI substrate formed by the second manufacturing method has the following problems. Less than,
Such a problem will be described with reference to the drawings.

FIG. 8 is a process chart for explaining a method of actually forming an element isolation structure using the SOI substrate formed by the manufacturing method shown in FIG. The same parts as those in FIG. 4 are denoted by the same reference numerals.

First, as shown in FIG.
An oxide film 19 to be an etching mask later is formed on the surface of the substrate. Then, a resist pattern 21 is formed on the oxide film 19 by a normal photolithography technique, and the oxide film 19 is etched by a normal etching technique using the resist pattern 21 as a mask to pattern the oxide film 19.

Next, as shown in FIG. 8B, after the resist pattern 21 is removed, the active layer 3 is trench-etched by a usual etching technique using the oxide film 19 as a mask to form a plurality of island-shaped active layers. 13 is formed.

Finally, as shown in FIG. 8C, after removing the oxide film 19, the oxide film 2 is formed on the side wall of the island-shaped active layer 13.
Then, polysilicon 25 is buried in the trench for flattening the substrate surface.

In this manner, the above-described device isolation structure can be formed. However, at the corner portion (the portion indicated by a in the figure) of the island-like active layer 13 in FIG. In order to suppress the occurrence, the following processing is actually performed. FIG. 9 is a process diagram for explaining a process of avoiding crystal defects at the corners of the active layer, which is intended to relieve stress by etching and rounding the corners of the active layer. It is.

First, as shown in FIG. 9A, the buried oxide film is wet-etched with an ammonium fluoride solution or the like in order to expose a corner portion of the island-shaped active layer 13 on the buried oxide film side.

Next, as shown in FIG. 9B, the corners of the island-shaped active layer 13 are rounded by chemical dry etching (CDE) (points indicated by b in the figure). Then, as described with reference to FIG. 8C, the island-shaped active layer 1 is formed.
An oxide film 23 is formed on the side wall of the gate electrode 3 and polysilicon 25 is buried in a trench for planarization of the substrate surface, thereby completing an element isolation structure.

[0024]

However, the following problem arises when an inter-element isolation structure subjected to the above-described crystal defect avoidance processing is formed on the conventional SOI substrate shown in FIG.

As shown in FIG. 10, when the buried oxide film is wet-etched in order to expose a corner of the island-shaped active layer 13 on the buried oxide film side, the amount of etching is such that the buried oxide film is formed. When the buried oxide film reaches the interface with the oxide film 5 of the base substrate 1 on which the buried oxide film is formed in the same manner as the oxide film 7 of the active layer, the etching of the buried oxide film proceeds along this interface (c in the figure). Therefore, there is a possibility that the active layer separated in an island shape may be peeled off.

The present invention has been made in view of the above circumstances, and an object of the present invention is to prevent the active layer from peeling off when forming an element isolation structure subjected to the above-described crystal defect avoidance treatment. It is an object of the present invention to provide a semiconductor substrate having an SOI structure and a method of manufacturing the same.

[0027]

In order to achieve the above object, the present invention provides a first insulating layer (oxide film) 5 formed on a semiconductor substrate (base substrate) 1 and a semiconductor layer (active film). Layer) 3
In a semiconductor substrate having a structure in which a second insulator layer (oxide film) 7 formed thereon is bonded to form an element on the active layer 3, the surface of the oxide film 7 on the active layer 3 It is characterized in that a low etching rate layer (p-type impurity layer) 7A having a lower etching rate for wet etching with an ammonium fluoride solution or the like than the oxide film 7 is formed.

According to the above configuration, the p-type impurity layer 7A having a small etching rate for wet etching is formed on the surface of the oxide film 7, so that the element isolation structure having been subjected to the above-described crystal defect avoidance processing is formed. When the buried oxide film is wet-etched, the amount of etching can be stopped by the p-type impurity layer 7A. Therefore, the amount of etching is limited to the interface between the oxide film 5 on the base substrate and the oxide film 7 on the active layer. Thus, the active layer 3 can be prevented from peeling off.

Here, the p-type impurity layer 7A is formed, for example, by a method of introducing a p-type impurity into the surface of the oxide film 7 by an ion implantation technique or by forming a p-type impurity-doped CVD film on the surface of the oxide film 7. However, it can be formed by a method of introducing the p-type impurity from the CVD film to the surface of the oxide film 7.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor substrate (SOI substrate) having an SOI structure according to an embodiment of the present invention.

As shown in FIG. 1, S according to the present embodiment
In the OI substrate, an active layer 3 is formed on a buried oxide film 9 on a base substrate 1. The buried oxide film 9 is composed of an oxide film 5 formed on the base substrate 1 and an oxide film 7 formed on the active layer substrate 3. A p-type impurity layer 7A in which a p-type impurity such as boron (B) is diffused is formed.

The p-type impurity layer 7A has a property that the etching rate of wet etching with an ammonium fluoride solution or the like is lower than that of the oxide film 7 (oxide film 7B) other than the p-type impurity layer 7A. In this embodiment,
By utilizing the property of the p-type impurity layer 7A, the separation of the active layer due to the crystal defect avoidance processing which has been a problem in the prior art can be suppressed. That is, as shown in FIG. 2, by stopping the progress of the wet etching with the p-type impurity layer 7A having a small etching rate, the etching amount does not reach the interface between the oxide film 5 and the oxide film 7, Therefore, the active layer does not peel off.

Next, a method for manufacturing an SOI substrate according to the present embodiment will be described with reference to the drawings. FIG. 3 is a process chart for describing a method for manufacturing an SOI substrate according to the present embodiment. The same parts as those in the prior art are denoted by the same reference numerals.

First, as shown in FIG. 3A, an oxide film 7 is formed on one main surface of an active layer substrate 3 which will be an active layer later.

Next, as shown in FIG.
Oxide film 5 is formed on one main surface of the substrate.

Next, as shown in FIG. 3C, a p-type impurity such as boron is introduced into the surface of the oxide film 7 formed on the active layer substrate 3 by a usual ion implantation technique.

Finally, as shown in FIG. 3D, the active layer substrate 3 and the base substrate 1 are bonded together by thermocompression bonding with their bonding surfaces facing each other. At this time, at the same time, the p-type impurity diffuses through the oxide film 7 by a thermal process for thermocompression bonding, and a p-type impurity layer 7A is formed. Then, if the other main surface is mirror-polished until the active layer substrate 3 has a predetermined thickness, the SOI substrate according to the present embodiment shown in FIG. 1 is formed.

In this embodiment, an ion implantation technique is used as a method for introducing a p-type impurity into the oxide film of the active layer, but the present invention is not limited to this method. For example, first, an oxide film doped with a p-type impurity, for example, boron-doped B
Forming an SG (Boro-Silicate-Glass) film by a normal CVD method, then diffusing boron from the BSG film to the oxide film, and finally removing the BSG film to form a p-type impurity layer. Is also possible.

[0039]

As described above, according to the present invention, in an SOI substrate having a structure in which an oxide film formed on a base substrate and an oxide film formed on an active layer are bonded to each other, Since a p-type impurity layer having a small etching rate for wet etching is formed on the surface of the oxide film of FIG. The etching amount can be stopped at the p-type impurity layer, so that the etching amount does not reach the interface between the oxide film on the pedestal substrate and the oxide film on the active layer, thereby removing the active layer. Can be suppressed. As a result, the buried oxide film formed between the base substrate and the active layer can be composed of the oxide film formed on the base substrate and the oxide film formed on the active layer. It is no longer necessary to form a thick buried oxide film necessary for a single thermal oxidation step, so that a high breakdown voltage power I can be obtained without lowering production efficiency and increasing costs.
An SOI substrate suitable for C can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor substrate having an SOI structure according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view when a buried oxide film of a semiconductor substrate according to the present embodiment is wet-etched.

FIG. 3 is a process diagram for describing the method for manufacturing a semiconductor substrate according to the present embodiment.

FIG. 4 is a cross-sectional view showing an element isolation structure using the SOI technique.

FIG. 5 is a cross-sectional view of a case where a high breakdown voltage power element and a control element are monolithically integrated using the element isolation structure shown in FIG.

FIG. 6 is a process chart for explaining a conventional method for manufacturing an SOI substrate.

FIG. 7 is a process chart for explaining another method for manufacturing a conventional SOI substrate.

8 is a process chart for explaining a method of actually forming an element isolation structure using the SOI substrate formed by the manufacturing method shown in FIG.

FIG. 9 is a process chart for describing a process of avoiding crystal defects at corners of the active layer shown in FIG.

FIG. 10 is a diagram for explaining a problem of the crystal defect avoidance processing shown in FIG. 9;

[Explanation of symbols]

 1 substrate 3 active layer (active layer substrate) 5, 7, 7B, 11, 19, 23 oxide film 7A p-type impurity layer 9 buried oxide film 13 island-shaped active layer 15 lateral power MOSFET 17 CMOST 21 photoresist 25 poly Silicon 27 etching removal part

Claims (4)

[Claims] 1. A structure in which a first insulator layer formed on a semiconductor substrate and a second insulator layer formed on a semiconductor layer are bonded to each other, and an element is formed on the semiconductor layer. A semiconductor substrate having a low etching rate layer formed on the surface of the second insulator layer, the etching rate of which is lower than that of the second insulator layer for wet etching with an ammonium fluoride solution or the like. Characteristic semiconductor substrate. 2. The low etching rate layer according to claim 2, wherein
2. The semiconductor substrate according to claim 1, wherein said insulator layer is a p-type impurity layer in which a p-type impurity is introduced. 3. A step of forming a first insulator layer on a semiconductor substrate as a base substrate, a step of forming a second insulator layer on a semiconductor layer on which an element is formed, and A semiconductor comprising at least a step of introducing a p-type impurity into a surface of an insulator layer by an ion implantation technique and a step of bonding the first insulator layer and the second insulator layer. Substrate manufacturing method. 4. A step of forming a first insulator layer on a semiconductor substrate as a base substrate, a step of forming a second insulator layer on a semiconductor layer on which an element is formed, and Forming a CVD film doped with a p-type impurity on the surface of the insulator layer, and introducing the p-type impurity from the CVD film to the surface of the second insulator layer; And bonding the second insulator layer to the semiconductor substrate.