JPH1050850A - Lsi layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To divert LSI's and layout design resources which have already existed and reduce a LSI development work amount by a method wherein a cell of basic logic unit is structured of magnitude integral times a pitch of basic dimensional unit. SOLUTION: When cells 1 to 11 constituting basic logic unit are formed on a semiconductor substrate, magnitude of occupied contour, input/output signals, power source terminal position, and wiring routes to connect a plurality of elements are structured integral times a pitch of basic dimensional unit and prescribed. Respective signal terminals and wirings are laid out and connected on lattices arranged at a pitch of basic dimensional unit to constitute LSI's. As described above, a basic logic cell is prescribed at a pitch of basic dimensional unit without depending on a semiconductor process, and this basic dimension can be changed corresponding to semiconductor design. Thereby, it is possible to reduce work steps required for design and enable LSI development for a short period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a standard cell type semiconductor integrated circuit, and more particularly to a layout and wiring design.

[0002]

2. Description of the Related Art FIG. 1 shows an example of a layout design in a semiconductor integrated circuit (referred to as "LSI") using standard cells. In the figure, 1 to 11 are basic logic circuits.
A standard cell having functions such as an inverter, a two-input NAND, and a three-input NAND is shown. In the figure, terminals indicated by white square symbols indicate input terminals, terminals indicated by black square symbols indicate output terminals, and wires connecting these terminals are indicated by arrows.

Consider a case where a semiconductor process is updated from a first semiconductor process (“technology A”) to a second semiconductor process (“technology B”) due to miniaturization of an LSI or the like.

In the second semiconductor process, it is general that the design dimensions of a circuit on a semiconductor substrate are updated, and the dimensions of each part are reduced with miniaturization.

In the conventional method of LSI layout design,
For the purpose of arranging and wiring by an automated tool, the elements are arranged and wired along a grid arranged at a pitch of a certain basic unit size.

However, when the design dimensions are reduced and changed by the above-described semiconductor process update, in order to pursue the performance, as shown in FIG. 3, the size of the standard cell of each basic circuit is reduced. The reduction differs depending on the circuit, and as a result, the relationship of the relative positions of the arrangement of the cells differs.

As a method for miniaturization of LSI, LS
There is a method of uniformly reducing (reducing) each dimension of the entire functional unit of I.

[0008]

The above-mentioned conventional system has the following problems.

(1) The first problem is that when the LSI is miniaturized by updating the semiconductor manufacturing process, the LSI must be renewed.
This means that LSI layout and wiring layout design must be performed, which requires an enormous amount of design work.

The reason is that the size of the basic logic cell constituting the logic function differs due to the change of the design dimension accompanying the semiconductor process update, and the relative positional relationship of the arrangement of each cell is lost. .

(2) The second problem is that when the entire functional unit of the LSI is uniformly reduced, blocks of each hierarchical level constituting a function cannot be used, and the layout of each LSI is individually designed. And it also requires a large amount of design work.

Accordingly, the present invention has been made in view of the above circumstances, and has as its object to reduce the size of an LSI in a standard cell LSI design.
When designing a new LSI, the arrangement and wiring information of standard cells and logic blocks combining them are diverted, regardless of the semiconductor process, thereby reducing the number of man-hours required for the design and shortening LSI development in a short time. An object of the present invention is to provide a layout method that can be used.

[0013]

In order to achieve the above object, a layout method according to the present invention is directed to a standard cell type semiconductor integrated circuit in which a plurality of logic function blocks having a plurality of transistor elements are formed on a semiconductor integrated circuit substrate. The size of the external shape occupied when forming the cells constituting the basic logical unit on the semiconductor substrate, the position of the input / output signal and the power supply terminal, and the wiring path connecting the plurality of elements are represented by an integer of the pitch of the basic dimensional unit It is characterized in that it is composed and specified as double.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. According to a preferred embodiment of the present invention, when configuring a basic logic cell of an LSI on an LSI substrate layout, the size of the cell and the positions of the input / output terminals are arranged on a lattice with a pitch of a basic dimension unit. In doing so, regardless of the design dimensions in the semiconductor process, the size converted on the pitch of each basic cell shall be the same, and the relative position of the arrangement position shall be maintained on the pitch grid of the basic dimension unit. This is a layout design.

In the embodiment of the present invention, the cells of the basic logical unit are preferably combined and arranged at an integral multiple of the pitch of the basic dimensional unit to form a hierarchically large-scale logical block. is there.

Further, in the embodiment of the present invention,
The basic unit pitch is related to the semiconductor manufacturing process.
It is variable according to different design dimensions.

As a result, even in the LSI layout design for semiconductor processes of different design dimensions, the LS
It is possible to reuse existing layout data resources without changing the relative positions of the internal cells only by changing the basic dimension unit for the entire I or some functional blocks in the LSI. it can.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. Referring to FIG. 1, in the embodiment of the present invention, each of the cells 1 to 11 of the basic logical unit is configured to have a size of an integral multiple of the pitch of the basic size unit, and each signal terminal and wiring are set to the basic size. It is arranged and connected on a grid (not shown) arranged at a unit pitch to form an LSI.

FIG. 2 is a diagram showing an example of a layout result according to this embodiment when miniaturization is performed on the LSI shown in FIG. 1 by a different semiconductor process. LS is reduced by reducing the pitch of the cell's basic dimension unit.
This is the result of the I arrangement.

As shown in FIG. 2, it can be seen that the relative positional relationship between the cells 1 to 11 is equivalent to the relative positional relationship between the cells in the LSI shown in FIG.

In this embodiment, regardless of the process,
By defining basic logic cells having the same cell size and terminal position on the pitch of the basic dimension unit, the basic logic cells constituting the LSI and the logic function blocks obtained by hierarchically combining the basic logic cells can be defined. The unit is set according to the semiconductor process, and arrangement and wiring are performed. The task of dimensioning the reduction / enlargement of these data is very generally possible with commercial CAD tools or layout, text-level conversion of information data.

Referring to FIG. 1, in a semiconductor process "technology A", a standard cell inverter 1 has a pitch of 1 pitch, a 2-input NAND cell 2 has a pitch of 2 pitch, and a 3-input NAND cell 3 has Pitch width 3
Arranged in order to realize an arbitrary logical function defined by cells having a pitch. The signal terminals and wirings are arranged on a lattice (not shown), and the terminal positions in the cell are fixed relative positions in the cell.

FIG. 2 shows the logic function of FIG. 1 realized by the semiconductor process "Technology B". The pitch of the basic dimension unit is reduced to half that of FIG. Are the same as those in FIG.

On the other hand, in the conventional method described above,
As shown in FIG. 3, since the relative arrangement of the cells is different when the cell configuration is defined independently of the technology A, the arrangement needs to be redesigned.

[0025]

As described above, according to the present invention,
There is an effect that existing LSI and layout design resources can be diverted, and the amount of LSI development work can be reduced.

The reason is that, in the present invention, the basic logic cell is defined by the pitch of the basic dimension unit without depending on the semiconductor process, and the basic dimension can be changed according to the semiconductor design.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention, and is a diagram illustrating an example of arrangement and wiring of an LSI by a first semiconductor process.

FIG. 2 is a diagram for explaining an embodiment of the present invention, and is a diagram showing an example of arrangement and wiring of LSIs by a second semiconductor process.

FIG. 3 is a diagram showing an example of an arrangement and wiring of an LSI by a semiconductor process in a conventional method.

[Explanation of symbols]

 1 to 11 basic logic cell 1 pitch basic dimension unit INV, 2NAND logic function technology A, B semiconductor process name

Claims (5)

[Claims] In a standard cell type semiconductor integrated circuit in which a plurality of logic function blocks having a plurality of transistor elements are formed on a semiconductor integrated circuit substrate, when a cell constituting a basic logic unit is formed on the semiconductor substrate, A layout method of a semiconductor integrated circuit, wherein a size of an external shape occupied, positions of input / output signals and power supply terminals, and a wiring path connecting a plurality of elements are constituted by an integral multiple of a pitch of a unit of a basic dimension. 2. A semiconductor process according to claim 1, wherein the layout of the basic logic cells constituting the semiconductor integrated circuit (hereinafter referred to as “LSI”) is performed on an LSI substrate. The pitch dimension of the basic dimension unit is variably adjusted according to a design dimension determined by a semiconductor process, and the relative pitch of the basic logic cell on the basic dimension unit pitch is different for different semiconductor processes. A layout method for a semiconductor integrated circuit, wherein the positional relationship is the same. 3. The semiconductor integrated circuit according to claim 1, wherein cells of said basic logical unit are arranged in combination at an integral multiple of a pitch of a basic dimension unit to form a hierarchically large-scale logical block. Circuit layout method. 4. The layout method for a semiconductor integrated circuit according to claim 1, wherein the pitch of the basic dimension unit is variable corresponding to different design dimensions related to a semiconductor manufacturing process. 5. The layout design according to claim 1, wherein the layout design is performed by combining the basic logic cells and the large-scale logic blocks defined by the pitch of the basic dimension unit regardless of the semiconductor manufacturing process. 2. The layout method of a semiconductor integrated circuit according to claim 1.