JPH06244387A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase the speed of a circuit and to lower the consumption power by removing unnecessary patterns from a hard-macronized macroblock. CONSTITUTION:Symbols a-e are given to output terminals 13-17 of a macroblock 1 respectively. Getting back to the input side, wiring lines and constituent blocks 2-6 are provided with the symbols corresponding to the output terminals. If there are any output terminals not used in the circuit design using this macroblock, the wiring lines and constituent blocks which bear the same symbol as the one given to the unused output terminals are removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly to a method of manufacturing a semiconductor integrated circuit using a macro block composed of a plurality of basic logic blocks.

[0002]

2. Description of the Related Art One of the methods for designing semiconductor integrated circuits
The gate array method is known as one. This is a method in which a functional block having general versatility is registered in advance as a macro block, and a circuit designer calls macro blocks required for designing a semiconductor integrated circuit and combines them to construct a circuit. By using this method, design can be performed efficiently, and design mistakes can be significantly reduced as compared with the case of designing at the basic logic block level.

As macro blocks, a layout is performed by a computer after the circuit design is completed only by defining a logical function and a hard macro in which basic characteristics such as switching characteristics and load characteristics are prepared up to layout design. Known as a soft macro. Conventionally, hard macros are applied only to small-scale and highly versatile blocks such as input / output buffers, and medium- and large-scale logic circuits are often provided as soft macros. Recently, with the increase in scale, there is an increasing tendency to convert a large-scale logic circuit into a hard macro.

FIG. 11 is a block diagram of a circuit to be designed using soft macro blocks. 201 to 206 are input terminals of the circuit, and 207 to 210
Is an output terminal of the circuit, 220 and 221 are macro blocks, 222 is a basic logic block, 230 to 235 are input terminals of the macro block, and 240 to 245 are output terminals of the macro block. FIG. 12 is a block diagram showing a configuration of macroblocks 220 and 221 in FIG. In FIG. 12, 250 to 252 are input terminals, 2
60 to 262 are output terminals, and 270 to 275 are basic logic blocks.

Here, when the output terminal 245 of the macroblock 221 becomes unused as shown in FIG. 11, that is, when the output terminal 262 in FIG. 12 becomes unused, it is connected to the output terminal 262. Basic logic gate 2
Since the output terminal of 73 is unused, it is deleted, and as a result, the output terminal of the basic logic gate 274 is unused, so it is deleted. Then, the netlist is reconstructed from this result, and the layout is designed. In this way, in a soft macro macroblock, by removing unnecessary basic logic gates in the macroblock after circuit design and reconfiguring the entire circuit without fixing the circuit in the block. , The circuits of similar macro blocks are made common, and partial use of the circuits is executed according to the usage status of terminals to reduce the number of macro blocks registered in the library in advance. (For example, JP-A-59-61944).

[0006]

In the above-described conventional manufacturing method, unnecessary blocks of the circuit in the macroblock are deleted according to the usage status of the terminals at the stage of the netlist, and the netlist is reconstructed from the result. The layout design was done based on the netlist created here. However, in the layout design, for example, the optimum shape is determined, or the configuration block directly connected to the input / output terminal of the macro block is set to the edge of the macro block. It is necessary to devise a layout such as forcibly arranging in a place close to. In addition, it is necessary to design the circuit considering the delay in the circuit as the speed of the semiconductor integrated circuit increases. In particular, the delay due to the wiring cannot be ignored. I have to.

However, in the conventional manufacturing method, the layout is performed after the contents of the macroblock are expanded, so that the constituent blocks of the macroblock are not always arranged in a group, and the delay and timing in the macro may be reduced. Since it is impossible to consider only within a block and it is necessary to consider it in relation to other circuits in the entire circuit, the propagation delay time of the macro block is undetermined at the circuit design stage. However, timing design becomes difficult. Therefore, the error in the estimation of the delay of the entire circuit before the layout becomes large, and the layout may have to be redone in some cases. Therefore, the layout process in the conventional example requires a great number of man-hours to obtain a satisfactory result.

Here, the above problems will be described more concretely by way of examples. In FIG. 12, blocks 270 and 271 are latches, terminals 280 and 282 are signal input terminals,
Terminals 281 and 283 are clock input terminals, net 29
0 and 291 are data signal lines, and nets 292 and 293 are clock signal lines. Since this macro block is laid out after being expanded, the blocks 270 and 271 are not necessarily arranged in the vicinity. Therefore, for example, the wiring length from the terminal 250 to the terminal 280 may be much larger than the wiring length from the terminal 251 to the terminal 281, and in this case, the block 270 may not be able to correctly latch the data. Block 2
71 can happen, but these situations are block 27
It depends on the distance between 0 and 271 and the wiring length of the nets 290, 291 and 292. In other words, there is no guarantee that this macro block will operate correctly at the circuit design stage, and that judgment cannot be made until the layout is completed. If it is found that the layout does not work after the layout, the layout needs to be redone again, and in this case, the man-hours increase significantly.

On the other hand, in a hard macro block which is used for circuit design after the layout design is completed, a design considering the delay inside the block is performed in advance, for example, nets 290, 291, 292. Ingenuity has been made in advance to reduce variations in wiring length. Moreover, since the layout is completed, the characteristics of the macro including the delay are clarified, and the operation of the macro block part is guaranteed as long as the circuit is designed according to the specifications.

However, in the conventional hard macro,
The layout pattern is the same regardless of the presence / absence of unused terminals. For example, even if a terminal with a macroblock becomes unused and as a result a certain constituent block (basic logic block) in the macroblock becomes unnecessary, The layout pattern of the constituent blocks was left as it was. Therefore, even when only a part of the function of the macro block is used, when designing the layout of the upper macro using the macro block, the wiring property of the wiring passing over the macro block is improved. There is no such thing. In addition, there is a problem that stray capacitance of other circuits increases due to unused wiring and configuration blocks, which hinders high-speed operation. Furthermore, unnecessary blocks continue to operate, and power is wasted accordingly. Was.

Therefore, an object of the present invention is, firstly, to avoid the above-mentioned inconvenience caused by deleting an unnecessary block from a soft macro, and secondly, to avoid it from a hard macro. It is an object of the present invention to provide a manufacturing method in which a block is deleted, and thus a semiconductor integrated circuit that is easy to design and evaluate, has high speed, and has low power consumption.

[0012]

To achieve the above object, according to the present invention, a circuit is constructed using a macroblock having a plurality of constituent blocks (basic logic blocks) and having a fixed layout pattern. As a result, the output terminals of the unused macro block are extracted, and the wiring line segment and the pattern of the configuration block related only to the unused output terminal are deleted from the macro block. There is provided a method for manufacturing a semiconductor integrated circuit, which is characterized in that a circuit is created by using a macroblock having the pattern.

A more specific means for deleting the wiring line segment and the pattern of the constituent block from the macro block is to remove the pattern of the unused portion of the wiring connected to the unused output terminal and to remove all the output terminals. Delete the pattern of the configuration block connected to the unused wiring pattern, delete the unnecessary wiring pattern as a result of this deletion, and repeat the same process until there are no patterns to delete. Yes, the wiring is divided into wiring line segments divided at branch points, different symbols are given to the output terminals of the macroblock, and the wiring line segments connected to the output terminals are given the symbols of the output terminals. All the symbols of the wiring line segment connected to the output terminal of the block are given to the block, and the configuration block is attached to the wiring line segment connected to the input terminal of the configuration block. After assigning all the symbols that the output side wiring line segment has to the input side wiring line segment at the branch point and assigning the symbols to all the wiring line segments and constituent blocks, This is achieved by deleting the pattern of the wiring line segment and the building block having only the symbols assigned to the used output terminals.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of a macro block that is made into a hard macro target in an embodiment of the present invention.
In the figure, reference numeral 1 is a macroblock, and 2 to 6 are constituent blocks constituting the macroblock 1, each of which is constituted by a basic logical block. 10 to 12 are input terminals of the macro block 1, 13 to 17 are output terminals of the macro block 1, 20 to 28 are nets that connect constituent blocks within the macro block 1, and 30 to 33 are wiring line segments. Branch points, 40 to 43, 47 to 50 are input terminals of the constituent block, and 44 to 46, 51 to 53 are output terminals of the constituent block.

To explain the first embodiment of the present invention,
As a result of designing the circuit using the macro block 1, it is assumed that the output terminals 13 and 14 are not used. In this case, first, the part between the output terminal 13 and the branch point 32 of the net 21 connected to the output terminal 13 and the output terminal 14
The net 26 connected to is deleted. Next, net 26
The configuration block 4 in which all the output terminals are unused due to the deletion of is deleted. Next, the portion between the configuration block 4 and the branch point 31 in the net 21, which is no longer necessary due to the removal of the configuration block 4, is deleted. The result of the above processing is shown in FIG.

As described above, according to the present invention, the portion of the net that is related only to the unused output terminals and the constituent blocks that are related to all the output terminals that are not used By deleting it, you can enjoy the following effects. The capacity of the net 21 is equal to the capacity of the deleted wiring line segment,
It is reduced by the sum of the input capacitance of the input terminal 47 of the building block 4. The smaller the capacitance, the faster the signal propagation speed between the terminals of the net. Therefore, the time required for the signal to reach the input terminal 48 from the output terminal 44 is shortened as compared with that before the pattern is deleted. That is, according to the present invention, it is possible to realize a high-speed circuit, increase the operational timing and delay margin of each component block, and improve the reliability of circuit operation.

By deleting the building block 4,
It is possible to reduce power consumption. When designing a layout of a high-order macro using macro blocks from which unnecessary patterns have been deleted, it is possible to improve the wiring property of the wiring that passes over this macro. Further, it is possible to reduce the capacitance between the wiring in the macro block and the wiring on the macro. Since the total number of patterns is reduced, it is possible to improve manufacturing reliability.

The characteristic evaluation of the macroblock after the pattern reduction processing can be easily performed by performing delay calculation including the wiring length by using the information of the wiring pattern remaining without being deleted. When registering this macroblock in the library, if the correspondence between each wiring and the prohibition information in the library is given in advance, the prohibition information corresponding to the deleted wiring can be deleted from the library to create new registration data. It can be easily recreated. When the semiconductor integrated circuit is of the gate array type, the deleted constituent block portion becomes an empty cell, and may be used by another block or left unused in the layout design of the upper block using this macro block. become. If left unused,
Since the underlying transistor that is not used remains there, it is desirable to add the processing of the input clamp of the unused transistor in order to improve the latch-up resistance.

Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 shows a result of pretreatment for carrying out the present embodiment, FIGS. 4, 5 and 6 show examples of results of carrying out the present embodiment, and FIG. 7 shows a chip design procedure according to the present embodiment. It is a flow chart shown.

If there is a layout of hard macro macroblocks as shown in FIG. 1, the wiring data of each net is first divided at the branch points of the wiring. For example, since the net 20 has a wiring branch point 30, the data is divided here and divided into three terminals 11 to 30, a branch point 30 to a terminal 41, and a branch point 30 to a terminal 43 to be held. Similarly,
Since the net 21 has branch points 31 and 32, the terminals 13 to
Branch point 32, branch point 32 to terminal 48, branch point 32 to branch point 31, branch point 31 to terminal 44, branch point 31 to terminal 47
The net 24 has a branch point 33. Therefore, the terminal 45 to the branch point 33 and the branch point 33 to the terminal 5 are divided.
It is divided into three pieces of data of 0, the branch point 33 to the terminal 17, and each piece of data is held.

Next, a symbol that is uniquely determined is given to each output terminal. For example, the symbols a to e are attached to the terminals 13 to 17. Next, according to the following rules, symbols are given to the wirings and the constituent blocks in order from the output terminal toward the signal input side. (1) The symbol is given to each wiring line segment divided above. (2) The symbol given to the output terminal is directly transmitted to the wiring line segment connected thereto, and the same symbol is given to this. (3) A set of symbols that is the logical sum of the symbols given to the wiring line segments on the output side of the branch point is given to the wiring line segments on the input side of the branch point. (4) A set of symbols that is the logical sum of the symbols given to the wiring line segments connected to the output terminals is given to the constituent block. (5) The symbols given to the constituent blocks are given to the wiring line segments connected to the input terminals of the constituent blocks. Here, the set of symbols is represented as, for example, (a, b). Further, for example, the logical sum of (a, b) and (b, c) is (a, b, c). The result of giving the symbols in this way is shown in FIG.

Next, the set U of unused terminals is obtained. For example, when the unused terminals are a and b, U = (a, b). Here, in comparison with the symbol U given to each wiring line segment / configuration block above, the wiring line segment and configuration block in which the symbol or its set is included in U are deleted. This makes it possible to delete all unnecessary portions of the pattern connected to the unused terminals.

The result of processing with U = (a, b) is shown in FIG.
FIG. 5 shows the result of processing U = (d), and U = (d)
The result of processing as = (a, c) is shown in FIG. U =
In the case of (a, b), since the symbols a and b and the symbol set (a and b) are included in this, the wiring line between the output terminal 13 and the branch point 32 to which the symbol a is added is included. Minutes, the wiring line segment between the input terminal 47 and the branch point 31 to which the symbol b is added, and the configuration block 4 to which the symbol b is added are deleted.

FIG. 7 shows a procedure for designing a circuit of a semiconductor integrated circuit chip by performing the above processing. After creating the circuit diagram, unused terminals of macroblocks included in the circuit are extracted. Then, the above-mentioned pattern deletion processing is performed from this information. Note that, up to the point where symbols are added as shown in FIG. 3, it can be done in advance before circuit design.
Next, the propagation delay value of the macroblock is recalculated based on the processing result, and the registration data in the layout library is recreated. Next, based on the calculated transmission delay value, verification before layout is performed, and if there is no problem, layout is executed.

As in the second embodiment, a unique symbol is given to each output terminal of the macroblock, and the wiring line segment and the basic logic block in the macroblock are given symbols according to the above rules. If so, the situation in the macroblock becomes clear, and the macroblock can be easily managed. In addition, by assigning and holding this symbol in advance, when designing other circuits using this macro block, the work of deleting wiring line segments and basic logic blocks can be executed quickly. The circuit design period can be shortened.

FIG. 8 is a block diagram of a hard macro-ized macroblock which is a target of the third embodiment of the present invention.
9A and 9B are block diagrams of a semiconductor integrated circuit having a target macroblock and other macroblocks mounted therein. In the present embodiment, the layout of the macro block is provided in advance with redundant terminals and redundant wiring patterns connected thereto, and the pattern connected to the unused terminals is deleted after the layout is completed.

As shown in FIG. 8, the macroblock 6
Wiring is provided from an output terminal 72 of one constituent block 61 in 0 to output terminals 70 and 71 of the macro block. Either one of the output terminals 70 and 71 is normally used, but the output terminals 70 and 71 are provided on the left and right sides of the macro block in order to improve the wiring property in the layout design of the upper block.

An example of proper use of terminals is shown in FIG.
It shows in (b). In the figure, the above-mentioned macroblock 6
0 is arranged on the upper block together with other macroblocks 90. The net 80 connects between the input terminal 91 of the block 90 and the output terminal 70 or 71 of the block 60. As shown in FIG. 9A, the block 90
Is on the left side of the block 60, by using the output terminal 70 in the layout design of the upper block, the layout can be performed more efficiently than when the output terminal 71 is used. Conversely, if block 90 is to the right of block 60, as shown in FIG.
By using the output terminal 71, efficient layout can be performed.

In the example shown in FIG. 9A, the wiring line segment between the output terminal 71 to the branch point 73 of the net 74 is unnecessary, and in the example shown in FIG. 9B, the output terminal 70 to the branch point. The wiring line segment between the points 73 becomes unnecessary. After either of the output terminals 70 and 71 is used and the layout of the upper block is completed, the unnecessary pattern connected to the unused output terminal is deleted. The method of deleting the pattern connected to the unused output terminal is the same as the method shown in the second embodiment of the present invention.

FIG. 10 is a flow chart showing a procedure for designing a semiconductor integrated circuit chip by performing the above processing. After creating the circuit diagram, verify before the layout, and if there is no problem, design the layout. After layout, the unused output terminals of the macroblock are extracted, and pattern deletion processing is performed from this information. Next, the propagation delay time of the macroblock is recalculated based on the processing result, and then the post-layout verification (back annotation) is performed based on the calculated propagation delay time. As described above, in this embodiment, by providing the output terminals and the wiring of the hard macro with redundancy, the wiring performance of the layout of the upper block is improved and the operation speed and reliability of the macro are improved. Can be planned.

[0031]

As described above, according to the present invention, when a high-order block is designed using a hard macro macroblock, unnecessary patterns relating to output terminals of unused macroblocks are deleted. Therefore, according to the present invention, without impairing the characteristics of the macroblock,
Further, it is possible to realize high-speed operation of a macroblock and a circuit using a macroblock without sacrificing design efficiency and ease of design, and it is possible to improve the reliability of circuit operation by expanding a timing margin. it can. In addition, it is possible to improve the wiring performance in the layout design of the upper block using the macro block, and it is possible to reduce the wiring capacity between the macro block and the upper block. Further, it is possible to reduce the useless power consumption by stopping the operation of the unused basic logic block.

[Brief description of drawings]

FIG. 1 is a block diagram of a hard macro-ized macro block for explaining an embodiment of the present invention.

FIG. 2 is a block diagram of a macroblock showing an implementation result of the first exemplary embodiment of the present invention.

FIG. 3 is a block diagram of macroblocks for explaining a second embodiment of the present invention.

FIG. 4 is a block diagram of a macroblock showing an implementation result of the second embodiment of the present invention.

FIG. 5 is a block diagram of a macroblock showing an implementation result of the second embodiment of the present invention.

FIG. 6 is a block diagram of a macroblock showing an implementation result of the second embodiment of the present invention.

FIG. 7 is a flowchart showing a design procedure of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 8 is a block diagram of a macroblock for explaining a third embodiment of the present invention.

FIG. 9 is a block diagram of an upper block for explaining a third embodiment of the present invention.

FIG. 10 is a flowchart showing a design procedure of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 11 is a block diagram of a circuit to be designed by a conventional method.

FIG. 12 is a block diagram showing a configuration of a macro block in FIG.

[Explanation of symbols]

1 macroblock 2 to 6 constituent block of macroblock 1 10 to 12 input terminal of macroblock 1 13 to 17 output terminal of macroblock 1 20 to 28 net for connecting constituent blocks within macroblock 1 30 to 33 wiring line Branch point 40 to 43 input terminal of the constituent block 44 to 46 output terminal of the constituent block 47 to 50 input terminal of the constituent block 51 to 53 output terminal of the constituent block 60 macroblock 61 constituent block of the macroblock 60 70 to 71 macro Output terminal 72 of block 60 Output terminal 73 of configuration block 61 Branch point of wiring line line 74 Net 80 in macro block 60 Net 90 connecting between macro block 60 and macro block 90 In connection with macro block 60 Block 91 macro block 9 0 input terminal 201 to 206 circuit input terminal 207 to 210 circuit output terminal 220, 221 circuit macroblock 222 basic circuit logic block 230 to 235 macroblock input terminal 240 to 245 macroblock output terminal 250 To 252 macro block input terminals 260 to 262 macro block output terminals 270 to 275 macro block constituent blocks 280, 281 macro block 270 input terminals 282, 283 macro block 271 input terminals 284 macro block 270 output terminals 285 Output terminal 290 to 292 of macro block 271 Net connected to input terminal

Claims (4)

[Claims] 1. A circuit is configured by using a macro block having a plurality of constituent blocks and having a fixed layout pattern, and as a result, an output terminal of a macro block that is unused is extracted, and an output that is not used. Manufacturing of a semiconductor integrated circuit characterized in that a wiring line segment and a pattern of a constituent block that are associated only with a terminal are deleted from a macro block, and a circuit is created using the macro block having the pattern of the remaining wiring and the constituent block. Method. 2. A pattern of a constituent block in which all the output terminals are connected to the unused wiring pattern by removing the pattern of the unused portion of the wiring connected to the unused output terminals. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the wiring pattern is deleted, an unnecessary wiring pattern is deleted as a result of the deletion, and the same process is repeated until there is no pattern to be deleted. 3. The wiring is divided into wiring line segments divided at branch points, different symbols are given to the output terminals of the macroblock, and the wiring line segments connected to the output terminals are given the symbols of the output terminals, All the symbols of the wiring line segment connected to the output terminal of the block are given to the configuration block, the symbols of the configuration block are given to the wiring line segment connected to the input terminal of the configuration block, and the input side at the branch point After assigning all the wiring line segment symbols to the output side line segments and assigning symbols to all wiring line segments and configuration blocks,
2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the wiring line segment and the pattern of the constituent block having only the symbols given to the unused output terminals are deleted. 4. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the macro block has a redundant output terminal and a redundant wiring pattern connected to the redundant output terminal.