JPH04140885A - Circuit diagram editter - Google Patents

Abstract

PURPOSE:To shorten a logic design time by automatically generating or erasing the macro terminal of a macro block of a hierarchy which is being edited, and the outside terminal of the macro block which is referred to by the hierarchy while being interlocked. CONSTITUTION:A diagram (a) is a display diagram before an input signal is connected with a macro block MA3 in the hierarchy which is being edited. When a VLSI designer selects the macro block with which the signal line is to be connected in the hierarchy which is being edited, a new screen is opened as indicated by a diagram (b), and the data in the macro block are displayed in it. A diagram (c) is the display diagram indicating that the signal line to be connected is connected with the macro block, an input pin P2 is added to the outside frame of the macro block, and an outside input terminal P1 is automatically generated in the macro block. Thus, the VLSI designer can continuously edit the data in the macro block, and design the logic without noticing a modification structure. Thus, the designing time can be shortened.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a circuit diagram editor that inputs and edits logic circuit diagrams in the logic design process of VLSI, and particularly relates to logic circuit diagram data of the layer being edited. A circuit in which the logic circuit diagram data in the macroblock referenced in that layer is input and edited at the same time, and the macro terminals of the macro block and external terminals in the macro block are automatically connected in conjunction with the connection between the layers. Regarding the diagram editor.

[Conventional technology]

Conventionally, this type of logic circuit diagram editor has been used to edit and input logic circuit diagram data in macroblocks that are referenced in the hierarchy being edited. Data was read into the editor, displayed, and input/edited. Also, when making connections between layers, add a macro terminal within the macroblock of the layer being edited, and input an external terminal with the same name into the macroblock referenced in that layer. Ta.

[Problem to be solved by the invention]

The conventional logic circuit diagram editor described above, when inputting/editing circuit diagram data in a macroblock referenced in the hierarchy being edited, inputs and edits the circuit diagram data in the hierarchy currently being edited. Input gA! After finishing A and saving, I read the data in the macroblock into the editor and performed input/tais. Therefore, when inputting or editing data that crosses between the layer being edited and the macroblocks referenced in that layer, it takes time to load and display it on the editor, and the ti4 collection is performed. To connect the hierarchy between the hierarchy you are editing and the macroblocks referenced in that hierarchy, add a macro terminal to the macroblock in the hierarchy you are editing, and add the macroblocks referenced in that hierarchy. This is done by inputting external terminals with the same name within the macroblock, which has the disadvantage of being time consuming.

An object of the present invention is to eliminate such drawback 3 and to simultaneously input logic circuit diagram data and circuit diagram data in a macroblock.
An object of the present invention is to provide a circuit diagram editor which can be edited and can automatically connect macro terminals of macro blocks and external terminals.

[Means for Solving the 3 Problems] A mask block to be input/edited in the circuit diagram editor of the present invention or in the hierarchy in which the Ii 4 measures of the logic circuit which is hierarchically designed in the logic design process of VLSI are performed. When you select , the data in that mask block is displayed, and the data in the layer being edited and the macroblocks referenced in that layer are input/edited at the same time, and the layer being edited is displayed. The macro terminal of the macro block and the external terminal of the macro block referenced in that hierarchy are automatically generated or deleted in conjunction with each other.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a flow diagram illustrating an embodiment of the present invention.

In the circuit diagram editor with the intra-macroblock mtA function of this embodiment, first, in step S1, when the input/g4-collected macroblock is selected in the circuit diagram of the layer currently being edited, another screen appears in step S2, The data within the macroblock is displayed. Then, in step S3, the data in the layer being edited and the macroblocks referenced in that layer are simultaneously input and edited.

Next, when a macro terminal is added (deleted) to the macroblock in the hierarchy being edited in step S4, an external terminal with the same name as the macro terminal added (deleted) in that macroblock is automatically generated and deleted. ) to be done.

In addition, when you delete the external terminal input in that macroblock in step S5, a pin with the same name as the external terminal name input in the outer frame of the macroblock in the layer that references that block (macro terminal) is automatically generated (erased). Then, in step S6, the input and
#i When the straw is finished, the screen displaying the data disappears and the process ends.

FIGS. 2(a) to 2(d) show the hierarchy edited with the circuit diagram editor with macroblock M4 collection function of this embodiment,
FIG. 6 is a display diagram of a circuit diagram showing, in order of steps, that circuit diagram data in macroblocks referenced in the hierarchy are simultaneously edited.

First, FIG. 2(a) is a display diagram before the logic elements A and B of the same type in the hierarchy being edited are moved into the macroblock MA2. When the VLSI designer selects the macroblock MA2 that he wants to edit in the hierarchy being edited (step S+), a new screen is opened in the building shown in FIG. is displayed (step S2).

Next, in FIG. 2(c), the movement of elements A and B into the macroblock is completed (step S4).
．． In step S5), FIG. 2(d) shows a display diagram in which the screen displaying the data in the macroblock disappears after editing has been completed (step S6).

Figures 3 (a) to (c) show what is referenced in the hierarchy when an input pin is added to the macro program in the hierarchy being edited with the circuit diagram editor with macroblock editing function of this embodiment. FIG. 7 is a display diagram showing that an external input terminal is automatically generated within a macroblock.

FIG. 3 (a) is a display diagram before an input signal is connected to macroblock MA3 in the layer being edited.

When the VLSI designer selects the macro program to which the signal line is to be connected in the editing hierarchy, a new screen will open as shown in Figure 3 (b). The data within the macroblock is displayed therein (step S2>).

Figure 3(c) is a display diagram showing that the signal line to be connected is connected to the macroblock, input bin P2 is added to the outer frame of the macroblock, and external input terminal P1 is automatically generated within the macroblock. Yes (step Sa, S5).

In this manner, the VLSI reviewer can continue to edit data in macroblocks and perform logic design without being aware of modified structures.

In addition, this macro terminal and external terminal blink and occur.
A designer can place it at a desired position using a pointing device.

〔·Effect of the invention〕

As explained above, the present invention allows inputting and editing of data in the hierarchy being edited in a logical circuit diagram with a hierarchical design and the macroblocks referenced in that hierarchy. When you add a macro terminal to a macroblock that is currently in use, an external terminal is automatically generated within that macroblock, or when an external terminal is input into a macroblock, the outer frame of the macroblock in the layer that references that macroblock Since macro terminals can be automatically generated or created, input and editing can be performed without being aware of the hierarchy, which has the effect of shortening the design time for VLSI logic design.

[Brief explanation of the drawing]

Figure 1 is a flow diagram explaining one embodiment of the present invention, and Figures 2 (a) to (d) show the hierarchy being edited with the circuit diagram editor of this embodiment and the macros referenced in that hierarchy. Display diagrams showing that circuit diagram data in a block are simultaneously edited, Figures 3 (a) to (c) show an input bin added to the macro block in the hierarchy being edited with the circuit diagram editor of this embodiment. FIG. 6 is a display diagram showing that an outer end input terminal is automatically generated in a macroblock that is referenced in the hierarchy. A, B, E...logic element, A1...moved 7 logic element, Dl,, D2...macroblock data, MAl
, MA2. MA3...mask block, Pl...external terminal, P2...macro terminal block), 81-S6 processing step.

Claims (1)

[Claims] When a mask block to be input/edited is selected in the layer where a hierarchically designed logic circuit is being edited in the VLSI logic design process, the data in that mask block is displayed, and the layer and layer where the editing is being performed are displayed. The data in the macroblock referenced in that layer is input and edited at the same time, and the macro terminal of the macroblock in the layer being edited is linked with the external terminal of the macroblock referenced in that layer. A circuit diagram editor characterized in that a circuit diagram is automatically generated or deleted.