JPH10335697A - Led array and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable an LED array to be lessened in manufacturing cost and simplified in manufacturing process. SOLUTION: P-type semiconductor layers 13 are formed in a line on an N-type semiconductor block 11, and a first interlayer insulating film 12 provided with first openings 16a and N-side openings 17 is formed thereon. P-side electrodes 14 connected to the P-type semiconductor layers 13 through the first openings 16a and N-side electrodes 55 (N-side contact, electrodes 55a and N-side pad electrodes 55b) connected to the N-type semiconductor block 11 through the N-side openings 17 arc formed on the first interlayer insulating film 12. Furthermore, s P-side matrix wiring 4 connected to the prescribed P-side electrodes 14 is formed through the intermediary of a second interlayer insulating film 18. The P-side electrodes 14 and the N-side electrodes 55 are formed of the same conductive film material and through the same film forming process and patterning process. The P-side electrodes 14 and the N-side electrodes are formed of film of Au or Au alloy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LED array in which a plurality of LEDs (light emitting diodes) are formed on the same semiconductor substrate and a method of manufacturing the same, and more particularly, to an electrode connected to a semiconductor substrate of a first conductivity type, The present invention relates to an LED array in which an electrode connected to a semiconductor layer is formed on the surface of a semiconductor substrate on which LEDs are formed, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A light emitting diode (hereinafter simply referred to as LED) array is used as an exposure light source (print head) for a photosensitive drum in an electrophotographic printer. FIG. 28 is a diagram showing an example of the structure of a conventional LED array.
(A) is a top view, and (b) is a cross-sectional view taken along AA 'in (a). The LED array shown in FIG.
This corresponds to [DPI] ([Dot / Inch]) and below, and has a configuration in which the LEDs 110 are arranged in a line on the n-type semiconductor substrate 102.

In FIG. 28, a plurality of p-type semiconductor layers 113 are formed on an n-type semiconductor substrate 102, and an interlayer insulating film 112 having an opening 116 is formed on the surface of the n-type semiconductor substrate 102. . On the interlayer insulating film 112, a plurality of p-side electrodes (individual electrodes) 114 that are individually connected to the p-type semiconductor layer 113 in the openings 116 are formed. An n-side electrode (common electrode) 115 is formed on the entire back surface of the n-type semiconductor substrate 102. L
When a voltage is applied between the p-side electrode 114 and the n-side electrode 115, the ED 110 causes a light emission phenomenon at the junction surface between the n-type semiconductor substrate 102 and the p-type semiconductor layer 113, and this emitted light is
It radiates from the surface of the type semiconductor layer 113 to the outside. p-side electrode 1
14 is formed of an aluminum (Al) film or an Al alloy film, and the n-side electrode 115 is formed of a gold (Au) film or Au.
It is formed by an alloy film.

However, in the case of an LED array having a very high density of 1200 [DPI] or more, the pitch of the p-side electrode and p
Since the space for routing the side electrode is narrowed, p
It becomes difficult to provide a bonding pad (p-side pad electrode) for each side electrode. Therefore, 1200 [DPI]
In the corresponding LED array, the structure as shown in FIG. 29 is adopted to reduce the number of p-side pad electrodes. FIG.
(A) is a top view which shows an example of the conventional LED array corresponding to 1200 [DPI]. FIG. 29 (b) shows A in FIG.
FIG. 29C is a cross-sectional view taken along the line A-A ′, and FIG.
It is sectional drawing between B '.

The LED array shown in FIG. 29 is one in which a plurality of LEDs are formed in a plurality of n-type semiconductor blocks 111 which are element-isolated from each other by a high-resistance semiconductor substrate 132 and an isolation groove 103. n-type semiconductor block 1
11, a plurality of p-type semiconductor layers 113, a p-side electrode 144 individually connected to the p-type semiconductor layer 113, and an n-side contact electrode 145a connected to the n-type semiconductor block 111.
And an n-side pad electrode 145b connected to the n-side contact electrode 145a. Multiple ps in a block
Of the side electrodes 144, only a predetermined number of p-side electrodes have p-side pad electrodes 144b (in FIG. 29, one p-side pad electrode 144b is formed per block). n
Side contact electrode 145a and n-side pad electrode 145
The n-side electrode 145 constituted by b
This is a common electrode for the ED. Further, a p-side electrode 144 connected to a predetermined p-side electrode 144 between the blocks at the via hole 121 is formed.
The p-side matrix wiring 104 is formed, and the p-side electrode 144 having no p-side pad electrode is connected to the p-side electrode 144 having the p-side pad electrode of another n-type semiconductor block 111 by the p-side matrix wiring 104. I have. Between the n-type semiconductor block 111 and the p-side matrix wiring 104,
A first interlayer insulating film 142 is formed, and a second interlayer insulating film 148 is formed between the p-side matrix wiring 104 and the p-side electrode 144.

[0006]

However, in the above-mentioned conventional LED array, the p-side electrode and the n-side electrode are separately formed of different conductive film materials, and the LED shown in FIG.
In the ED array, since the n-side contact electrode and the n-side pad electrode are formed separately, there is a problem that the number of manufacturing steps is increased and the manufacturing cost is increased.

An object of the present invention is to solve such a conventional problem, and an object of the present invention is to provide an LED array and a method for manufacturing the same, which can reduce the cost and simplify the manufacturing process.

[0008]

In order to achieve the above object, an LED array according to the present invention comprises a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and a side on which the semiconductor layer is formed. A first conductive side contact electrode connected to the semiconductor substrate and a second conductive side electrode connected to the semiconductor layer are formed on the surface of the semiconductor substrate, wherein the first conductive side contact electrode and the The two conductive side electrodes are made of the same conductive film material.

Further, another LED array according to the present invention comprises:
Forming a second conductive type semiconductor layer on a conductive type semiconductor substrate;
A first conductive side electrode comprising a first conductive side contact electrode connected to the semiconductor substrate and a first conductive side pad electrode connected to the first conductive side contact electrode, on the surface of the semiconductor substrate on which the semiconductor layer is formed. Wherein the first conductive side electrode has a single layer structure in which the first conductive side contact electrode and the first conductive side pad electrode are integrally formed by the same conductive film. Of course, the first conductive side contact electrode, the first conductive side pad electrode, and the second conductive side electrode may be formed of the same conductive film. As the conductive film, for example, Au
A film or an Au alloy film is used.

Next, a method of manufacturing an LED array according to the present invention comprises forming a second conductive type semiconductor layer on a first conductive type semiconductor substrate, and forming the second conductive type semiconductor layer on the semiconductor substrate surface on the side where the semiconductor layer is formed. In a method for manufacturing an LED array in which a first conductive side contact electrode connected to a semiconductor substrate and a second conductive side electrode connected to the semiconductor layer are formed, the first conductive side contact electrode and the second conductive side electrode are formed on a surface of the semiconductor substrate. A step of forming a first conductive side contact electrode and the second conductive side electrode at the same time by forming a conductive film to be a second conductive side electrode and patterning the conductive film is performed. .

In another method of manufacturing an LED array according to the present invention, a semiconductor layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, and a surface of the semiconductor substrate on the side where the semiconductor layer is formed is provided on the semiconductor substrate. In the method for manufacturing an LED array, a first conductive side electrode formed of a first conductive side contact electrode connected to the semiconductor substrate and a first conductive side pad electrode connected to the first conductive side contact electrode is formed. A step of forming a conductive film to be the first conductive side electrode on a surface and patterning the conductive film to form the first conductive side electrode in a single-layer structure is performed. Of course, the first conductive side contact electrode, the first conductive side pad electrode, and the second conductive side electrode may be simultaneously formed by patterning the same formed conductive film.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment FIG. 1 is a top view showing a structure of an LED array 1 according to a first embodiment of the present invention. The LED array 1 includes a semiconductor substrate 2
The n-type semiconductor blocks 11 arranged in a line above have LE
This is an LED array corresponding to 1200 [DΡI] in which a plurality of D10s are formed. The LED array 1 includes LEDs
The p-side electrode 14 and the n-side electrode 15 of the semiconductor substrate 2
In the same plane. The semiconductor substrate 2 is obtained by forming an n-type semiconductor substrate 2a such as an epitaxial layer on a high-resistance semiconductor substrate 2b. n-type semiconductor block 1
Reference numeral 1 denotes a divided n-type semiconductor substrate 2a. The n-type semiconductor block 11 is electrically separated from the high-resistance semiconductor substrate 2b by a separation groove (etching groove) 3. The LED array 1 has an n-type first conductivity type.
This is an LED array in which the second conductivity type is a p-type.

In the n-type semiconductor block 11, N
(N is a positive integer) LEDs 10 are formed. In FIG. 1, N = 3. In the n-type semiconductor block 11,
N p-type semiconductor layers (p-type semiconductor regions) 13 are formed in a line by a diffusion method or the like. On the n-type semiconductor block 11, a first interlayer insulating film 12 is formed. In the first interlayer insulating film 12, a first opening 16a for exposing substantially the entire surface of the p-type semiconductor layer 13 and an n-side opening 17 for exposing the surface of the n-type semiconductor block 11 are formed.

On the first interlayer insulating film 12, N p-side electrodes 14, an n-side contact electrode 15a, and an n-side pad electrode 15b are formed. The p-side electrode 14 is connected to the p-type semiconductor layer 13 at the first opening 16a.
The n-side contact electrode 15 a is formed on the n-side opening 17 and is connected to the n-type semiconductor block 11.
The n-side pad electrode 15b partially overlaps the n-side contact electrode 15a,
a. The n-side contact electrode 15a and the n-side pad electrode 15b constitute an n-side electrode 15 having a laminated structure.

On the first interlayer insulating film 12 on which the p-side electrode 14 and the n-side electrode 15 are formed, a second interlayer insulating film 18 is formed. The second interlayer insulating film 18 has a second opening 16b exposing almost the entire area of the first opening 16a.
A p-side pad opening 19 for exposing the pad electrode of the p-side electrode 14, an n-side pad opening 20 for exposing the n-side pad electrode 15b, and the first interlayer insulating film 1 of the p-side electrode 14.
2 and a via hole 21 for exposing a portion formed on the substrate. First opening 16a and second opening 16
b forms the p-side opening 16. On the second interlayer insulating film 18, M (M is an integer equal to or greater than N) p-side matrix wirings 4 are formed. In the LED array 1 of FIG. 1, M = 9. The p-side matrix wiring 4 is formed over all the n-type semiconductor blocks 11, and is connected to the p-side electrode 14 at the via hole 21.

The LED 10 includes an n-type semiconductor block 11 common to the N LEDs 10 and the n-type semiconductor block 1.
1, a p-type semiconductor layer 13 individually formed on the p-type semiconductor layer 13, a p-type electrode 14 individually formed on the p-type semiconductor layer 13, and an n-type semiconductor commonly formed on the N LEDs 10 in the n-type semiconductor block 11. And an electrode 15. p-type semiconductor layer 1
The depth dimension of 3 is smaller than the thickness dimension of the n-type semiconductor block 11. Therefore, the p-type semiconductor layer 13 is formed in the n-type semiconductor block 11 in a floating island shape. p-type electrode 14
When a voltage is applied between the P-type semiconductor layer 13 and the n-type electrode 15, a light-emitting phenomenon occurs at the junction surface between the p-type semiconductor layer 13 and the n-type semiconductor block 11, and the emitted light is radiated outside from the surface of the p-type semiconductor layer 13. You.

The LED array 1 is different from the conventional LED array in that the p-side electrode 14 and the n-side contact electrode 15 are formed of the same conductive film material. As the conductive film serving as the p-side electrode 14 and the n-side contact electrode 15, a conductive film capable of ohmic contact, for example, an Au film or an Au alloy film is used for both the p-type semiconductor layer 13 and the n-type semiconductor block 11. Here, the Au alloy film includes a laminated metal film or a laminated alloy film. As the Au alloy film, titanium (Ti) and platinum (Pt) are used.
Metal film of Au and Au (hereinafter referred to as Ti / Pt / Au film), or a laminated alloy film of an alloy film of Au, germanium (Ge), nickel (Ni) and an Au film (hereinafter Α)
uGeNi / Au film) or a laminated alloy film of an alloy film of Δu and Ge, a Ni film, and an Au film (ΔuGe / Ni film)
/ Au film).

The manufacturing process of the LED array 1 according to the first embodiment shown in FIG. 1 will be described below. FIG. 2 to FIG.
FIG. 4 is a diagram illustrating an example of a manufacturing process of the ED array 1. In each of the drawings, (a) is a top view, and (b) is a cross-sectional view along AA ′ in (a). FIG.
FIG. 10C is a cross-sectional view taken along line BB ′ in FIG. 8A, and FIG. 10C is a cross-sectional view taken along line BB ′ in FIG.

First, as shown in FIG. 2, a semiconductor substrate 2 having an n-type semiconductor substrate 2a on a high-resistance semiconductor substrate 2b is manufactured. Here, a semi-insulating GaAs substrate is used as the high-resistance semiconductor substrate 2b. Also, this semi-insulating GaAs
An n-type AlGaAs layer is epitaxially grown on the substrate, and this AlGaAs epitaxial layer is used as an n-type semiconductor substrate 2a. The thickness of the n-type semiconductor substrate 2a (n-type epitaxial layer) is, for example, about 3 [μm].

Next, as shown in FIG. 3, the n-type semiconductor substrate 2
A first interlayer insulating film 12 serving as a diffusion mask 25 is formed on the surface of a, and the first opening 16a and the diffusion mask 25 are formed by patterning the first interlayer insulating film 12 by photolithography and etching. As the first interlayer insulating film 12 (diffusion mask 25), for example, an aluminum nitride film (AlN
Film). This AlN film is formed by a sputtering method, and its thickness is, for example, about 500 to 3000 [Å].

Next, as shown in FIGS. 4 to 6, a p-type semiconductor layer 13 is formed on the n-type semiconductor 2a. Here Zn
The solid phase diffusion method is used. That is, a Δn diffusion source film 26 is formed on the surface of the n-type semiconductor substrate 2a on which the first opening 16a has been formed, and an annealing cap film 27 is further formed thereon.
Is formed. The Ζn diffusion source film 26 is, for example, ZnO
Forming a SiO ₂ mixed film; This ZnO—SiO ₂ mixed film is made of zinc oxide (ZnO) and silicon oxide (Si).
O ₂₎ and a 1: film mixed in 1, is formed by sputtering. As the annealing cap film 27, for example, a silicon nitride film (SiN
Film). The thickness of the ZnO—SiO ₂ mixed film is, for example, about 500 to 3000 [Å], and the thickness of the SiN film is, for example, 500 to 3000 [Å].
It is about.

Subsequently, high-temperature annealing is performed on the n-type semiconductor substrate 2a on which the annealing cap film 27 has been formed,
(4) Zn is diffused from the n-diffusion source film 26 into the n-type semiconductor substrate 2a. In the first opening 16a, Zn diffuses into the n-type semiconductor substrate 2a, but in the region where the diffusion mask 25 is formed, Zn does not diffuse, so that Zn diffuses into the first opening 16a of the n-type semiconductor substrate 2a. A p-type semiconductor layer 13 is selectively formed in a corresponding region. The conditions of the high-temperature annealing are, for example, an annealing temperature of 700 [° C.] and an annealing time of 2 hours under a nitrogen atmospheric pressure. By this annealing condition, the depth is about 1 [μm] and the surface Zn concentration is 10
The p-type semiconductor layer 13 of ²⁰ [cm ³ ] is formed. Since the thickness of the n-type semiconductor substrate 2a is about 3 [μm] as described above, the depth dimension of the p-type semiconductor layer is
Smaller than the thickness dimension of. Note that the annealing cap film 2
7 prevents Zn from diffusing into the annealing atmosphere.

Next, as shown in FIG. 7, the p-type semiconductor layer 13 is formed.
In the n-type semiconductor substrate 2a where the formation of the diffusion source film 26 and the annealing cap film 2 are formed on the surface,
7 is entirely removed by, for example, a selective wet etching method, leaving only the first interlayer insulating film 12 (diffusion mask 25). An etchant that does not selectively etch the first interlayer insulating film 12, for example, buffered hydrofluoric acid is used.

Next, as shown in FIG. 8, in the n-type semiconductor substrate 2a from which the diffusion source film 26 and the annealing cap film 27 have been removed, an n-side opening 17 is formed in the interlayer insulating film 12 by photolithography and etching. I do. The n-side opening 17 is formed in a region where the n-type contact electrode 15a is to be formed, and connects the n-type contact electrode 15a to be formed thereafter to the n-type semiconductor substrate 2a. As a result, the p-type semiconductor layer 1 is
This means that the first opening 16a opening the three surfaces and the n-side opening 17 opening the surface of the n-type semiconductor substrate 2a are formed.

Next, as shown in FIG. 9, the p-side electrode 14 is formed on the entire surface of the n-type semiconductor substrate 2a where the n-side opening 17 has been formed.
And a conductive film to be the n-side contact electrode 15a is formed, and the conductive film is patterned by a lift-off method.
The p-side electrode 14 and the n-side contact electrode 15a are formed. That is, a photoresist pattern is formed using a region other than the region where the p-side electrode 14 and the n-side contact electrode 15a are to be formed, and a conductive film serving as the p-side electrode 14 and the n-side contact electrode 15a is formed over the entire surface. The photoresist and the conductive film formed thereon are lifted off to form the p-side electrode 14 and the n-type contact electrode 15a. The p-side electrode 14 is formed so that a part thereof overlaps the surface of the p-type semiconductor layer 13 in the first opening 16a.
a is formed so as to cover the entire surface of the n-side opening 17. p
As the conductive film to be the side electrode 14 and the n-type contact electrode 15a, for example, the above-described Au alloy film is used. Thereafter, the p-side electrode 14 is ohmically connected to the p-type semiconductor layer 13 at the first opening 16a, and the n-side contact electrode 15a is ohmically connected to the n-type semiconductor substrate 2a at the n-side opening 17 ( Heat treatment).

As described above, the manufacturing process of the LED array 1 is based on the same conductive film material (Au alloy in this example).
The point that the p-side electrode 14 and the n-side contact electrode 15a are formed simultaneously is different from the conventional LED array manufacturing process. In the case where the p-side electrode and the n-side contact electrode are formed of different conductive film materials as in the related art, the steps of forming and patterning the conductive film need to be performed twice. When the p-side electrode 14 and the n-side contact electrode 15a are formed of the same conductive film material as described above, the film forming and patterning steps need only be performed once, and the steps can be simplified.

Next, as shown in FIG. 10, a conductive film serving as an n-side pad electrode 15b is formed on the n-type semiconductor substrate 2a on which the p-type electrode 14 and the n-type contact electrode 15a have been formed. The film is patterned by a lift-off method to form an n-side pad electrode 15b. Thereafter, a sintering process is performed. Part of the n-side pad electrode 15b is n
It is formed so as to overlap with the side contact electrode 15a, and is ohmic-connected to the n-side contact electrode 15a at the overlap portion. The n-side contact electrode 15a and the n-side pad electrode 15b form an n-side electrode 15 having a laminated structure.

As the conductive film to be the n-side pad electrode 15b, for example, the same Au alloy film as the n-side contact electrode 15a is used. Of course, the n-type electrode pad electrode 15b has
An Au film, another Au alloy film different from the n-side contact electrode 15a, or a metal or alloy other than the Au alloy may be used. However, it is necessary that the connection can be made ohmic with the n-side contact electrode 15a, and that the connection portion with the n-side contact electrode 15a does not cause disconnection due to electromigration or the like or does not cause disconnection in the n-side contact electrode 15a. For example, for the n-side contact electrode 15a of the Au alloy film,
After the formation of the side contact electrode 15a, the subsequent heat treatment (specifically, the heat treatment in the step of forming the second interlayer insulating film 18 shown in FIG. 12) causes Au to be connected to the Al side at the connection portion between the Au alloy film and the Al film. To cause disconnection.

Next, as shown in FIG. 11, the high-resistance semiconductor substrate 2 is formed on the n-type semiconductor substrate 2a on which the n-side electrode 15 has been formed.
The n-type semiconductor substrate 2a is divided into the n-type semiconductor blocks 11 by forming the separation groove 3 reaching to "b". In other words, the first region in the region where the isolation groove is to be formed by photolithography and etching
The interlayer insulating film 12 and the n-type semiconductor substrate 2a thereunder are etched to expose the high-resistance semiconductor substrate 11b. Thus, the n-type semiconductor block 11 is electrically separated from each other by the separation groove 3 and the high-resistance semiconductor substrate 2b. N-type semiconductor block 11 (n-type semiconductor substrate 2a) having a thickness of about 3 [μm] and a film thickness of 500 to 300
For the first interlayer insulating film 12 of about 0 [０], the depth of the isolation groove 3 is, for example, about 3.5 [μm]. Separation groove 3
Is limited by the distance between the p-type semiconductor layers 13. 1
In a 200 [DPI] LED array, the pitch dimension of the p-type semiconductor layer 13 is about 21 [μm], and if the width of the p-type semiconductor layer 13 is about 8 [μm], the width of the separation groove 3 is 13 [μm]. [Μm].

Next, as shown in FIG. 12, a second interlayer insulating film 18 is formed on the entire surface of the semiconductor substrate 2 on which the isolation trenches 3 have been formed. Part 1
6a, and a p-side pad opening 19 that opens the pad electrode portion of the p-side electrode 14
Then, an n-side pad opening 20 for opening the n-side pad electrode 15b and a via hole 21 reaching the p-side electrode 14 are formed. As the second interlayer insulating film 18, for example, a polyimide film is used. The polyimide film is formed and patterned as follows using, for example, polyimide dissolved in a photoresist developing solution (alkaline solution). A polyimide source is spin-coated on a semiconductor substrate 2 (wafer),
Pre-bake at about 00 [° C]. Next, a photoresist is spin-coated on the pre-baked polyimide film, and this photoresist is exposed so that the opening and the via hole 21 are formed into a pattern. During the development of the photoresist, the polyimide film region where the resist is not formed is also removed, and the polyimide film is patterned. Next, the remaining resist is removed, and the patterned polyimide film is baked at about 350 ° C.

Finally, as shown in FIG. 13, the entire surface of the semiconductor substrate 2 after the patterning of the second interlayer
A conductive film to be the side matrix wiring 4 is formed, and the conductive film is patterned by a lift-off method to form the p-side matrix wiring 4. Thereafter, a sintering process is performed to make ohmic connection of the p-side matrix wiring 4 to the p-side electrode 14 in the via hole 21. As the conductive film to be the p-type matrix wiring 4, for example, an Au alloy film is used. Of course, the conductive film serving as the p-side matrix wiring 4 need not be an Au alloy film as long as it can be ohmic-connected to the p-side electrode 14 and does not cause disconnection at the connection portion. As described above, the LED array 1 shown in FIG. 1 is manufactured.

Next, the operation of the LED array 1 will be briefly described. The n-type semiconductor blocks 11 are denoted by 11-1, 11-2, 11-3,... from the right side of FIG. Also, n
In the semiconductor block 11, the LEDs 10 are 10-1, 10-2, and 10-3 in order from the right side in FIG. 1, and the p-side electrodes 14 are 14-1, 14-2, and 1 in order from the right side in FIG.
4-3, and the p-side pad electrodes 14b are 14b-1 and 14b-2 in order from the right side in FIG. Also, the p-side matrix wirings 4 are arranged in order from the lower side in FIG.
And

In the n-type semiconductor block 11-1, p
The side electrode 14-1 is connected to the p-side matrix wiring 4-1.
The p-side electrode 14-2 is connected to the p-side matrix wiring 4-2, and the p-side electrode 14-3 is connected to the p-side matrix wiring 4-3.
Connected to In the n-type semiconductor block 11-2, the p-side electrode 14-1 is connected to the p-side matrix wiring 4-4, and in the n-type semiconductor block 11-3, the p-side electrode 14-1 is connected to the p-side matrix wiring 4-7. Connected.
Further, in an n-type semiconductor block 11-4 (not shown), similarly to the n-type semiconductor block 11-1, the p-side electrode 14-1 is connected to the p-side matrix wiring 4-1 and the p-side matrix wiring 4-2. And the p-side electrode 14-3
Is connected to the p-side matrix wiring 4-3.

In n-type semiconductor blocks 11-1 to 11-3, p-side electrodes 14-1 and 14-2 have p-side pad electrodes. N-type semiconductor block 1 not shown
In 1-4 to 11-6, the p-side electrodes 14-2 and 1
4-3 has a p-side pad electrode, and in an n-type semiconductor block 11-7 to 11-9 (not shown), a p-side electrode 14- is provided.
1 and 14-3 have p-side pad electrodes.

For example, L of the n-type semiconductor block 11-1
To turn on the ED 10-1, the n-type semiconductor block 1
1-1 p-side electrode 14-1 (the p-side pad electrode 14b
-1) and the n-side electrode 15 of the n-type semiconductor block 11-1
(The n-side pad electrode 15b). At this time, an n-type semiconductor block 11-4 (not shown)
If the LED 10-1 is turned on simultaneously, the n-side electrode 15 of the n-type semiconductor block 11-4 may be set to the same potential as the n-side electrode 15 of the n-type semiconductor block 11-1. This is because the p-side electrode 14-1 of the n-type semiconductor block 11-4 is connected to the p-side electrode 14-1 of the n-type semiconductor block 11-1 by the p-side matrix wiring 4-1. . LED of n-type semiconductor block 11-1
If the LED 10-1 of the n-type semiconductor block 11-4 is turned off while the light 10-1 is turned on, then n
The n-side electrode 15 of the type semiconductor block 11-4 may be opened.

The LE of the n-type semiconductor block 11-1 is
To turn on D10-3, the p-side matrix wiring 4-
3 and has another p-side pad electrode 14b.
Electrode 14 of the n-type semiconductor block 11-4, for example, the p-side electrode 14 of the n-type semiconductor block 11-4 (not shown)
-3 and an n-side electrode 15 of the n-type semiconductor block 11-1.

As described above, according to the first embodiment, the p-side electrode 14 and the n-side contact electrode 15a are formed of the same conductive film in the same step, thereby simplifying the manufacturing process. And therefore low cost can be realized. Further, the p-side electrode 14 and the n-side contact electrode 1
By forming the substrate 5a in the same step, it is possible to reduce variation in characteristics between substrates (wafers).

The LED array 1 according to the first embodiment has a structure in which the p-side electrode and the n-side pad electrode are formed on the opposite side of the p-type semiconductor layer. It may be provided on the same side as the p-side electrode with respect to the type semiconductor layer.

Second Embodiment FIG. 14 is a top view showing the structure of an LED array 31 according to a second embodiment of the present invention. In FIG. 14, FIG.
The same components as those described above are denoted by the same reference numerals. LED array 3
1, the n-side pad electrode 15b is provided on the same side of the p-type semiconductor layer 13 as the p-side electrode 14 in the LED array 1 of the first embodiment shown in FIG. Accordingly, of the three p-side electrodes 14 in the n-type semiconductor block 11, the number of the p-side electrodes 14 having the p-side pad electrodes 14b is reduced from two to one. That is, in the n-type semiconductor block 11, only the p-side electrode 14-1 has the p-side pad electrode 14b. n-type semiconductor block 11-
The first p-side electrode 14-1 is connected to the p-side matrix wiring 4-1 and the p-side electrode 14-1 of the n-type semiconductor block 11-2.
1 is connected to the p-side matrix wiring 4-2. Similarly,
P-side electrode 14 of n-type semiconductor block 11-9 not shown
-1 is connected to the p-side matrix wiring 4-9. Also,
In the n-type semiconductor block 11-1, the p-side electrode 14-
2 is connected to the p-side matrix wiring 4-4, and the p-side electrode 1
4-3 is connected to the p-side matrix wiring 4-5. Similarly, in an unillustrated n-type semiconductor block 11-4,
The p-side electrode 14-2 is connected to the p-side matrix wiring 4-7, the p-side electrode 14-3 is connected to the p-side matrix wiring 4-8, and in the n-type semiconductor block 11-5 (not shown), The electrode 14-2 is a p-side matrix wiring 4-9.
And the p-side electrode 14-3 is connected to the p-side matrix wiring 4
-1. The manufacturing process of the LED array 31 is the same as that of the first embodiment.

As described above, according to the second embodiment, the structure in which the n-side pad electrode 15b is provided on the same side as the p-side electrode 14 with respect to the p-type semiconductor layer 13 is used.
The chip size can be made smaller than in the embodiment.

Third Embodiment FIG. 15 is a top view showing the structure of an LED array 41 according to a third embodiment of the present invention. In FIG. 15, FIG.
The same components as those in FIG. 14 are denoted by the same reference numerals. The LED array 41 according to the third embodiment includes the LEDs shown in FIG.
In the array 1, the n-side electrode 15 is an n-side electrode 55 including an n-side contact electrode 55a and an n-side pad electrode 55b, the p-side electrode 14 is a p-side electrode 54, and the p-side matrix wiring 4 is a p-side matrix wiring. 44.

The LED array 41 is characterized in that the n-side electrode 55 has a single layer structure by integrally forming the n-side contact electrode 55a and the n-side pad electrode 55b of the n-side electrode 55 with the same conductive film material. It is different from the conventional LED array. As the conductive film to be the n-side contact electrode 55a and the n-side pad electrode 55b, a conductive film capable of ohmic contact with the n-type semiconductor block 11, for example, Au
A film or an Au alloy film is used. As the Au alloy film, a Ti / Pt / Au film or @ uGeNi / Au
Film, or a @ uGe / Ni / Au film. Also,
The same conductive film material as that of the n-side electrode 55 or a different conductive film material may be used for the p-side electrode 54. The operation of the LED array 41 is the same as that of the LED array 1 of the first embodiment.

The manufacturing process of the LED array 41 according to the third embodiment shown in FIG. 15 will be described below. 16 to 2
0 is a diagram showing an example of a manufacturing process of the LED array 41. In each of the drawings, (a) is a top view, (b) is a cross-sectional view taken along line AA ′ in (a), and (c) is a cross-sectional view taken along line BB ′ in (a).

First, as shown in FIG. 16, in the same manner as in the manufacturing steps shown in FIGS. 2 to 8 in the first embodiment, an n-type n-type semiconductor substrate 2b made of a semi-insulating GaAs substrate is formed. A semiconductor substrate 2 on which an n-type semiconductor substrate 2b made of an AlGaAs epitaxial layer is formed,
A diffusion mask 25 (first interlayer insulating film 12) and a first opening 16a are formed on the surface of the n-type semiconductor substrate 2a.
First opening 1 of n-type semiconductor substrate 2a by n solid phase diffusion method
A p-type semiconductor layer 13 is formed in the region 6a, and an n-side opening 17 is formed in the first interlayer insulating film 12.

Next, as shown in FIG.
Is formed on the surface of the n-type semiconductor substrate 2a on which the
A conductive film 4 is formed, and the conductive film is patterned by a lift-off method to form a p-type electrode 54. Thereafter, a sintering process is performed. For example, an Al film is used as the conductive film. Of course, an Au alloy may be used as in the first embodiment.

Next, as shown in FIG. 18, an n-side electrode 55 is formed on the surface of the n-type semiconductor substrate 2a on which the p-type electrode 54 has been formed.
(The n-side contact electrode 55a and the n-side pad electrode 55
A conductive film as shown in b) is formed, and the conductive film is patterned by a lift-off method to form an n-side electrode 55 having a single-layer structure. Thereafter, a sintering process is performed. The n-side contact electrode 55a is formed so as to cover the entire surface of the n-side opening 17, and is ohmically connected to the n-type semiconductor substrate 2a at the n-side opening 17. Also, the n-side contact electrode 55a
The n-side pad electrode 55 b connected to the first interlayer insulating film 1 on the side opposite to the p-side electrode 54 with respect to the p-type semiconductor layer 13 is formed.
2 is formed. As the conductive film to be the n-type electrode 55, for example, the above-described Au alloy film is used.

As described above, the manufacturing process of the LED array 41 is performed by using the same conductive film material (Au alloy in this example).
n-side contact electrode 55a and n-side pad electrode 55b
Are formed integrally at the same time, and the n-side electrode 55 is formed not in a laminated structure but in a single layer structure, which is different from the conventional LED array manufacturing process. In the case where the n-side electrode is formed by lamination as in the related art, a step of forming a conductive film and patterning it has to be performed twice. However, as in the LED array 41, the n-side contact electrode 55a and the If the n-side pad electrode 55b is formed of the same conductive film material and the n-side electrode 55 has a single-layer structure, the film forming and patterning steps need only be performed once, and the steps can be simplified.

Next, as shown in FIG. 19, similar to the procedure shown in FIGS. 11 and 12 of the first embodiment,
A block isolation groove 3 is formed in the semiconductor substrate 2 on which the n-type electrode 55 has been formed, a second interlayer insulating film 18 is formed thereon, and a second opening 16 b is formed in the second interlayer insulating film 18. p
A side pad opening 19, an n-side pad opening 20, and a via hole 21 are formed.

Finally, as shown in FIG. 20, the entire surface of the semiconductor substrate 2 after the patterning of the second interlayer
A conductive film to be the side matrix wiring 44 is formed, and the conductive film is patterned by a lift-off method to form the p-side matrix wiring 44. Thereafter, a sintering process is performed.
As the conductive film to be the p-type matrix wiring 44, for example, an Al film is used. Of course, the conductive film serving as the p-side matrix wiring 44 need not be an Al film as long as it can be ohmic-connected to the p-side electrode 54 and does not cause disconnection at the connection portion. As described above, the LED array 4 shown in FIG.
1 is manufactured.

As described above, according to the third embodiment, the n-side contact electrode 55a and the n-side pad electrode 55b are integrally formed by the same conductive film in the same step.
Has a single-layer structure, the manufacturing process can be simplified, and therefore, low cost can be realized. Further, by forming the n-side contact electrode 55a and the n-side pad electrode 55b in the same step, it is possible to reduce the variation in characteristics between substrates (wafers).

The LED array 41 according to the third embodiment has a structure in which the p-side electrode and the n-side pad electrode are formed on the opposite side to the p-type semiconductor layer. It may be provided on the same side as the p-side electrode with respect to the type semiconductor layer.

Fourth Embodiment FIG. 21 is a top view showing the structure of an LED array 51 according to a fourth embodiment of the present invention. In FIG. 21, the same components as those in FIGS. 1, 14, and 15 are denoted by the same reference numerals. The LED array 51 is the same as the LED array 41 of the third embodiment shown in FIG.
Are provided on the same side as the p-side electrode 54 with respect to the p-type semiconductor layer 13. Accordingly, the p-side electrode 54 having the p-side pad electrode 54b among the three p-side electrodes 54 in the n-type semiconductor block 11 is similar to the LED array 31 of the second embodiment shown in FIG. It has been reduced from two to one. That is, in the n-type semiconductor block 11, only the p-side electrode 54-1 has the p-side pad electrode 14b. The operation of the LED array 51 is the same as that of the LED array 31 of the second embodiment. In addition, LED
The manufacturing process of the array 51 is the same as that of the third embodiment.

As described above, according to the fourth embodiment, the n-side pad electrode 55b is provided on the same side of the p-type semiconductor layer 13 as the p-side electrode 54.
The chip size can be made smaller than in the embodiment.

Fifth Embodiment FIG. 22 is a top view showing the structure of an LED array 61 according to a fifth embodiment of the present invention. In FIG. 22, the same components as those in FIGS. 1, 14, 15, and 21 are denoted by the same reference numerals. In the LED array 61 of the fifth embodiment, in the LED array 1 shown in FIG. 1, the n-side electrode 15 is an n-side electrode 55 including an n-side contact electrode 55a and an n-side pad electrode 55b.

In the LED array 61, the n-side electrode 55 has a single-layer structure by integrally forming the n-side contact electrode 55a and the n-side pad electrode 55b of the n-side electrode 55 with the same conductive film material. Side electrode 55 and p-side electrode 1
4 is formed of the same conductive film material as the conventional L.
Different from ED arrays. n-side contact electrode 55a, n
The n-type semiconductor block 11 and the p-type semiconductor layer 13 are used as a conductive film to be the side pad electrode 55 b and the p-side electrode 14.
In each case, a conductive film capable of ohmic contact, for example, an Au film or an Au alloy film is used. As the above Au alloy film, a Ti / Pt / Au film or @uGeN
an i / Au film or a @ uGe / Ni / Au film. The operation of the LED array 61 is the same as that of the LED array 1 of the first embodiment.

The manufacturing process of the LED array 61 of the fifth embodiment shown in FIG. 22 will be described below. 23 to 2
6 is a diagram illustrating an example of a manufacturing process of the LED array 61. In each of the drawings, (a) is a top view, (b) is a cross-sectional view taken along line AA ′ in (a), and (c) is a cross-sectional view taken along line BB ′ in (a).

First, as shown in FIG. 23, an n-type n-type semiconductor substrate 2b made of a semi-insulating GaAs substrate is formed in the same manner as in the manufacturing steps shown in FIGS. 2 to 8 in the first embodiment. A semiconductor substrate 2 on which an n-type semiconductor substrate 2b made of an AlGaAs epitaxial layer is formed,
A diffusion mask 25 (first interlayer insulating film 12) and a first opening 16a are formed on the surface of the n-type semiconductor substrate 2a.
First opening 1 of n-type semiconductor substrate 2a by n solid phase diffusion method
A p-type semiconductor layer 13 is formed in the region 6a, and an n-side opening 17 is formed in the first interlayer insulating film 12.

Next, as shown in FIG.
The n-side electrode 5 is formed on the surface of the n-type semiconductor substrate 2a on which the
5 (n-side contact electrode 55a and n-side pad electrode 5
5b) and a conductive film to be the p-side electrode 14 are formed, and the conductive film is patterned by a lift-off method to form the n-side electrode 55 and the p-side electrode 14. Thereafter, a sintering process is performed. As the conductive film, for example, the above-described Au alloy film is used.

As described above, the manufacturing process of the LED array 61 uses the same conductive film material (Au alloy in this example).
The point that the n-side contact electrode 55a, the n-side pad electrode 55b, and the p-side electrode 14 are formed simultaneously and the n-side electrode 55 is formed in a single layer structure is different from the conventional LED array manufacturing process. Conventionally, in order to form a p-side electrode and an n-side electrode having a multilayer structure, a process of forming a conductive film and patterning the conductive film had to be performed three times in total.
Like the ED array 61, the n-side electrode 55 and the p-side electrode 1
If the electrode 4 is formed of the same conductive film material and the n-side electrode 55 has a single-layer structure, the film forming and patterning steps need only be performed once, and the steps can be simplified.

Next, as shown in FIG. 25, similar to the procedure shown in FIGS. 11 and 12 of the first embodiment,
The block isolation groove 3 is formed in the n-type semiconductor substrate 2a on which the n-type electrode 55 has been formed, and the second interlayer insulating film 18 is formed thereon.
Is formed, and a second opening 16b is formed in the second interlayer insulating film 18.
, P-side pad opening 19 and n-side pad opening 20
And a via hole 21 are formed.

Finally, as shown in FIG. 26, the p-layer is formed on the entire surface of the semiconductor substrate 2 after the patterning of the second interlayer insulating film 18 is completed.
A conductive film to be the side matrix wiring 4 is formed, and the conductive film is patterned by a lift-off method to form the p-side matrix wiring 4. Thereafter, a sintering process is performed. As described above, the LED array 61 shown in FIG. 22 is manufactured.

As described above, according to the fifth embodiment, the p-side electrode 14, the n-side contact electrode 55a, and the n-side pad electrode 55b are formed by using the same conductive film and the same process material, so that the first electrode is formed. Further, the manufacturing process can be further simplified as compared with the fourth embodiment, so that a low cost can be realized. In addition, by forming the p-side electrode 14, the n-side contact electrode 55a, and the n-side pad electrode 55b in the same step, it is possible to further reduce variation in characteristics between substrates (wafers).

Sixth Embodiment FIG. 27 is a top view showing the structure of an LED array 71 according to a sixth embodiment of the present invention. 27, the same components as those in FIGS. 1, 14, 15, 21, and 22 are denoted by the same reference numerals. The LED array 71 includes a plurality of LEDs 80 arranged in a row on the semiconductor
{I] corresponding LED array. LED array 7
1 connects the p-side electrode 14 and the n-side electrode 55 of the LED 80,
This is a structure formed on the same surface of the semiconductor substrate 2. This 60
In the LED array 71 corresponding to 0 [DΡI], 1200 [D] like the LED array 1 of the first embodiment is used.
Unlike the LED array of [I], since all the p-side electrodes have the p-side pad electrodes, there is no need to form an isolation groove, a p-side matrix wiring, and a second interlayer insulating film. The LED array 71 is an LED array in which the first conductivity type is n-type and the second conductivity type is p-type.

The n-type semiconductor substrate 2a of the semiconductor substrate 2 has
Q (Q is a positive integer) LEDs 10 are formed in one line. In FIG. 27, Q = 9. n-type semiconductor substrate 2a
The LED array 1 of the first embodiment shown in FIG.
Similarly, Q p-type semiconductor layers 13 are formed in one line. The first opening 16 is formed on the n-type semiconductor substrate 2a.
A first interlayer insulating film 12 having a and an n-side opening 17 is formed. On the first interlayer insulating film 12, Q p-side electrodes 14, an n-side contact electrode 55a, and an n-side pad electrode 55b are formed. The p-side electrode 14 is
The opening 16a is connected to the p-type semiconductor layer 13. The n-side contact electrode 55a is formed so as to cover the entire surface of the n-side opening 17, and is ohmically connected to the n-type semiconductor substrate 2a at the n-side opening 17. Also, an n-side pad electrode 55b connected to the n-side contact electrode 55a
Are formed on the first interlayer insulating film 12. The n-side contact electrode 55a and the n-side pad electrode 55b constitute an n-side electrode 55 having a single-layer structure.

The LEDs 80 are an n-type semiconductor substrate 2 a common to the Q LEDs 80, a p-type semiconductor layer 13 individually formed on the n-type semiconductor substrate 2 a, and individually formed on the p-type semiconductor layer 13. It is composed of a p-type electrode 14 and an n-type electrode 55 commonly formed for the Q LEDs 80. When a voltage is applied between the p-type electrode 14 and the n-type electrode 55, a light-emitting phenomenon occurs at the junction surface between the p-type semiconductor layer 13 and the n-type semiconductor substrate 2a. Radiated to the outside.

Conventionally, in an LED array of 600 [DPI] or less, an n-type semiconductor substrate having no high-resistance semiconductor substrate is used, and a p-type semiconductor layer and a p-side electrode are formed on the surface of the n-type semiconductor substrate. Polish the back of the mold semiconductor substrate,
An n-side electrode was formed on the entire back surface using a conductive film different from the p-type electrode. However, in the LED array 71, the p-side electrode 14 and the n-side electrode 55 made of the same conductive film material are simultaneously placed on the same surface of the semiconductor
It is formed by a conductive film forming step and a patterning step thereof. Accordingly, a step of polishing the back surface of the semiconductor substrate and a step of forming a conductive film to be an n-side electrode on the back surface of the semiconductor substrate can be omitted. As the conductive film serving as the p-side electrode 14 and the n-side electrode 55, a conductive film that can make ohmic contact with both the p-type semiconductor layer 13 and the n-type semiconductor substrate 2a, for example, an Au film or an Au alloy film is used. As the above-mentioned Au alloy film, Ti / Pt / A
u film, or @ uGeNi / Au film, or @ uGe /
Ni / Au film and the like.

As described above, according to the sixth embodiment, the n-side electrode conventionally formed on the back surface of the n-type semiconductor substrate is formed on the same surface as the p-side electrode and the p-type semiconductor layer.
By forming the n-side electrode 55 and the n-side electrode 55 in the same step using the same conductive film, the manufacturing process can be simplified, and thus the cost can be reduced.

In the embodiment of the present invention, a homojunction structure composed of the same crystal has been described as the pn junction structure of the LED array. However, the present invention is also applicable to a heterojunction structure in which different materials are bonded. it can.

[0069]

As described above, according to the LED array and the method of manufacturing the same of the present invention, the n-side contact electrode and the p-side electrode, or the n-side contact electrode and the n-side pad electrode, or the n-side contact electrode and the n-side electrode Side pad electrode and p
By forming the side electrodes with the same conductive film in the same step, there is an effect that the manufacturing process can be simplified, and thus the cost can be reduced. Also,
There is an effect that characteristic variations between substrates (wafers) can be reduced.

[Brief description of the drawings]

FIG. 1 is a top view illustrating a structure of an LED array according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 1).

FIG. 3 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 2).

FIG. 4 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 3).

FIG. 5 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 4).

FIG. 6 is a view illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 5).

FIG. 7 is a view illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 6).

FIG. 8 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 7).

FIG. 9 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 8).

FIG. 10 is a diagram illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 9).

FIG. 11 is a view illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 10).

FIG. 12 is a view illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 11).

FIG. 13 is a view illustrating an example of a manufacturing process of the LED array according to the first embodiment of the present invention (part 12).

FIG. 14 is a top view illustrating a structure of an LED array according to a second embodiment of the present invention.

FIG. 15 is a top view illustrating a structure of an LED array according to a third embodiment of the present invention.

FIG. 16 is a diagram illustrating an example of a manufacturing process of the LED array according to the third embodiment of the present invention (part 1).

FIG. 17 is a view illustrating an example of a manufacturing process of the LED array according to the third embodiment of the present invention (part 2).

FIG. 18 is a view illustrating an example of a manufacturing process of the LED array according to the third embodiment of the present invention (part 3).

FIG. 19 is a diagram illustrating an example of a manufacturing process of the LED array according to the third embodiment of the present invention (part 4).

FIG. 20 is a view illustrating an example of a manufacturing process of the LED array according to the third embodiment of the present invention (part 5).

FIG. 21 is a top view illustrating a structure of an LED array according to a fourth embodiment of the present invention.

FIG. 22 is a top view illustrating a structure of an LED array according to a fifth embodiment of the present invention.

FIG. 23 is a diagram illustrating an example of a manufacturing process of the LED array according to the fifth embodiment of the present invention (part 1).

FIG. 24 is a diagram illustrating an example of a manufacturing process of the LED array according to the fifth embodiment of the present invention (part 2).

FIG. 25 is a view illustrating an example of a manufacturing process of the LED array according to the fifth embodiment of the present invention (part 3).

FIG. 26 is a view showing an example of the manufacturing process of the LED array according to the fifth embodiment of the present invention (part 4).

FIG. 27 is a top view illustrating a structure of an LED array according to a sixth embodiment of the present invention.

FIG. 28 is a view showing a structure of a conventional LED array corresponding to 600 [DPI] or less.

FIG. 29 is a diagram showing a structure of a conventional LED array corresponding to 1200 [DPI].

[Explanation of symbols]

1,31,41,51,61,71 LED array,
2a n-type semiconductor substrate, 13 p-type semiconductor layer, 1
4,54 p-side electrode, 15,55 n-side electrode, 15
a, 55a n-side contact electrode, 15b, 55b
n-side pad electrode.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takaatsu Shimizu 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (9)

[Claims] A first conductive type semiconductor layer formed on a first conductive type semiconductor substrate, and a first conductive side contact electrode connected to the semiconductor substrate on a surface of the semiconductor substrate on a side on which the semiconductor layer is formed. And a second conductive side electrode connected to the semiconductor layer, wherein the first conductive side contact electrode and the second conductive side electrode are made of the same conductive film material. . 2. A first conductive side contact electrode connected to the semiconductor substrate, wherein a second conductive type semiconductor layer is formed on a first conductive type semiconductor substrate, and a semiconductor substrate is formed on a surface of the semiconductor substrate on which the semiconductor layer is formed. And an LED array having a first conductive side electrode formed of a first conductive side pad electrode connected to the first conductive side contact electrode, wherein the first conductive side electrode is formed of the first conductive side contact electrode and the first conductive side contact electrode. An LED array having a single-layer structure in which a conductive-side pad electrode is integrally formed with the same conductive film. 3. A second conductive side electrode connected to the semiconductor layer is formed on a surface of the semiconductor substrate on the semiconductor layer forming side, and the first conductive side electrode and the second conductive side electrode are connected to each other. 3. The LE according to claim 2, wherein the same conductive film material is used.
D array. 4. The LE according to claim 1, wherein the conductive film is an Au film or an Au alloy film.
D array. 5. The LED array according to claim 4, wherein the Au alloy film is an alloy film containing Au, Ti, and Pt, or an alloy film containing Au, Ge, and Ni. 6. A first conductive side contact electrode connected to the semiconductor substrate, wherein a second conductive type semiconductor layer is formed on a first conductive type semiconductor substrate, and a semiconductor substrate is formed on the semiconductor substrate surface on the side where the semiconductor layer is formed. And a method of manufacturing an LED array in which a second conductive side electrode connected to the semiconductor layer is formed, wherein a conductive film serving as the first conductive side contact electrode and the second conductive side electrode is formed on a surface of the semiconductor substrate. Forming a first conductive contact electrode and a second conductive electrode at the same time by forming a film and patterning the conductive film. 7. A first conductive side contact electrode connected to the semiconductor substrate, wherein a second conductive type semiconductor layer is formed on the first conductive type semiconductor substrate, and the semiconductor substrate is provided on the surface of the semiconductor substrate on the side where the semiconductor layer is formed. And a method of manufacturing an LED array in which a first conductive side electrode formed of a first conductive side pad electrode connected to the first conductive side contact electrode is formed. A conductive film serving as the first conductive side electrode on a surface of the semiconductor substrate Forming a first layer on the first conductive side in a single-layer structure by patterning the conductive film. 8. A step of patterning the conductive film, comprising: forming a conductive film serving as the first conductive side electrode and a second conductive side electrode connected to the semiconductor layer on a surface of the semiconductor substrate; 8. The method according to claim 7, wherein the first conductive side electrode is formed in a single-layer structure by patterning a film, and the first conductive side electrode and the second conductive side electrode are simultaneously formed. A method for manufacturing the LED array described in the above. 9. The LE according to claim 6, wherein the conductive film is an Au film or an Au alloy film.
Method for manufacturing D array.