JPH10144955A - Light-emitting element array and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain inexpensive light-emitting array of an electronic photo print head with improved characteristics. SOLUTION: A light-emitting element array is made of a substrate with a plurality of n-type blocks 19, consisting of n-type compound semiconductor layer 12 having a plurality of pn-junctions. Then, a common electrode 174 that is connected to an n-type compound semiconductor layer 12 of an array-shaped light-emitting element constituted of each pn-junction in each n-type block 19 and an individual electrode 173 that is connected to a plurality of diffusion regions 16 formed on the surface of the n-type semiconductor layer, are provided on the same surface of the n-type block. Also, two pads, namely a common electrode pad 171 that is connected to a common electrode through a wiring and line wiring pad 172 connected to separate electrodes through a wiring are provided on the same surfaces of the n-type blocks respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting element array and a method of manufacturing the same, and more particularly to a light emitting element (also referred to as an LED) array used as a light source of an electrophotographic print head and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, regarding an LED array used as a light source of a print head for electrophotography, see, for example, "Trikeps (WS-6), Design of Optical Printer", supervised by Yoshisuke Takeda, October 31, 1985. JP, issued by Trikeps Corporation.

FIG. 12 is an explanatory view of a principal part schematically showing an outline of an LED array structure described on page 126 of the above-mentioned document. The lower view in FIG. 12 is a top perspective view, and the upper view is an MM cross-sectional view. In general, a substrate used for an LED array is conventionally made of a group III-V compound semiconductor, and for example, a GaAs _1-x P _x epitaxial substrate has been used.

[0004] Then, n-type Ga
A p-type diffusion layer 2 is formed by selectively diffusing Zn (zinc) as a p-type impurity into an As _1-x P _x substrate 1 to form a pn junction which becomes an emitter region 3 of an LED. An array of a plurality of the pn junctions (light emitting elements) is formed as an LED array. During the formation process in this case, Zn is replaced with n-type GaAs.
In order to selectively diffuse into the s _1-x P _x substrate 1, a diffusion mask (insulating film such as SiN) 6 having an opening in an area to be diffused on the semiconductor substrate is generally formed.

A P electrode (also used as an electrode pad) 4 made of a conductor such as a metal is formed so as to expose the entire surface of the semiconductor substrate having the diffusion openings and cover a part of the area of each opening. I have. Then, an N electrode 5 is generally formed on the entire back surface of the substrate. As described above, the conventional LED array has a structure in which one P electrode 4 is provided in each p-type region (p-type diffusion layer 2) as shown in FIG. By applying a voltage between the P electrode 4 and the N electrode 5 to flow a forward current, light unique to the element is emitted from the emitter region 3.

[0006]

SUMMARY OF THE INVENTION As described above, the conventional L
The ED array and its manufacturing method have problems to be solved as described in the following 1) to 3). 1) Since the electrode pad and the LED are in a 1: 1 ratio, when a high-density array such as 1200 DPI (DPI: dot per inch) is used, the ratio (density) occupied by the electrode pad increases, and the wiring pattern It becomes difficult to form. 2) The wiring density becomes very high, and connection with the IC becomes difficult. 3) Therefore, the mounting cost becomes very high.

[0007]

The light-emitting element array according to the present invention comprises a substrate having a plurality of n-type blocks constituted by an n-type semiconductor layer having a plurality of pn junctions. A light-emitting element array configured as an element, wherein an n-type common electrode connected to an n-type semiconductor layer and n
P-type individual electrodes connected to a plurality of p-type diffusion regions formed on the surface of the type semiconductor layer are provided on the same surface of the n-type block;
Two pads, a common electrode pad connected to the n-type common electrode via the wiring and a line wiring pad connected to the same order p-type individual electrode in the n-type block via the wiring, are provided on the same surface of each n-type block. Each is assigned to one. Here, the n-type blocks of the plurality of light-emitting element arrays are obtained by dividing the n-type semiconductor layer on the same substrate by separating grooves.
It is good that it is formed. Further, it is desirable that two pads, a common electrode pad and a line wiring pad, are arranged on the same side with respect to the pn junction, or the common electrode pad is arranged on the opposite side of the pn junction with the line wiring. May be provided.

Further, in the above-described light emitting element, the line wiring connected to the same-order p-type individual electrode in the n-type block through the wiring has a structure in which a plurality of line wiring pads are provided for one line wiring. Alternatively, the line wiring connected to the same order p-type individual electrode in the n-type block through the wiring may have a structure in which the matrix wiring in the chip is divided into a plurality of sections. There may be.

In the method of manufacturing a light emitting element array according to the present invention, at least the following 1)
-5) is performed. 1) Before the separation groove forming step, a p-type diffusion region forming step and an electrode / wiring pattern forming step are performed. 2) A p-type individual electrode is formed and sintered before an n-type common electrode is formed by contact formation. 3) Formation of p-type individual electrode and Au alloy-Al after sintering
A common electrode wiring / pad having a system wiring contact is formed. 4) An antioxidant film is formed on the first-layer Al-based wiring, and a contact with the second-layer Al-based wiring is formed. 5) The contact of the common electrode is an Au alloy electrode, and the wiring is formed on the insulating film as an Al-based wiring.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is an explanatory view schematically showing a main part of an LED array according to a first embodiment of the present invention. FIG.
, A top view (upper view) of the LED array, an AA cross-sectional view (middle left view) of the top view, a BB cross-sectional view (lower left view) of the top view, and a CC cross-sectional view (right view) of the top view (Middle figure) is shown. In addition, like the drawings in each of the following embodiments,
FIG. 1 schematically shows the present invention as long as the present invention can be understood, and does not limit the present invention such as dimensions.

The substrate used has a structure in which an n-type compound semiconductor is epitaxially grown on a semi-insulating compound semiconductor. The semi-insulating substrate 11 is, for example, a GaAs wafer of a III-V compound semiconductor, and the n-type compound semiconductor layer 12 is an Al _x Ga _{1 -x} As epitaxial growth layer. The composition X can be determined according to a desired emission wavelength.

The n-type compound semiconductor layer 12 is divided into a plurality of n-type blocks 19 by separation grooves 18. In each n-type block 19, a plurality of pn junctions are formed by a plurality of p-type diffusion regions 16 formed by selectively diffusing Zn and the n-type compound semiconductor layer 12. On the diffusion region 16 of the pn junction, a diffusion opening (light emitting portion) 161 penetrating the interlayer insulating films 13 and 14 and the insulating film 15 is formed as seen in the AA cross-sectional view. That is, light emitted from the pn junction is radiated outside from the opening.

Each n-type block 19 is provided with a common electrode 174 as an n-side electrode by an ohmic electrode near the pn junction, and an individual electrode 173 as a p-side electrode by an ohmic contact electrode at each pn junction. The individual electrode 173 is insulated from the n-type compound semiconductor layer 12 by the interlayer insulating film 13 and the interlayer insulating film 14. The common electrode 174 is formed of, for example, an Au alloy, and
73 is formed of Al or a metal containing Al.

The common electrode 174 is connected to the individual electrode 1
73, the common electrode pad 171 is formed by wiring insulated from the substrate by the interlayer insulating film 13 and the interlayer insulating film 14.
Is connected to The individual electrodes 173 provided at the respective pn junctions are connected to the same-ranked electrodes in the respective n-type blocks 19 by one wiring. Here, the common electrode (n-side electrode) 174 and the individual electrode (p-side electrode) 173
Are referred to as a first-layer wiring 175, and wirings connected to the same-ranking electrodes in each n-type block 19 are referred to as a second-layer wiring 176.

Since the second layer wiring 176 straddles the separation groove 18, the separation groove 18 is flattened by the insulating film 15.
In the present invention, the second layer wiring 176 is
Is used as an interlayer insulating film. In this case, as apparent from the function of the interlayer insulating film, the interlayer insulating film between the first-layer wiring 175 and the second-layer wiring 176 is provided with the flattening insulating film 15 and another insulating film. May be provided in another layer.

The number of lines of the second layer wiring 176 is one n
The number of pn junctions present in the mold block 19, ie 1
The number is the same as the number of the individual electrodes 173 in one n-type block 19. Each common electrode 174 and each line of the second layer wiring 176 have a common electrode pad 171 and a line wiring pad 17 for connection to a driving IC (not shown).
2 are provided. These electrode pads are all provided on the same side with respect to the pn junction array. By providing them on the same side in this manner, the drive IC can be installed on the same side with respect to the pn junction array chip, so that the width of the substrate can be reduced and the number of drive ICs can be reduced.

The above-mentioned electrode pads are arranged so as not to cover the separation groove 18. The number and arrangement of the electrode pads are determined by the number and pitch of pn junctions provided in each n-type block 19. . The number of the pn junctions and the width of the pitch determine whether the electrode pads can be arranged in a straight line or whether the electrode pads are arranged in a plurality of stages. The pitch between the common electrode pad 171 and the line wiring pad 172 can be arbitrarily determined. In the present embodiment, the common electrode pad 1
The pitch of 71 and the pitch of the line wiring pad 172 are respectively equal pitches.

In the above-described first embodiment, the description has been given of the case where the substrate in which the n-type compound semiconductor is epitaxially grown on the semi-insulating compound semiconductor is used. However, as in the substrate shown in FIG. For example, a substrate having a structure in which an n-type semiconductor layer 21 is formed on a top surface of a substrate 23 via a semi-insulating semiconductor layer 22 which is a buffer layer having a certain structure may be used.

As described above, according to the first embodiment,
N divided into a plurality of blocks having a plurality of pn junctions
Type semiconductor layer is provided, an n-side common electrode is provided in each n-type block, and a line wiring for connecting p-side individual electrodes of the same rank in each n-type block is provided. Since one electrode wiring is provided for each n-side common electrode and each line wiring on the same side, the following effects 1) to 4) are obtained. 1) A light emitting element array that can be dynamically driven is obtained. 2) The wiring connection density to the drive IC can be reduced. 3) It is also possible to adopt a structure in which the electrode pads are arranged in a line, and the chip size can be reduced even in an ultra-high-density array. 4) Since the driving ICs can be arranged on one side of the pn junction array chip, the size of the substrate for mounting the pn junction array chip and the driving IC can be reduced. In this case, the number of drive ICs can be reduced.

[Second Embodiment] FIG. 3 is an explanatory view schematically showing a main part of an LED array according to a second embodiment of the present invention. In the present embodiment, in the first embodiment, for example, a plurality of line wiring pads 172-1a,.
, 172-8b and the like.

When the number of pn junctions (light emitting element regions) included in one chip is large, the chip length becomes long. Therefore, the length of the line wiring connecting the pn junctions of the same rank in each n-type block 19 becomes longer. When the chip width is reduced, space can be saved by reducing the line wiring width. Here, an increase in the length of the wiring and a decrease in the width of the wiring both mean that the electrical resistance of the wiring increases. In particular, when the resistance of the line wiring is high, the voltage drop generated according to the distance from the line electrode pad cannot be ignored, and the light emission intensity of each dot may vary.

In the present embodiment, in order to cope with such a situation, by providing a plurality of line electrode pads in accordance with the resistance of one line wiring, the light emission intensity of each light emitting element becomes uniform. It is what it was. The configuration of FIG. 3 shows a structure in which an electrode pad connected to the same line wiring is provided every eight blocks of a plurality of divided n-type blocks. As is clear from the purpose of the present embodiment, the number of electrode pads provided on the same line can be arbitrarily set by design.

As described above, according to the second embodiment,
Since a plurality of line wiring pads are provided for one line wiring, the following effects 1) to 3) can be obtained. 1) Even when the line wiring length becomes longer, the wiring width becomes narrower, or the wiring thickness becomes thinner, the resistance of the line wiring becomes higher, so that the effect of the voltage drop can be reduced and the variation in the light emission intensity can be reduced. Dynamic driving of the light emitting element becomes possible. 2) The design margin of the line wiring can be increased. 3) The number of dots per chip can be increased.

[Third Embodiment] FIG. 4 is a schematic explanatory view of a principal part of a third embodiment of the LED array according to the present invention. The feature of this embodiment is that one line wiring is
The point is that the structure is divided into a plurality of lines at the separation part 41 of the line wiring. In this case, one or a plurality of electrode pads are provided for each divided line wiring. In FIG. 4, one line wiring pad 172 is provided for each divided line wiring.

The substrate structure shown in FIG. 4, that is, the structure shown by the cross section of the element is the same as that shown in FIG. 1 in the first embodiment. Since the configuration and structure of FIG. 1 have been described in the description, they are omitted in this section. With the light emitting element structure according to the present embodiment as described above, the light emitting element groups in each section obtained by dividing the line wiring in the chip can be independently driven dynamically. Therefore, it is possible to increase the driving speed of one LED line.

In the third embodiment, the description has been given of the case where a substrate in which an n-type compound semiconductor is epitaxially grown on a semi-insulating compound semiconductor is used. However, as in the substrate shown in FIG. For example, a substrate having a structure in which an n-type semiconductor layer 21 is formed on the upper surface of a buffer layer of some structure, for example, a semi-insulating semiconductor layer 22 via a semi-insulating semiconductor layer 22 may be used on the substrate 23, but this is also the first embodiment. As described in the above.

As described above, according to the third embodiment,
Since the matrix wiring in the chip is divided into a plurality of sections, the following effects 1) to 3) can be obtained. 1) Dynamic driving of the light emitting element can be performed independently for each of a plurality of sections in the chip. 2) Since a plurality of sections in the chip can be simultaneously driven dynamically by the light-emitting elements, high-speed driving is possible. 3) Since the matrix wiring is divided into a plurality of sections, the number of line wirings can be reduced depending on the number of sections to be divided, and the chip width of the light emitting element array can be reduced.

[Fourth Embodiment] In this embodiment, a method of manufacturing an LED array having the structure described in the first to third embodiments will be described. FIG. 5, FIG. 6, FIG. 7, and FIG. 8 are a series of main part process explanatory views showing one embodiment of a method of manufacturing an LED array according to the present invention. In addition, (a) to (f) added throughout the drawings are a series of process sequential diagrams. Here, a manufacturing method using an array substrate having a structure in which an n-type Al _x Ga _1-x As epi (abbreviation for epitaxial) layer 53 of an n-type compound semiconductor layer is provided on a semi-insulating GaAs substrate 54 is described. , Will be described in the order shown in FIG.

FIG. 5A: Diffusion opening 51 (diffusion opening 511 in the left plan view) selectively on the array substrate.
Is formed. The thin film material is
For example, AlN (aluminum nitride: insulator) is used. FIG. 5B: A diffusion source film 56 containing Zn (for example, Zn
After the formation of the doped silica film, the annealing cap film 55 is formed. In this state, the substrate is put into an annealing furnace, and diffusion annealing is performed at 650 ° C. for one hour to form a diffusion region 58 forming a pn junction. Under these conditions, for example, a junction having a diffusion depth of 1 to 1.5 μm can be formed. The diffusion annealing conditions are appropriately adjusted depending on the desired diffusion depth.

FIG. 6C: After the pn junction is selectively formed as described above, the diffusion source film 56 is removed and the n-side electrode (n
The substrate surface in the side ohmic contact) formation region is exposed, and a common electrode formation opening 521 for contact formation is formed. In this step, the diffusion mask thin film 52 (AlN) on the separation groove forming region 522 is also removed.

FIG. 6D: SiN having openings in the light emitting portion and the n-type electrode formation region in order to enhance interlayer insulation.
A film 60 is formed on the diffusion mask thin film 52. SiN film 6
After the formation of 0, an opening is formed at the opening of the diffusion mask thin film 52 by standard photolithography and dry etching. At this time, the Si
The N film 60 is also removed. Further, a pattern of an Al-based p-side electrode 59 having a contact in the light emitting opening is formed.
In each of the above-described pattern forming steps, a standard photolithography technique and a SiN pattern are formed by a dry etching technique, and an Al wiring is formed by a wet etching technique. It is also possible to use a lift-off technique by forming an Al-based wiring. Then, after forming the pattern of the Al-based p-side electrode 59, the whole is sintered to obtain a good ohmic contact.

FIG. 7E: Next, an Au alloy pattern is formed in the common electrode forming opening 521 by a lift-off method, and a common electrode pattern 593 is formed. After forming the common electrode pattern 593, the whole is sintered in order to obtain a good ohmic contact. FIG. 8F: Further, a common electrode pattern 593, a common electrode pad 592, and a line wiring pad 591 are formed. The wiring is made of, for example, an Al-based metal. By wiring with an Al-based metal, good adhesion between the insulating film and the wiring can be maintained. The Al-based metal wiring is coated with, for example, Ni (nickel) to prevent oxidation of the wiring surface.

Next, the step of separating the n-type block by the separation groove will be described with reference to FIGS. 9A, 9B and 10C. In each figure, LED
The structure of the array is not shown, and only the method of separating n-type blocks is shown.

FIG. 9A: First, a substrate comprising an n-type compound semiconductor epilayer 65 formed on a semi-insulating substrate 61 is used, and a first insulating film 63 and a second insulating film are further formed thereon. A film 64 is provided, and first, an insulating film opening 63a is formed in the first insulating film 63 and the second insulating film 64 in the isolation groove forming region. Up to this point, it is formed by the manufacturing process described with reference to FIG. That is, the opening of the first insulating film 63 is removed in the step of FIG. 6C, and the second insulating film is removed in the step of FIG. Then, the insulating film opening 63a
A negative resist pattern 62 having an opening 62a having a smaller width is formed. This is to prevent an eave from remaining on the separation groove after the separation groove is formed in a later step.
Next, the n-type epi layer 65 and the semi-insulating substrate 61 are mixed with phosphoric acid / hydrogen peroxide (phosphoric acid + hydrogen peroxide + water) through the opening 62a.
Is partially etched to form a separation groove 611.

FIG. 9B: Next, after the negative resist pattern 62 is removed, the separation groove 611 is filled with a polyimide resin and flattened, whereby the flattening film 66 is formed.
To form FIG. 10C: Further, after forming a contact hole 69 at a place where the first-layer wiring 67 and the second-layer wiring 68 are in contact and at a pad formation position, the Al wiring pattern 7 is formed.
2,75 are formed. That is, an Al wiring pattern 72 connecting the common electrode pad 70 and the common electrode 71 and an Al wiring pattern 75 connecting the line wiring pad 73 and the diffusion region 74 are formed by applying a standard photolithography technique and a wet etching technique. I do.

As described above, according to the fourth embodiment,
Since the LED array is manufactured by the above method, the following effects 1) to 5) can be obtained. 1) Since the diffusion step and the electrode / wiring pattern forming step are performed before the formation of the separation groove, the diffusion and the formation of the electrode / wiring pattern are not affected by the separation groove. Further, the formation of the planarizing film is not affected by the p-side contact formation or the sintering process. 2) Since the p-type contact (p-side electrode) is formed and sintered before the formation of the n-type contact (n-side electrode), the n-type contact is not affected by the sinter.

3) Since the common electrode wiring and the pad are formed after the formation and sintering of the p-type contact, the Au alloy-A
The contact of the l-system wiring is not affected by the sinter. 4) Since an oxidation prevention film of Ni or the like is formed on the first-layer Al-based wiring film, the contact resistance with the second-layer Al-based wiring can be kept low. 5) Since the contact of the common electrode is an Au alloy electrode and the upper surface of the insulating film is an Al-based wiring, good adhesion between the insulating film and the wiring can be maintained.

[Fifth Embodiment] FIG. 11 is a schematic structural explanatory view showing another mode of an LED array according to a fifth embodiment of the present invention. FIG. 11 is a configuration explanatory diagram corresponding to the explanatory diagram of FIG. 10C described in the fourth embodiment.

In FIG. 11, a common electrode pad 80 of an n-side common electrode is formed and arranged on the opposite side of a pn junction array 81 from a line wiring pad 82. Here, the configuration of the pn junction array 81 is the same as that of FIG. 10C except for the common wiring pattern 72a.
In this configuration, the common wiring pattern 72a connecting the common electrode pad 80 and the common electrode 71 is formed by a simple first-layer wiring in one direction.

As described above, according to the fifth embodiment,
Although the chip width shown in the vertical direction in the figure increases, a pn junction array with a high dot density has an advantage that a larger wiring space can be secured. That is, since the common electrode pad is provided on the opposite side of the pn junction array from the line wiring pad, there is an effect that a wiring space in the horizontal direction in the drawing can be particularly secured.

In the above-described embodiment, the n-type epitaxial layer is separated by the separation groove. However, the separation band may be formed by diffusion of the p-type impurity. In this case, the p-type impurity may be selectively diffused into the isolation region before the step of selectively diffusing the light emitting region. The epitaxial layer is made of Al
It is clear that the present invention is applicable to other than GaAs. Further, in a substrate in which an AlGaAs layer is grown on a GaAs substrate, a buffer layer such as a GaAs epitaxial layer may be provided between the AlGaAs layer and the GaAs substrate for the purpose of improving the crystallinity.

[0042]

As described above, according to the present invention, a plurality of p
An n-type semiconductor layer having an n-junction is composed of a substrate having a plurality of n-type blocks and connected to the n-type semiconductor layer.
A common electrode connected to the n-type common electrode and a plurality of p-type diffusion regions formed on the surface of the n-type semiconductor layer on the same surface of the n-type block; Since two pads of the pad and the line wiring pad connected to the same-order p-type individual electrode in the n-type block via the wiring are arranged on the same surface of each n-type block, one each, 1) Dynamic drive A light emitting element array capable of performing the above is obtained. 2) The wiring connection density to the drive IC can be reduced. 3) It is also possible to adopt a structure in which the electrode pads are arranged in a line, and the chip size can be reduced even in an ultra-high-density array. 4) Since the driving ICs can be arranged on one side of the pn junction array chip, the size of the substrate for mounting the pn junction array chip and the driving IC can be reduced. Excellent effects such as are obtained.

[Brief description of the drawings]

FIG. 1 is a schematic main part explanatory view showing a first embodiment of an LED array according to the present invention.

FIG. 2 is an explanatory diagram showing an example of another substrate that can be used in the present invention.

FIG. 3 is a schematic diagram illustrating a main part of an LED array according to a second embodiment of the present invention.

FIG. 4 is an explanatory view schematically showing a main part of an LED array according to a third embodiment of the present invention.

FIG. 5 is an explanatory diagram of a series of main steps showing one embodiment of a method of manufacturing an LED array as a fourth embodiment of the present invention.

FIG. 6 is an explanatory diagram of a series of main steps showing an embodiment of a method of manufacturing an LED array according to a fourth embodiment of the present invention.

FIG. 7 is an explanatory diagram of a series of main steps showing one embodiment of a method of manufacturing an LED array as a fourth embodiment of the present invention.

FIG. 8 is an explanatory diagram of a series of main steps showing one embodiment of a method of manufacturing an LED array as a fourth embodiment of the present invention.

FIG. 9 is a process explanatory view showing a process of separating an n-type block by a separation groove according to the present invention.

FIG. 10 is a process explanatory view showing a process of separating an n-type block by a separation groove according to the present invention.

FIG. 11 is a schematic configuration explanatory view showing another mode of the LED array according to the fifth embodiment of the present invention.

FIG. 12 is an explanatory diagram of a main part schematically showing an LED array structure described in a document.

[Explanation of symbols]

Reference Signs List 1 n-type GaAs _1-x P _x substrate 2 p-type diffusion layer 3 emitter region 4 P electrode 5 N electrode 6 diffusion mask 11, 61 semi-insulating substrate 12 n-type compound semiconductor layer 13, 14 interlayer insulating film 15 insulating film 16, 58, 74 Diffusion region 17, 173 Individual electrode 18 Separation groove 19 N-type block 161 Diffusion opening (light emitting portion) 171 Common electrode pad 172 Line wiring pad 174 Common electrode 175, 67 First layer wiring 176, 68 Two layers Eye wiring 21 n-type semiconductor layer 22 semi-insulating semiconductor layer 23 Si substrate 41 Line wiring separation point 51,511 Diffusion opening 52 Diffusion mask thin film 53 n-type Al _x Ga _{1 -x} As epi layer 54 GaAs substrate 55 Annealed cap film 56 Diffusion source film 59 p-side electrode 60 SiN film 521 Common electrode formation opening 522 Separation groove formation planned region 591 In wiring pad 592, 70 Common electrode pad 593 Common electrode pattern 61 Semi-insulating substrate 62 Negative resist pattern 62a Opening 63 First insulating film 63a Insulating film opening 64 Second insulating film 65 n-type epilayer 66 Flattening Film 69 contact hole 611 separation groove 70 common electrode pad 71 common electrode 72,75 Al wiring pattern 72a common wiring pattern 73,82 line wiring pad 81 pn junction array

Claims (11)

[Claims] 1. A light-emitting element array comprising a substrate having a plurality of n-type blocks formed by an n-type semiconductor layer having a plurality of pn junctions, wherein each of the pn junctions is configured as an array of light-emitting elements, an n-type common electrode connected to the n-type semiconductor layer and p-type individual electrodes connected to a plurality of p-type diffusion regions formed on the surface of the n-type semiconductor layer are provided on the same surface of the n-type block; Two pads, a common electrode pad connected to a common electrode via a wiring and a line wiring pad connected to the same p-type individual electrode in the n-type block via a wiring, are connected to the same surface of each of the n-type blocks. A light emitting element array, wherein one light emitting element array is provided for each light emitting element. 2. The light-emitting element array according to claim 1, wherein the plurality of n-type blocks are formed by dividing and forming an n-type semiconductor layer on the same substrate by a separation groove. 3. The light emitting element array according to claim 1, wherein two pads, a common electrode pad and a line wiring pad, are arranged on the same side of the pn junction. 4. The light emitting element array according to claim 1, wherein the common electrode pad is disposed on a side opposite to the line wiring with respect to the pn junction. 5. A line wiring connected to a p-type individual electrode of the same rank in an n-type block via a wiring, wherein a plurality of line wiring pads are provided for one line wiring. The light-emitting element array according to claim 1. 6. A line wiring connected to a same-order p-type individual electrode in an n-type block via a wiring has a structure in which a matrix wiring in a chip is divided into a plurality of sections. 2. The light emitting element array according to 1. 7. A method for manufacturing a light emitting element array for forming a light emitting element array according to claim 1, wherein a step of forming a p-type diffusion region and a step of forming an electrode / wiring pattern are performed before the step of forming an isolation groove. A method of manufacturing a light emitting element array. 8. A method for manufacturing a light emitting element array for forming a light emitting element array according to claim 1, wherein a p-type individual electrode is formed and sintered before forming an n-type common electrode by forming a contact. A method of manufacturing a light emitting element array. 9. The method for manufacturing a light emitting element array for forming a light emitting element array according to claim 1, wherein a common electrode wiring having a contact of an Au alloy-Al based wiring after forming and sintering a p-type individual electrode. -A method for manufacturing a light-emitting element array, comprising forming a pad. 10. A method for manufacturing a light emitting element array for forming a light emitting element array according to claim 1, wherein
An antioxidant film is formed on the Al wiring of the second layer to form an Al
A method for manufacturing a light emitting element array, comprising forming a contact with a system wiring. 11. A method of manufacturing a light emitting element array for forming a light emitting element array according to claim 1, wherein the contact of the common electrode is an Au alloy electrode, and the contact on the insulating film is A.
A method for manufacturing a light emitting element array, wherein wiring is formed as l-system wiring.