KR101997104B1 - Micro array lighting emitting diode and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a micro array light emitting diode and a method of manufacturing the same, and more particularly, to a micro array light emitting diode for selectively emitting a plurality of unit light emitting units arranged in two dimensions and a method of manufacturing the same. The micro array light emitting diode according to an embodiment of the present invention includes a substrate; a plurality of unit semiconductor stack structures including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer stacked on the substrate and separated two-dimensionally; a p-type electrode provided on the p-type semiconductor layer; an n-type electrode provided on the n-type semiconductor layer exposed by a first via hole passing through the active layer and the p-type semiconductor layer; and an insulating film provided on the inner surface of the first via hole.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a micro-array light-

The present invention relates to a micro-array light-emitting diode and a method of manufacturing the same, and more particularly, to a micro-array light-emitting diode for selectively emitting a plurality of unit light-emitting units arranged two-dimensionally and a method of manufacturing the same.

A light emitting diode (LED) is a semiconductor device capable of generating light of various colors based on the recombination of electrons and holes at the junction of an n-type semiconductor and a p-type semiconductor when an electric current is applied, Demand continues to increase because it has many advantages, including power, good initial drive characteristics, high vibration resistance, and high tolerances for repetitive power interruptions.

In particular, the fabrication technology of light emitting diodes using III-V semiconductor materials has been expanded from the red light emitting diode using AlGaAs-GaAs material to the red and green light emitting diode using AlGaInP-InP. Recently, With the development of blue light emitting diodes using materials, it becomes possible to realize the total color, so that the demand is explosively increasing with the rapid growth of the portable terminal industry and the continuous high brightness and high output application products.

In addition, unlike conventional incandescent lamps and fluorescent lamps, light-emitting diodes have many advantages such as ultra-small size, low power consumption, high efficiency and eco-friendliness, and recently they have begun to be applied to medium and large-sized displays such as backlights for large LCD- , Automotive lighting as well as the general lighting market.

However, the light emitting diodes developed to date require further improvement in terms of light extraction efficiency, light output and cost, and in particular, in order to expand the application range of light emitting diodes to general illumination, improvement of light extraction efficiency is a top priority .

KR 10-2005-0088987 A

The present invention provides a microarray light emitting diode capable of minimizing a non-emission region of a unit semiconductor stacked structure and improving light extraction efficiency and a method of manufacturing the same.

A micro-array light-emitting diode according to an embodiment of the present invention includes a substrate; A plurality of unit semiconductor laminated structures including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer stacked on the substrate, the two or more unit semiconductor stacked structures being arranged in two dimensions; A p-type electrode provided on the p-type semiconductor layer; An n-type electrode provided on the n-type semiconductor layer exposed by a first via hole penetrating the active layer and the p-type semiconductor layer; And an insulating layer provided on an inner surface of the first via hole.

The n-type electrode may be formed by filling a second via hole passing through the insulating film with a conductive material.

The second via hole may extend into the n-type semiconductor layer.

The n-type electrode may be disposed at a central portion of the unit semiconductor laminated structure.

And an n-type auxiliary electrode extending from a top surface of the n-type electrode along the surface of the insulating film.

A first interlayer insulating layer provided on the p-type electrode; An n-type electrode pad electrically connected to the n-type electrode and provided on the first interlayer insulating layer; A second interlayer insulating layer provided on the n-type electrode pad; And a p-type electrode pad electrically connected to the p-type electrode and provided on the second interlayer insulating layer.

The n-type electrode and the n-type electrode pad are connected by an n-type plug formed by filling the first via hole with a conductive material, and the cross-sectional area of the lower end of the n-type plug is larger than the cross- have.

Wherein the n-type electrode pad extends on the first interlayer insulating layer to electrically connect n-type electrodes included in the plurality of unit semiconductor stacked structures to each other, and is connected to the n-type electrode pad, And an n-type common pad provided outside the semiconductor stacked structure.

The p-type electrode pad may be provided separately for each p-type electrode included in the unit semiconductor laminated structure.

The p-type electrode can reflect light emitted from the active layer.

The light emitting device according to an embodiment of the present invention includes any one of the above-described micro array light emitting diodes; And a circuit board on which a plurality of transistors are mounted, wherein an n-type electrode included in each of the plurality of unit semiconductor stacked structures is commonly connected to the power supply terminal, and the plurality of units The p-type electrodes included in the semiconductor stacked structure are individually connected to the plurality of transistors.

A method of fabricating a microarray light emitting diode according to an embodiment of the present invention includes the steps of: stacking an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a substrate and forming a unit semiconductor stacked structure arranged two-dimensionally; Forming a first via hole in the unit semiconductor stack structure to expose the n-type semiconductor layer; Forming an insulating film on a sidewall of the first via hole; Forming an n-type electrode on the exposed n-type semiconductor layer; And forming a p-type electrode on the p-type semiconductor layer.

The process of forming the insulating layer may include forming an insulating layer pattern on the inner surface of the first via hole; And forming a second via hole through the lower surface of the insulating film pattern. In the forming the n-type electrode, the second via hole may be filled with a conductive material.

The process of forming the second via hole may be such that the second via hole extends through the insulating film layer to a predetermined depth of the n-type semiconductor layer.

The forming of the second via hole may include forming the second via hole so as to have an average sectional area smaller than that of the first via hole.

The process of forming the second via hole may be performed by selectively irradiating a laser on the lower surface of the insulating film pattern.

Forming a first interlayer insulating layer on the p-type electrode; Forming an n-type electrode pad electrically connected to the n-type electrode on the first interlayer insulating layer; Forming a second interlayer insulating layer on the first interlayer insulating layer; And forming a p-type electrode pad electrically connected to the p-type electrode on the second interlayer insulating layer.

And forming an n-type common pad on the outside of the plurality of unit semiconductor stacked structures to be connected to the n-type electrode pad, wherein forming the n-type electrode pad comprises: The n-type electrode pad may be extended to electrically connect the n-type electrodes included in the n-type electrode.

The process of forming the p-type electrode pad may include forming a plurality of p-type electrode pads so that the p-type electrode pad is individually connected to each p-type electrode included in the unit semiconductor stacked structure.

A method of manufacturing a light emitting device according to an embodiment of the present invention includes the steps of: preparing a micro array light emitting diode manufactured by any one of the manufacturing methods described above; A circuit board on which a power terminal for applying power and a plurality of transistors are mounted; Connecting n-type electrodes included in each of the plurality of unit semiconductor laminated structures to the power supply terminal in common; And individually connecting the p-type electrodes included in the plurality of unit semiconductor stacked structures to the plurality of transistors, respectively.

According to the microarray light emitting diode and the method of manufacturing the same according to the embodiment of the present invention, an insulating film is formed on the inner surface of the first via hole passing through the active layer and the p-type semiconductor layer, Layer can be effectively insulated.

In addition, compared to the case where the n-type electrode is formed by filling the second via hole passing through the insulating film to form the n-type electrode, the n-type electrode is spaced apart from the first via hole so as to be disposed at the center of the first via hole, It is possible to minimize the non-emission area formed by the first via hole in the unit laminate structure and to maximize the light extraction efficiency.

In addition, an n-type electrode and a p-type electrode that are electrically connected to the n-type semiconductor layer and the p-type semiconductor layer, respectively, are provided for each of the plurality of unit semiconductor laminated structures, It is possible to electrically isolate each unit semiconductor stacked structure, thereby obtaining excellent electrical characteristics and uniform light emission through efficient current injection.

In addition, a plurality of n-type electrodes included in each of the plurality of unit semiconductor laminated structures may be electrically connected to each other by n-type electrode pads to apply a uniform voltage or current to the plurality of n-type electrodes, Or the heat generated by applying the current may be effectively released to the outside. In addition, a plurality of n-type electrodes are commonly connected to a power supply terminal, and a plurality of p-type electrodes are individually connected to a plurality of transistors and driven to minimize the interval between the unit semiconductor stacked structures, The dark region can be minimized.

1 is a view showing a conventional micro-array light-emitting diode.
2 is a plan view showing a micro-array light-emitting diode according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the micro-array light-emitting diode shown in FIG. 2 cut in a direction AA 'according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view showing the micro-array light-emitting diode shown in FIG. 2 cut in a direction AA 'according to another embodiment of the present invention;
5 is a view showing a state in which a microarray light emitting diode and a circuit board are connected to each other according to an embodiment of the present invention.
6 is a view illustrating a method of manufacturing a micro-array light-emitting diode according to an embodiment of the present invention.
7 is a view illustrating another method of manufacturing a microarray light emitting diode according to an embodiment of the present invention.
8 is a view illustrating a method of manufacturing a microarray light emitting diode according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, Is provided to fully inform the user.

It is to be understood that when an element, such as a film, a region, or a substrate, is referred to as being "on" another element throughout the specification, the element may be directly "on" It is to be understood that there may be other components intervening in the system.

Further, relative terms such as "upper" or "lower" may be used herein to describe the relative relationship of certain elements to other elements as shown in the Figures. Relative terms are intended to include different orientations of the device in addition to those depicted in the Figures. Wherein like numerals refer to like elements.

1 is a view showing a conventional micro array light emitting diode.

A conventional microarray light emitting diode is manufactured by sequentially laminating an n-type semiconductor layer 31, an active layer 32 and a p-type semiconductor layer 33 on a substrate. The n-type semiconductor layer 31, the active layer 32, And the p-type semiconductor layer 33 are separated into a plurality of unit semiconductor stacked structures arranged two-dimensionally on the substrate 10. [ The p-type electrode 40 is disposed on the separated p-type semiconductor layer 33 and the n-type electrode 50 is disposed on the edge of the n-type semiconductor layer 31.

However, when the n-type electrode 50 is disposed at the edges as described above, the distance between the p-type electrode 40 and the n-type electrode 50, which are arranged on the p-type semiconductor layer 33, The difference in voltage or current to be applied to the unit semiconductor stacked structure is generated and uniform light emission is difficult. Further, since the n-type electrode 50 is formed at the edge, there is a problem that light is also emitted to an undesired unit light emitting unit.

On the other hand, in the microarray light emitting diode according to the embodiment of the present invention, an n-type electrode is formed in a via hole formed in a unit semiconductor stacked structure, and a p-type electrode is formed on the n-type electrode, It is possible to prevent unintended electric energy from intermingling to prevent crosstalk between neighboring unit semiconductor stacked structures and to apply uniform voltage or current regardless of the position of each unit semiconductor stacked structure to have excellent electrical characteristics, Light can be emitted. In addition, the cross-sectional area of the via hole formed in the center of the unit semiconductor stacked structure can be reduced to minimize the non-emission area and improve the light extraction efficiency.

Hereinafter, a micro-array light-emitting diode according to an embodiment of the present invention will be described in detail.

2 is a plan view showing a micro array light emitting diode according to an embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating the microarray light-emitting diode shown in FIG. 2 cut in the direction AA 'according to an embodiment of the present invention. FIG. 4 is a cross- Sectional view taken along the AA 'direction in accordance with another embodiment of the present invention.

2 to 4, a micro-array light-emitting diode according to an embodiment of the present invention includes a substrate 100; A plurality of unit semiconductor laminated structures 300 (hereinafter, referred to as " p-type ") semiconductor layers 310 and 320, ); A p-type electrode 400 provided on the p-type semiconductor layer 330; An n-type electrode 520 provided on the n-type semiconductor layer 310 exposed by a first via hole V1 passing through the active layer 320 and the p-type semiconductor layer 330; And an insulating layer 600 provided on a sidewall of the first via hole V1.

The substrate 100 may be formed using a transparent material including sapphire as a substrate suitable for growing a semiconductor single crystal. In addition to the sapphire, the substrate 100 may be formed of zinc oxide (ZnO), gallium nitride (GaN), silicon carbide (SiC), aluminum nitride (AlN), silicon (Si), silicon oxide .

On the substrate 100, a buffer layer 200 may be formed to improve the lattice matching between the substrate formed of a material such as sapphire and the semiconductor layer. The buffer layer 200 may be an undoped gallium nitride (GaN) layer to which no impurity is added.

The buffer layer 200 may be formed of at least one of InGaN, AlN, SiC, SiCN, and GaN, as well as GaN, to complement the characteristics of the substrate 100. That is, when the n-type semiconductor layer 310, which is an Epi layer, is directly grown on the substrate 100, it is difficult to manufacture a high-quality device by lattice mismatching, so that the single crystal growth of the n-type semiconductor layer 310 is facilitated To solve the problems associated with lattice mismatch between the substrate 100 and the semiconductor layers and to improve the lattice matching with the substrate 100 by forming an undoped semiconductor layer on the substrate 100 The buffer layer 200 may be further formed.

Further, the substrate 100 may further include a light extracting structure (not shown) provided on at least one surface or the other surface of the substrate 100 to increase the extraction amount of the emitted light. Here, the substrate 100 is a sapphire substrate having a patterned sapphire substrate (PSS). The sapphire substrate is a surface on which light is emitted from the sapphire substrate or a surface opposite to the sapphire substrate, and a plurality of It is possible to improve the light extraction efficiency by forming a fine pattern having a concavo-convex shape.

That is, when a pattern of a certain shape is formed on the surface of the sapphire substrate used for growth of the nitride-based semiconductor layer and GaN is epitaxially grown on the pattern, a light output enhancement effect can be obtained as compared with GaN grown on the flat substrate 100. Here, the light output of the nitride semiconductor layer grown on the patterned sapphire substrate (PSS) can be improved more than that of the light emitting diode grown on the flat substrate 100 due to the scattering of the emitted light due to the irregularity of the surface of the substrate 100. The light extracting structure may be disposed on one surface or the other surface of the sapphire substrate with a constant pattern and / or interval, and its size and arrangement form are not limited.

The unit semiconductor laminated structure 300 includes an n-type semiconductor layer 310, an active layer 320 and a p-type semiconductor layer 330 stacked on a substrate 100 and is formed on the substrate 100 two-dimensionally Are provided separately arranged. The unit semiconductor stack structure 300 includes an n-type semiconductor layer 310, an active layer 320, and a p-type semiconductor layer 330 stacked on a substrate 100, a stacked n-type semiconductor layer 310, At least the active layer 320 and the p-type semiconductor layer 330 of the active layer 320 and the p-type semiconductor layer 330 are etched to form an isolation part I filled with an insulating material, Can be separated and formed.

More specifically, the n-type semiconductor layer 310 may be formed on the substrate 100 and may be formed of a gallium nitride-based semiconductor material. The n-type semiconductor layer 310 may be a GaN layer doped with an n-type conductive impurity or a GaN / AlGaN layer. As the n-type conductivity impurity, Si, Ge, or Sn may be used. have.

The active layer 320 may be formed on the n-type semiconductor layer 310 and may include an InGaN / GaN layer having a multi-quantum well structure. The active layer 320 may emit light when a voltage is applied to the n-type semiconductor layer 310 and a current is supplied to the p-type semiconductor layer 330.

The p-type semiconductor layer 330 may be formed on the active layer 320 and may be made of a gallium nitride-based semiconductor material. The p-type semiconductor layer 330 may be a GaN layer doped with a p-type conductivity-type impurity or a GaN / AlGaN layer. As the p-type conductivity-type impurity, Mg, Zn, Be or the like may be used. have.

a part of the p-type semiconductor layer 330, the active layer 320 or the p-type semiconductor layer 330, the active layer 320 and the n-type semiconductor layer 310 may be removed by MESA etching, And a plurality of unit semiconductor stacked structures 300 arranged two-dimensionally on the substrate 100 can be formed by forming the isolation part I by filling insulating material. The number and arrangement structure of the unit semiconductor laminated structures 300 may be variously changed.

As described above, a general micro array light emitting diode forms a mesa region at an edge to form an n-type electrode 520. [ However, the distance between the p-type electrode 400 and the n-type electrode 520 arranged on the p-type semiconductor layer 330 due to the n-type electrode 520 formed on the edge is different for each unit semiconductor laminated structure 300 The difference in voltage or current applied to the unit semiconductor multilayer structure 300 is generated, and uniform light emission is difficult.

However, in the microarray light emitting diode according to the embodiment of the present invention, the n-type electrode 520 and the p-type electrode 400 are provided for each of the plurality of unit semiconductor laminated structures 300. Here, the n-type electrode 520 and the p-type electrode 400 may be arranged in the vertical direction, that is, the vertical direction in the unit semiconductor stacked structure 300, respectively. Therefore, since the unit semiconductor laminated structures 300 can be electrically separated while maintaining the same distance between the p-type electrode 400 and the n-type electrode 520 disposed in each unit semiconductor laminated structure 300, It is possible to obtain excellent electrical characteristics and uniform light emission through current injection.

The p-type electrode 400 is provided on the p-type semiconductor layer 330 and is formed of a conductive material such as Ag, Al, Au, Cr, Ir, Mg, Nd, Ni, Pd, Pt, Rh, . In addition, the p-type electrode 400 may be formed as a reflective electrode. Here, the reflective electrode may reflect light radiated to the upper portion of the substrate 100 from the light emitted from the active layer 320 toward the lower side of the substrate 100. In this case, the p-type electrode 400 may be formed of two or more of the metals having high reflectivity, or may be formed of a lamination structure of different metals, or may be formed of ITO, IZO, ZnO or In ₂ O ₃ film, As shown in FIG. In addition, the p-type electrode 400 may be formed to have an area corresponding to the top surface of the p-type semiconductor layer 330 so as to minimize the area of the p-type semiconductor layer 330 exposed. The reason for not exposing is to increase the amount of light reflected by the reflecting surface by increasing the reflection surface to improve the light extraction efficiency.

The n-type electrode 520 is provided on the n-type semiconductor layer 310 exposed by the first via hole V 1 passing through the active layer 320 and the p-type semiconductor layer 330. The n-type electrode 520 may be formed of a conductive material such as Ag, Al, Au, Cr, Ir, Mg, Nd, Ni, Pd, Pt, Rh, . Here, the n-type electrode 520 may be formed on a part of the n-type semiconductor layer 310 exposed by the first via hole V1. That is, the n-type electrode 520 is formed at the center portion of the n-type semiconductor layer 310 exposed by the first via hole V1 and the side wall of the first via hole V1 is formed around the n- Type semiconductor layer 330 and the n-type electrode 520 or the p-type electrode 400 (see FIG. 4) so that a current flows or a voltage is applied to the inner surface of the first via hole V1 to cover the active layer 320, ) And the n-type electrode 520 may be formed.

The insulating layer 600 is disposed in the first via hole V1 passing through the active layer 320 and the p-type semiconductor layer 330 to electrically isolate the p-type semiconductor layer 330 from the n-type electrode 520. [ That is, the insulating layer 600 is formed along the sidewalls of the first via hole V1 between the p-type semiconductor layer 330 and the n-type electrode 520 to form the p-type semiconductor layer 330 and the n- the n-type semiconductor layer 310 or the p-type semiconductor layer 330 and the n-type electrode 520 or the p-type electrode 400 and the n-type electrode 520 are electrically isolated from each other. The insulating film 600 may be made of SiO ₂ , or an oxide or nitride having electrical insulation properties such as Si ₃ N ₄ and Al ₂ O ₃ , an SiN Can be used. As described above, the insulating film 600 is formed of an oxide or a nitride to electrically isolate the p-type electrode 400 from the n-type electrode 520, and at the same time, impurities are generated in the formation of the through- Can be minimized.

The insulating layer 600 extends along the side wall of the via hole and a second via hole V2 is formed through the insulating layer 600 under the insulating layer 600. [

The n-type electrode 520 may be provided by filling a second via hole V2 through the insulating layer 600 with a conductive material. Here, the second via hole V2 may be formed at the center of the first via hole V1. That is, a first via hole V1 passing through the active layer 320 and the p-type semiconductor layer 330 is formed at the central portion of the unit semiconductor stacked structure 300 and a second via hole The second via hole V2 is formed at the center of the unit semiconductor multilayer structure 300 and the n-type electrode 520 provided by filling the second via hole V2 with a conductive material is formed in the unit semiconductor laminate structure 300. [ May be disposed at the center of the structure 300, respectively.

The n-type electrode 520 is disposed at the central portion of the unit semiconductor laminated structure 300 by the insulating film 600 and the p-type electrode 400 is formed at the upper portion in the vertical direction of the n-type electrode 520 The distance between the p-type electrode 400 and the n-type electrode 520 disposed in each of the unit semiconductor stacked structures 300 can be made smaller than the distance between the p-type electrode 400 and the n- The same can be maintained. Therefore, the same voltage or current can be applied to the plurality of unit semiconductor laminated structures 300, and uniform light emission can be obtained.

In the microarray light emitting diode according to the embodiment of the present invention, the n-type electrode 520 is formed by filling the second via hole V2 formed in the first via hole V1 with a conductive material, thereby forming the first via hole V1 ) Can be reduced to minimize the non-emission area and improve the light extraction efficiency. In this case, the first via hole V1 can have a diameter of about 3 to 7 mu m, and the light emitting area of the unit semiconductor stacked structure 300 and the p-type electrode 400 can be minimized and the light extraction efficiency can be improved.

The second via hole V2 not only penetrates the active layer 320 and the p-type semiconductor layer 330 but also extends to the inside of the n-type semiconductor layer 310 so that at least a part of the n- As shown in FIG. In this case, the lower portion 522 of the n-type electrode 520 formed by filling the second via hole V2 with a conductive material may be in contact with the n-type semiconductor layer 310 on the side. In other words, the n-type electrode 520 may be formed as a penetrating electrode which is partially inserted into the n-type semiconductor layer 310 as shown in Figs. 3 and 4, Type semiconductor layer 310. The n-type semiconductor layer 310 is formed as an electrode and extends to the inside of the n-type semiconductor layer 310, thereby increasing the area of the n-type electrode 520 in contact with the n-type semiconductor layer 310, And the n-type electrode 520, thereby improving the electrical characteristics.

4, the microarray light emitting diode further includes an n-type auxiliary electrode 540 extending upward from the n-type electrode 520 along the surface of the insulating layer 600 can do. The n-type auxiliary electrode 540 has a hollow internal space and extends upward along the surface of the insulating layer 600. By forming the n-type auxiliary electrode 540 on the n-type electrode 520, Type electrode 520 and the later-described n-type plug 740 can be improved. In particular, even when the second via hole V2 is formed to have a fine diameter by laser processing or the like, current or voltage can be stably applied.

In addition, the microarray light emitting diode according to the embodiment of the present invention includes a first interlayer insulating layer 820 provided on a p-type electrode 400; an n-type electrode pad 720 electrically connected to the n-type electrode 520 and provided on the first interlayer insulating layer 820; A second interlayer insulating layer 840 provided on the n-type electrode pad 720; And a p-type electrode pad (920) electrically connected to the p-type electrode (400) and provided on the second interlayer insulating layer (840).

The n-type electrode pad 720 is formed on the first interlayer insulating layer 820 to electrically connect the n-type electrodes 520 included in the plurality of unit semiconductor stacked structures 300 to each other And an n-type common pad (760) connected to the n-type electrode pad (720) and provided outside the plurality of unit semiconductor stacked structures (300) A light emitting diode may be constituted. In this case, the p-type electrode pad 920 may be provided separately for each p-type electrode 400 included in the unit semiconductor stacked structure 300 and electrically connected to the p-type electrode 400, respectively.

The first interlayer insulating layer 820 electrically isolates the p-type electrode 400 from the n-type electrode pad 720 provided on the first interlayer insulating layer 820, May be formed on the front surface. The second interlayer insulating layer 840 electrically insulates the n-type electrode pad 720 from the p-type electrode pad 920 provided on the second interlayer insulating layer 840, Type electrode pad 720 on the first electrode pad 820.

Here, in order to ensure sufficient insulation, the thickness of the first interlayer insulating layer 820 and the second interlayer insulating layer 840 may be about 0.5 탆 or more, and may be formed of a photosensitive polyimide material having excellent insulation property have.

After the first interlayer insulating layer 820 is formed on the n-type electrode 520, the n-type electrode pad 720 is formed on the first interlayer insulating layer 820. The n-type electrode 520 and the n-type electrode pad 720 are electrically connected by an n-type plug 740 filling the first via hole V1 with a conductive material. Since the second via hole V2 is formed at the center of the first via hole V1 as described above, the second via hole V2 can have an average sectional area smaller than that of the first via hole V1, The cross-sectional area of the lower end of the n-type plug 740 filled in the first via hole V1 is larger than the cross-sectional area of the upper end of the n-type electrode 520 filled in the second via hole V2. By forming the cross-sectional area of the lower end of the n-type plug 740 larger than the cross-sectional area of the upper end of the n-type electrode 520, the area occupied by the n-type electrode 520 in the unit semiconductor laminated structure 300 can be minimized , The non-emission area can be minimized and the light extraction efficiency can be improved as described above.

The n-type electrode pad 720 is formed of a metal material having excellent conductivity. The n-type electrode pad 720 extends on the first interlayer insulating layer 820, 520 are electrically connected to each other. That is, the n-type electrode pad 720 is formed in each of the plurality of unit semiconductor laminated structures 300, and a plurality of n-type electrodes 520 arranged two-dimensionally are arranged in a first direction and a direction crossing the first direction As shown in FIG. The n-type electrode pad 720 may have a lattice shape in which a plurality of first conductive lines 721 extending in the row direction and a plurality of second conductive lines 722 extending in the longitudinal direction cross each other And an n-type electrode 520 is disposed under the region where the plurality of conductive lines intersect. For example, the first conductive line 721 may be an n-type common pad provided outside the unit semiconductor laminated structure 300, (Not shown). By forming the n-type electrode pad 720 so as to have a lattice shape in which a plurality of conductive lines cross each other, the power applied from the n-type common pad 760 is applied to the n- 520, and it is also possible to effectively discharge heat generated by applying a voltage or current for light emission to the outside.

a second interlayer insulating layer 840 is formed on the n-type electrode pad 720 and the first interlayer insulating layer 820 and a p-type electrode pad 920 is formed on the second interlayer insulating layer 840 . Here, the n-type electrode pad 720 electrically connects a plurality of n-type electrodes 520 included in the plurality of unit semiconductor stacked structures 300 to each other, while a plurality of p-type electrode pads 920 are provided And the plurality of p-type electrodes 400 included in the plurality of unit semiconductor stacked structures 300 are independently electrically connected to each other. Each of the p-type electrodes 400 is connected to each p-type electrode pad 920 by a p-type plug 940. The p-type electrode 400 and the n-type electrode 520 have the same conductivity It may be formed of a metal material.

5 is a view illustrating a connection between a micro array light emitting diode and a circuit board according to an embodiment of the present invention. 5A is a plan view showing a micro array light emitting diode according to an embodiment of the present invention, FIG. 5B is a plan view showing a circuit board according to an embodiment of the present invention, FIG. 5C is a cross- Sectional view showing a state where a micro-array light-emitting diode and a circuit board are connected to constitute a light-emitting device.

Referring to FIG. 5, a light emitting device according to an embodiment of the present invention includes the above-described micro array light emitting diode; And a circuit board 100 on which a power terminal 1200 for applying power and a plurality of transistors 1300 are mounted, and an n-type electrode 520 included in each of the plurality of unit semiconductor stacked structures 300 Are commonly connected to the power supply terminal 1200 and the p-type electrodes 400 included in the plurality of unit semiconductor stacked structures 500 are individually connected to the plurality of transistors 1300, respectively.

That is, the n-type common pad 760 is electrically connected to the power supply terminal 1200 of the circuit board 1000, and the p-type electrode pad 920 is electrically connected to the plurality of transistors 1300 mounted on the circuit board 1000 And the light emitting device can be constituted by being electrically connected to each other. That is, in the light emitting device according to the embodiment of the present invention, a plurality of p-type electrodes 400 included in a plurality of unit semiconductor laminated structures 300 are electrically connected to a plurality of transistors 1300, The plurality of unit semiconductor laminated structures 300 are individually controlled to be turned on by applying external power to the n-type common pad 720 electrically connected in common by the electrode 520 and the n-type electrode pad 720 Active) drive.

Hereinafter, a method of manufacturing a micro array light emitting diode according to an embodiment of the present invention will be described in detail. In the description of the method of fabricating the micro-array light-emitting diode according to the embodiment of the present invention, the description of the micro-array light-emitting diode according to the embodiment of the present invention will be omitted.

6 is a view illustrating a method of manufacturing a micro array light emitting diode according to an embodiment of the present invention, and FIG. 7 is a view illustrating another method of manufacturing a micro array light emitting diode according to an embodiment of the present invention. 8 is a view illustrating a method of manufacturing a micro array light emitting diode according to another embodiment of the present invention.

6 to 8, a method of manufacturing a microarray light emitting diode according to an exemplary embodiment of the present invention includes forming an n-type semiconductor layer 310, an active layer 320, and a p-type semiconductor layer 330 on a substrate 100 Forming a unit semiconductor laminated structure 300 that is two-dimensionally arranged and separated; Forming a first via hole (V1) in the unit semiconductor stack structure (300) so that the n-type semiconductor layer (310) is exposed; Forming an insulating layer 600 on a sidewall of the first via hole V1; Forming an n-type electrode (520) on the exposed n-type semiconductor layer (310); And forming a p-type electrode (400) on the p-type semiconductor layer (330).

First, in a method of manufacturing a microarray light emitting diode according to an embodiment of the present invention, an n-type semiconductor layer 310, an active layer 320, and a p-type semiconductor layer 330 are stacked on a substrate 100. The active layer 320 and the p-type semiconductor layer 330 are then etched and patterned to form a unit semiconductor laminated structure 300 that is two-dimensionally separated and arranged on the substrate 100. In this case, Can be formed. That is, the active layer 320 and the p-type semiconductor layer 330 are etched or etched to a part of the n-type semiconductor layer 310 as well as the active layer 320 and the p-type semiconductor layer 330, The unit semiconductor laminated structure 300 can be formed. The unit semiconductor stacked structures 300 separated on the substrate 100 by such a process can be arranged in two dimensions to form a microarray.

The buffer layer 200 is formed before the n-type semiconductor layer 310, the active layer 320 and the p-type semiconductor layer 330 are laminated on the substrate 100. The n-type semiconductor layer 330 is formed on the buffer layer 200, Layer 310, the active layer 320, and the p-type semiconductor layer 330 may be stacked, and a description of the overlapped portions with respect to the buffer layer 200 will be omitted.

The first via hole V1 is formed by forming a first via hole V1 in the unit semiconductor stacked structure 300 such that the n-type semiconductor layer 310 is exposed. Here, the first via hole V1 may be formed by forming a first photoresist layer on the p-type semiconductor layer 330, exposing and developing the first photoresist layer in the portion to be etched, Layer 310 may be etched so as to be exposed, or a first photoresist layer may be formed on the p-type semiconductor layer 330 and a laser may be irradiated on the first photoresist layer. The first via hole V1 may be formed by forming a first photoresist layer 560 on the p-type semiconductor layer 330 as shown in FIG. 8 and forming a first photoresist layer 560 on the first The photoresist layer 560 may be removed and the p-type semiconductor layer 330 may be irradiated with a laser beam. In this case, it is possible to prevent impurities from being generated from the first photoresist layer 560 formed mainly of an organic material such as polyimide by the irradiation of the laser.

In the process of forming the insulating layer 600, an insulating layer 600 is formed on the sidewall of the first via hole V1 formed by the above-described process. Here, the process of forming the insulating film 600 includes the steps of forming an insulating film pattern 610 on the inner surface of the first via hole V1; And forming a second via hole V2 through the lower surface of the insulating film pattern 610. The process of forming the n-type electrode 520 may include forming the second via hole V2 in a conductive material . ≪ / RTI >

That is, in the process of forming the insulating film 600, the insulating film layer is formed on the p-type semiconductor layer 330 and the second via hole V2 is formed through the insulating film layer at the center of the first via hole V1 And forming an insulating layer pattern 610 by patterning the insulating layer 600 such that the insulating layer is separated from the plurality of unit semiconductor stacked structures 300 before the second via hole V2 is formed . ≪ / RTI >

Here, the process of forming the insulating layer on the p-type semiconductor layer 330, the other than SiO ₂ or SiO ₂ on the p-type semiconductor layer 330 comprising a first via hole (V1) Si ₃ N _4, Al ₂ O ₃ or the like and an insulating film layer formed of a material such as SiN or the like having an insulating property and capable of preventing a change in temperature or humidity. In this case, the p-type electrode 400 and the n-type electrode 520 can be electrically isolated from each other. In the case where the second via hole V2 is formed by irradiating a laser beam, impurities can be prevented from being generated by the organic material .

In the process of patterning the insulating film layer, an insulating film pattern is formed by patterning the insulating film layer so that the insulating film layer is divided into a plurality of unit semiconductor laminated structures 300. Such patterning of the insulating film layer can be performed by forming an insulating film layer on the first photoresist layer on which the first via hole V1 is formed and removing the first photoresist layer by a lift-off method.

In the process of forming the second via hole V2, the second via hole V2 is formed through the insulating layer 600 at the center of the first via hole V1. Here, the second via hole V2 is filled with a conductive material to form the n-type electrode 520, as described later. The second via hole V2 may extend through the insulating layer 600 and extend to a predetermined depth of the n-type semiconductor layer 310. In this case, the lower portion 522 of the n- -Type semiconductor layer 310 and the through-hole electrode. As described above, the n-type electrode 520 is formed as a penetrating electrode and extends to the inside of the n-type semiconductor layer 310, thereby increasing the area in which the n-type electrode 520 is in contact with the n-type semiconductor layer 310 As a result, it is possible to maintain an effective ohmic contact between the n-type semiconductor layer 310 and the n-type electrode 520, thereby improving the electrical characteristics.

In addition, the process of forming the second via hole V2 may be formed such that the second via hole V2 has an average sectional area smaller than that of the first via hole V1. The process of forming the second via hole V2 in order to form the second via hole V2 so as to have a fine diameter and an average cross sectional area smaller than that of the first via hole V1 may be performed by using a specific In this case, the second via hole V2 may be formed to have an average diameter of about 3 to 7 mu m in the central portion of the unit semiconductor laminated structure 300. In this case, When the sectional area of the second via hole V2 is reduced in this manner, the light emitting area of the unit semiconductor laminated structure 300 and the non-light emitting area formed by the via hole in the p-type electrode 400 formed of the reflective electrode are minimized, The extraction efficiency can be improved.

In the process of forming the n-type electrode 520, the n-type electrode 520 is formed on the n-type semiconductor layer 310 exposed by the first via hole V1. More specifically, the process of forming the n-type electrode 520 exposes the n-type semiconductor layer 310 by the first via hole V1 and is formed on the insulator provided on the sidewall of the first via hole V1 And filling the second via hole V2 with a conductive material.

In order to form the n-type electrode 520 by filling the second via hole V2 with the conductive material, a second photoresist layer 570 is formed on the p-type semiconductor layer 330 including the first via hole V1, After the second photoresist layer 570 in the portion corresponding to the second via hole V2 is exposed and developed, an n-type electrode layer 580 is formed on the second photoresist layer 570 to form n Type electrode layer 580 may be filled in the second via hole V2. 6 and 7, the process of forming the n-type electrode 520 may include forming a conductive material in the second via hole V2 according to the exposure and development regions of the second photoresist layer 570, 8, an n-type auxiliary electrode 540 extending along the inner wall of the insulating layer 600 may be formed and a conductive material may be formed in the second via hole V2, Lt; / RTI >

Thereafter, a p-type electrode 400 is formed on the p-type semiconductor layer 330. The p-type electrode 400 is formed on the p-type semiconductor layer 330 to supply current to the p-type semiconductor layer 330 and the process of forming the p- So that a duplicate description thereof will be omitted.

A method of fabricating a microarray light emitting diode according to an embodiment of the present invention includes: forming a first interlayer insulating layer 820 on the p-type electrode 400; Forming an n-type electrode pad (720) electrically connected to the n-type electrode (520) on the first interlayer insulating layer (820); Forming a second interlayer insulating layer 840 on the first interlayer insulating layer 820; And forming a p-type electrode pad 920 electrically connected to the p-type electrode 400 on the second interlayer insulating layer 840.

The method of manufacturing a microarray light emitting diode according to an embodiment of the present invention includes forming an n-type common pad 760 on the outer side of the plurality of unit semiconductor stacked structures 300 to be connected to the n-type electrode pad 720 And forming the n-type electrode pad (720), the process of forming the n-type electrode pad (720) includes the step of forming the n-type electrode layer (520) Type electrode pad 720 can be extended. In the process of forming the p-type electrode pad 920, the plurality of p-type electrode pads 920 are formed so as to be individually connected to the p-type electrodes 400 included in the unit semiconductor stacked structure 300 .

That is, the n-type electrode pad 720 is formed on the first interlayer insulating layer 820 and the p-type electrode pad 920 is formed on the second interlayer insulating layer 840 And is exposed to the outside. Here, the n-type electrode pad 720 is formed to electrically connect a plurality of n-type electrodes 520 included in the plurality of unit semiconductor stacked structures 300 to each other to form an n-type electrode pad 720 Type common pad 760, which is electrically connected to the n-type electrode 520, may be formed at the same time.

The n-type electrode pad 720 may be formed by forming an n-type electrode layer on the first interlayer insulating layer 820 including the first via hole V1 and patterning the formed n-type electrode layer. In this process, The via hole V1 is filled with a conductive material to form an n-type plug 740. The n-type electrode pad 720 is formed in each of the plurality of unit semiconductor stacked structures 300 and includes a plurality of n-type electrodes 520 two-dimensionally arranged in a first direction and a direction crossing the first direction As shown in FIG. That is, the n-type electrode pad 720 may have a lattice shape in which a plurality of conductive lines extending in the row direction and the column direction are arranged to cross each other, and an n-type electrode And the conductive line may be formed to be electrically connected to the n-type common pad 760 provided outside the unit semiconductor stacked structure 300. By forming the n-type electrode pad 720 so as to have a lattice shape in which a plurality of conductive lines cross each other, the power applied from the n-type common pad 760 is applied to the n- 520, and the heat generated from each of the unit semiconductor stacked structures 300 can be effectively radiated to the outside through the light emission as described above.

a second interlayer insulating layer 840 is formed on the n-type electrode pad 720 and the first interlayer insulating layer 820 and a p-type electrode pad 920 is formed on the second interlayer insulating layer 840 . The p-type electrode pad 920 may be formed by forming a p-type electrode layer on the second interlayer insulating layer 840 and patterning the formed p-type electrode layer. A plurality of p-type electrode layers are formed, And is electrically connected to the plurality of p-type electrodes 400 included in the unit semiconductor stacked structure 300 independently of each other. It is needless to say that the p-type electrode 400 may be formed of a metal material having excellent conductivity as the n-type electrode 520.

Meanwhile, although a specific process is not shown, a method of manufacturing a light emitting device according to an embodiment of the present invention includes the steps of providing a micro array light emitting diode manufactured by any one of the methods described above; A step of providing a power source terminal 1200 for applying power and a circuit board 100 on which a plurality of transistors 1300 are mounted; Connecting the n-type electrode 520 included in each of the plurality of unit semiconductor stacked structures 300 to the power supply terminal 1200; And individually connecting the p-type electrodes 400 included in the plurality of unit semiconductor stacked structures 300 to the plurality of transistors 1300, respectively.

That is, as described above, the n-type common pad 760 is electrically connected to the power supply terminal 1200 of the circuit board 1000, and the p-type electrode pad 920 is electrically connected to the plurality of transistors The light emitting device according to the embodiment of the present invention can be manufactured. In the light emitting device according to the embodiment of the present invention, a plurality of p-type electrodes 400 included in a plurality of unit semiconductor laminated structures 300 and a plurality of transistors 1300 are electrically connected to each other and a plurality of n-type electrodes 520 and the n-type electrode pad 720 by applying external power to the n-type common pad 720 electrically connected in common by the n-type electrode pad 520 and the n-type electrode pad 720, It becomes possible to drive.

As described above, according to the microarray light emitting diode and the method of fabricating the same according to the embodiment of the present invention, the insulating layer 600 is formed on the inner surface of the first via hole V1 passing through the active layer 320 and the p- Type semiconductor layer 330 and the n-type semiconductor layer 310 can be effectively isolated from the outside of the active layer 320.

The n-type electrode 520 is formed by filling the second via hole V2 penetrating the insulating film 600 with a conductive material so that the first via hole V1 is spaced apart from the first via hole V1 The average cross-sectional area of the first via hole V1 is greatly reduced compared with the case where the n-type electrode 520 is formed so that the non-emission area formed by the first via hole V1 in the unit semiconductor stacked structure 300 is And the light extraction efficiency can be maximized.

In addition, an n-type electrode 520 and a p-type electrode 400 electrically connected to the n-type semiconductor layer 310 and the p-type semiconductor layer 330 are provided for each of the plurality of unit semiconductor laminated structures 300 , the unit semiconductor laminated structure 300 can be electrically isolated while maintaining the same distance between the n-type electrode 520 and the p-type electrode 400, so that excellent electrical characteristics and uniform light emission Can be obtained.

The plurality of n-type electrodes 520 included in the plurality of unit semiconductor stacked structures 300 are electrically connected to each other by the n-type electrode pads 720, Or a current can be applied, and heat generated by application of voltage or current for light emission can be effectively emitted to the outside. In addition, a plurality of n-type electrodes 520 are commonly connected to the power supply terminal 1200, and a plurality of p-type electrodes 400 are individually connected to the plurality of transistors 1300 and driven, The space between the unit semiconductor stack structures 300 can be minimized and the dark region between the unit semiconductor stack structures 300 can be minimized.

While the preferred embodiments of the present invention have been described and illustrated above using specific terms, such terms are used only for the purpose of clarifying the invention, and the embodiments of the present invention and the described terminology are intended to be illustrative, It will be obvious that various changes and modifications can be made without departing from the spirit and scope of the invention. Such modified embodiments should not be individually understood from the spirit and scope of the present invention, but should be regarded as being within the scope of the claims of the present invention.

100: substrate 200: buffer layer
300: unit semiconductor laminated structure 310: n-type semiconductor layer
320: active layer 330: p-type semiconductor layer
400: p-type electrode 520: n-type electrode
540: n-type auxiliary electrode 600: insulating film
720: n-type electrode pad 740: n-type plug
760: n-type common pad 820: first interlayer insulating layer
840: second interlayer insulating layer 920: p-type electrode pad
940: p-type plug

Claims (20)

Board;
A plurality of unit semiconductor laminated structures including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer stacked on the substrate, the two or more unit semiconductor stacked structures being arranged in two dimensions;
A p-type electrode provided on the p-type semiconductor layer;
An n-type electrode provided on the n-type semiconductor layer exposed by a first via hole penetrating the active layer and the p-type semiconductor layer;
An insulating film provided on an inner surface of the first via hole;
A first interlayer insulating layer provided on the p-type electrode;
An n-type electrode pad electrically connected to the n-type electrode and provided on the first interlayer insulating layer;
A second interlayer insulating layer provided on the n-type electrode pad; And
And a p-type electrode pad electrically connected to the p-type electrode and provided on the second interlayer insulating layer,
Wherein the n-type electrode and the n-type electrode pad are connected by an n-type plug formed by filling the first via hole with a conductive material,
Sectional area of the lower end of the n-type plug is larger than that of the upper end of the n-type electrode.
The method according to claim 1,
And the n-type electrode is formed by filling a second via hole passing through the insulating film with a conductive material.
The method of claim 2,
And the second via hole extends into the n-type semiconductor layer.
The method according to claim 1,
And the n-type electrode is disposed at a central portion of the unit semiconductor laminated structure.
Board;
A plurality of unit semiconductor laminated structures including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer stacked on the substrate, the two or more unit semiconductor stacked structures being arranged in two dimensions;
A p-type electrode provided on the p-type semiconductor layer;
An n-type electrode provided on the n-type semiconductor layer exposed by a first via hole penetrating the active layer and the p-type semiconductor layer; And
And an insulating layer provided on an inner surface of the first via hole,
And an n-type auxiliary electrode extending from an upper surface of the n-type electrode along the surface of the insulating film.
delete delete The method according to claim 1,
Wherein the n-type electrode pad extends on the first interlayer insulating layer to electrically connect the n-type electrodes included in the plurality of unit semiconductor laminated structures to each other,
And an n-type common pad connected to the n-type electrode pad and provided outside the plurality of unit semiconductor stacked structures.
The method according to claim 1,
Wherein the p-type electrode pad is provided separately for each p-type electrode included in the unit semiconductor stacked structure.
The method according to claim 1,
And the p-type electrode reflects light emitted from the active layer.
A microarray light emitting diode according to any one of claims 1 to 5, and 8 to 10. And
And a circuit board on which a power source terminal for applying power and a plurality of transistors are mounted,
The n-type electrodes included in the plurality of unit semiconductor laminated structures are commonly connected to the power supply terminal,
And the p-type electrode included in each of the plurality of unit semiconductor laminated structures is individually connected to the plurality of transistors.
A process of laminating an n-type semiconductor layer, an active layer and a p-type semiconductor layer on a substrate and forming a unit semiconductor stacked structure arranged two-dimensionally;
Forming a first via hole in the unit semiconductor stack structure to expose the n-type semiconductor layer;
Forming an insulating film on a sidewall of the first via hole;
Forming an n-type electrode on the exposed n-type semiconductor layer;
Forming a p-type electrode on the p-type semiconductor layer;
Forming a first interlayer insulating layer on the p-type electrode;
Forming an n-type electrode pad electrically connected to the n-type electrode on the first interlayer insulating layer;
Forming a second interlayer insulating layer on the first interlayer insulating layer; And
And forming a p-type electrode pad electrically connected to the p-type electrode on the second interlayer insulating layer,
Wherein the n-type electrode and the n-type electrode pad are connected by an n-type plug formed by filling the first via hole with a conductive material,
Sectional area of the lower end of the n-type plug is larger than that of the upper end of the n-type electrode.
The method of claim 12,
The process of forming the insulating film may include:
Forming an insulating film pattern on an inner surface of the first via hole; And
And forming a second via hole through the lower surface of the insulating film pattern,
The process of forming the n-type electrode includes:
And filling the second via hole with a conductive material.
14. The method of claim 13,
The forming of the second via-
And the second via hole extends through the insulating film pattern to extend to a predetermined depth of the n-type semiconductor layer.
14. The method of claim 13,
The forming of the second via-
Wherein the second via hole is formed to have an average cross-sectional area smaller than that of the first via hole.
14. The method of claim 13,
The forming of the second via-
And a lower surface of the insulating film pattern is selectively irradiated with a laser beam.
delete The method of claim 12,
And forming an n-type common pad outside the plurality of unit semiconductor stack structures to be connected to the n-type electrode pad,
The process of forming the n-type electrode pad includes:
And the n-type electrode pad is extended to electrically connect the n-type electrodes included in the plurality of unit semiconductor laminated structures to each other.
The method of claim 12,
The process of forming the p-type electrode pad includes:
And the p-type electrode pads are formed in a plurality of the p-type electrode pads so that the p-type electrode pads are individually connected to the p-type electrodes included in the unit semiconductor stacked structure.
A step of providing a micro array light emitting diode manufactured by any one of claims 12 to 16, 18 and 19;
A circuit board on which a power terminal for applying power and a plurality of transistors are mounted;
Connecting n-type electrodes included in each of the plurality of unit semiconductor laminated structures to the power supply terminal in common; And
And connecting each of the p-type electrodes included in the plurality of unit semiconductor laminated structures to the plurality of transistors individually.

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