JPH10335179A - Thin film capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the current path and reduce the inductance, by forming a first electrode layer and a second electrode layer within the same plane. SOLUTION: A capacitance element A has a positive electrode layer 2 formed on the lower surface of a dielectric layer 1, and a negative electrode layer 3 formed on the upper surface. A capacitance element B has a negative electrode layer 3 formed on the lower surface of a dielectric layer 1, and a positive electrode layer 2 formed on the upper surface. The capacitance elements A and B are juxtaposed at a predetermined spacing. The negative electrode layer 3 of the capacitance element B is formed on the same plane as the positive electrode layer 2 of the capacitance element A, and the positive electrode layer 2 of the capacitance element B is formed on the same plane as the negative electrode layer 3 of the capacitance element A. The positive electrode layer 2 and the negative electrode layer 3 are formed in rectangular shapes, and the dielectric layer 1 has a size enough to cover the positive electrode layer 2 or the negative electrode layer 3 formed on the lower surface of the dielectric layer 1. On the positive electrode layers 2 and the negative electrode layers 3 of the pair of capacitance elements A and B, connection terminal electrodes 5 protruding toward the facing capacitance elements A and B are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film capacitor, for example, a large-capacity, low-inductance thin-film capacitor provided in an electric circuit operating at high speed and used for bypassing high-frequency noise or preventing fluctuations in power supply voltage. It relates to a thin film capacitor.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there has been a growing demand for electronic components installed in the electronic devices to be smaller, thinner, and compatible with high frequencies.

In particular, in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is from 100 MHz to several hundred MHz, and the clock frequency of the bus between chips is also from 30 MHz, even at the personal computer level. The high-speed operation is remarkable at 75 MHz.

As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to suppress power consumption. As the speed, density, and voltage of these IC circuits have increased, it has become essential for passive components, such as capacitors, to exhibit excellent characteristics with respect to high-frequency or high-speed pulses, along with increasing the size and capacity. I have.

In order to reduce the size and the capacity of a capacitor, it is most effective to make the dielectric sandwiched between the pair of electrodes thinner and thinner. The thinning also conforms to the above-mentioned tendency of voltage drop.

On the other hand, various problems associated with the high-speed operation of the IC circuit are more serious than miniaturization of each element. Of these functions, the function of the capacitor, which is particularly important in the function of removing high-frequency noise, is that the instantaneous drop of the power supply voltage that occurs when simultaneous switching of logic circuits occurs at the same time is a measure of the energy stored in the capacitor. This function is reduced by supplying the This is a so-called decoupling capacitor.

[0007] The performance required of the decoupling capacitor lies in how quickly the current can be supplied in response to the current fluctuation in the load section faster than the clock frequency. Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.

However, an actual capacitor element has a resistance component and an inductance component in addition to a capacitance component. The impedance of the capacitance component decreases with increasing frequency,
The inductance component increases as the frequency increases.
For this reason, as the operating frequency increases, the transient current to be supplied by the inductance of the element is limited, and the power supply voltage on the logic circuit side instantaneously drops or new voltage noise is generated. As a result, an error occurs in the logic circuit.

Particularly, in recent LSIs, the power supply voltage has been reduced in order to suppress an increase in power consumption due to an increase in the total number of elements.
The allowable fluctuation range of the power supply voltage is also small. Therefore, it is very important to reduce the inductance of the decoupling capacitor element itself in order to minimize the voltage fluctuation width during high-speed operation.

There are three ways to reduce inductance. The first is a method for minimizing the length of the current path, the second is a method for minimizing the loop cross-sectional area by forming the current path into a loop structure, and the third is a method of distributing the current path into n pieces to reduce the effective inductance by one. / N.

The first method may be achieved by increasing the capacity per unit area to achieve miniaturization, and can be achieved by reducing the thickness of the capacitor element. For the purpose of obtaining a capacitor having a large capacity and good high-frequency characteristics, Japanese Patent Application Laid-Open No. 60-94716 discloses a capacitor in which the thickness of a dielectric material is reduced to 1 μm or less.

The second method has an effect of reducing the magnetic field formed by one current path by the magnetic field formed by another adjacent current path. Therefore, a pair of electrode plates or electrodes forming a capacitor is used. The directions of the currents flowing through the layers should not be in the same direction as much as possible.

In the third method, low inductance can be achieved by connecting the divided capacitors in parallel.
As such a capacitor, Japanese Patent Laid-Open Publication No.
Japanese Patent Application Laid-Open Publication No. H11-163,887 discloses a device using a thin film dielectric layer.

[0014]

However, when considering a decoupling capacitor that can be mounted at a desired place, the size that can be handled is 0.5 mm × 0.5 mm.
mm or more is required, and there is a limit to reducing the inductance by only the first thin film and the method of miniaturization.

Further, in the second method, the positive and negative terminal electrodes need to be at the same end face or orthogonal to each other, which is disadvantageous in mounting.

The third method of split parallel connection is advantageous for a built-in board type, but has no flexibility in mounting. In addition, although ordinary multilayer capacitors are also connected in parallel, the magnetic field formed by each electrode current is superimposed because the direction of the current is the same. That is, since the mutual inductance becomes large, the effective total inductance cannot be sufficiently reduced. Therefore, it was necessary to employ the second means together, but as described above, there was a mounting problem due to the problem of the terminal electrode.

An object of the present invention is to provide a thin film capacitor having a low inductance structure which is easy to mount and easy to laminate.

[0018]

According to the present invention, there is provided a thin film capacitor comprising: a first capacitor having a first electrode layer formed on an upper surface of a dielectric layer and a second electrode layer formed on a lower surface; The two electrode layers are juxtaposed with a second capacitance element having a first electrode layer formed on the lower surface, and the first electrode layers and the second electrode layers of the first capacitance element and the second capacitance element are connected to a connection terminal. Each is connected via an electrode.

Also, a plurality of electrode layers and a plurality of dielectric layers are alternately laminated, and the first and second electrode layers are alternately stacked from the bottom.
A first capacitive element serving as an electrode layer or a second electrode layer, and a plurality of electrode layers and a plurality of dielectric layers are alternately laminated, and the electrode layers are alternately arranged from below on the second electrode layer or the second electrode layer. Along with juxtaposing the second capacitance element formed as one electrode layer,
The first electrode layers and the second electrode layers of the capacitor and the second capacitor are connected to each other via connection terminal electrodes.

[0020]

In the thin-film capacitor of the present invention, the pair of capacitors are juxtaposed at a predetermined interval, so that the pair of capacitors includes the first electrode layer (for example, the positive electrode layer) and the second electrode layer in the same plane. Since an electrode layer (for example, a negative electrode layer) is formed and the distance between the positive electrode layer and the negative electrode layer can be reduced, the current path can be shortened and the inductance can be reduced. it can.

Further, since the directions of the currents flowing through the positive electrode layer and the negative electrode layer of each of the capacitive elements are opposite to each other, the generated inductances are canceled out and can be reduced.

Further, since each electrode layer can be connected at the connection terminal electrode formed on the opposing surface, lamination is facilitated. Since the external terminal electrodes used for contact with the outside can be formed on the uppermost electrode layer, mounting is easy.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a single-plate type thin film capacitor according to the present invention, a pair of capacitive elements having a positive electrode layer and a negative electrode layer formed on the upper and lower surfaces of a dielectric layer are opposed to each other at a predetermined interval. At the same time, the electrode layer formed at a position facing the pair of capacitors is an electrode layer having a different polarity, and further, the positive electrode layer and the negative electrode layer of the pair of capacitors are directed toward the facing capacitor. A protruding connection terminal electrode is formed, and the connection terminal electrodes of the electrode layers having the same polarity are connected to each other in a pair of capacitance elements.

Further, in the laminated thin-film capacitor of the present invention, a pair of capacitive elements formed by alternately laminating a plurality of electrode layers and a plurality of dielectric layers are opposed to each other at a predetermined interval, and Are alternately positive electrode layers or negative electrode layers in the laminating direction, and the electrode layers formed at positions opposed to the pair of capacitive elements are electrode layers having different polarities. A connection terminal electrode protruding toward the opposing capacitance element is formed on each of the layer and the negative electrode layer, and the connection terminal electrodes of the electrode layers having the same polarity in the pair of capacitance elements are connected to each other.

As shown in FIGS. 1 to 3, the single-plate type thin film capacitor of the present invention has a positive electrode layer 2 (first electrode layer) and a negative electrode layer 3 (first electrode layer) on the upper and lower surfaces of a dielectric layer 1. A pair of capacitive elements A and B formed by forming two electrode layers) are juxtaposed to face each other. The electrode layers formed at positions facing the pair of capacitive elements A and B have different polarities.

The capacitors A and B are formed on the upper surface of the substrate 4.

That is, the capacitive element A has a positive electrode layer 2 formed on the lower surface of the dielectric layer 1 and a negative electrode layer 3 formed on the upper surface. The capacitive element B has a negative electrode layer formed on the lower surface of the dielectric layer 1. 3, the positive electrode layer 2 is formed on the upper surface. And the capacitive elements A and B
Are arranged at predetermined intervals, and the negative electrode layer 3 of the capacitive element B is on the same plane as the positive electrode layer 2 of the capacitive element A, and the capacitive element B is on the same plane as the negative electrode layer 3 of the capacitive element A. Of the positive electrode layer 2 is formed.

As shown in FIG. 4, the positive electrode layer 2 and the negative electrode layer 3 have a rectangular shape, and the dielectric layer 1 is formed on the lower surface of the dielectric layer 1 by the positive electrode layer 2 or the negative electrode layer. It has a rectangular shape large enough to cover the layer 3. The dielectric layers 1 are spaced apart from each other at a predetermined interval. Positive electrode layer 2 or negative electrode layer 3 formed on the upper surface of dielectric layer 1
Has the same shape and the same dimensions as the positive electrode layer 2 or the negative electrode layer 3 formed on the lower surface of the dielectric layer 1.

The thickness of the dielectric layer 1 is 0.1 to 1 μm, and the size is 1.2 mm long and 1.2 mm wide.
The thickness of the electrode layers 2 and 3 is 0.1 to 1 μm, and the size is 1.0 mm in length and 0.3 mm in width.

A connection terminal electrode 5 is formed on the positive electrode layer 2 and the negative electrode layer 3 of the pair of capacitance elements A and B so as to project toward the opposing capacitance elements A and B, respectively. The connection terminal electrodes 5 of the layers 2 and 3 are connected to each other.

The positive electrode connection portion 7 where the positive electrode layers 2 are connected to each other and the negative electrode connection portion 8 where the negative electrode layers 3 are connected to each other are spaced apart from each other by a predetermined distance, and are thereby insulated. The same material as that of the dielectric layer 1 may be filled between the positive electrode connecting portion 7 and the negative electrode connecting portion 8. In this case,
The dielectric layers 1 of the pair of capacitive elements A and B are connected to form an H shape when viewed in plan. Positive electrode layer 2 and negative electrode layer 3
Between the positive electrode connecting portion 7 and the negative electrode connecting portion 8 may be filled with the same material as the dielectric layer 1.

Although not shown, the thin-film capacitor of the present invention has external electrode terminals connected to, for example, the positive electrode layer 2 and the negative electrode layer 3 formed on the outermost surfaces of the capacitors A and B by soldering or the like. Thereby, the capacity is taken out.

As the substrate 4 used in the present invention, alumina, sapphire, MgO single crystal, SrTiO ₃ single crystal, titanium-coated silicon, or copper (Cu), nickel (Ni), titanium (Ti), tin (Sn) A stainless steel (SUS) thin film or thin plate is desirable. In particular, alumina and sapphire are desirable in terms of low reactivity with the thin film, low cost and high strength, and crystallinity of the dielectric film or the electrode film, and copper (Cu) thin plate or A copper (Cu) thin film is desirable.

Further, the electrode layer of the present invention comprises platinum (Pt),
There are gold (Au), palladium (Pd), copper (Cu) thin films and the like, and among these, platinum (Pt) and gold (Au) thin films and low-resistance copper (Cu) thin films are most suitable. This is because Pt and Au have low reactivity with the dielectric and are hardly oxidized, so that a low dielectric constant phase is hardly formed at the interface with the dielectric.

Further, the dielectric layer may have a high dielectric constant in a high frequency region, and the thickness thereof is 1 μm.
m or less is desirable. The dielectric layer is, for example, a dielectric thin film made of a perovskite-type composite oxide crystal containing Pb, Mg, and Nb as metal elements.
A dielectric thin film having a relative dielectric constant of 1000 or more at 00 MHz (room temperature) is desirable. In the present invention, Pb, Mg,
Other than a dielectric thin film composed of a perovskite-type composite oxide crystal containing Nb, for example, a perovskite-type composite oxide crystal containing Ba and Ti, PZT, PLZT, SrTiO
₃ , Ta ₂ O ₅ or the like may be used without any particular limitation. Such a dielectric layer is manufactured by a known method such as a PVD method, a CVD method, and a sol-gel method.

In the thin film capacitor configured as described above, since the pair of capacitors A and B are formed to face each other, the pair of capacitors A and B have the positive electrode layer 2 in the same plane. And the negative electrode layer 3 are formed at a predetermined interval, and the positive electrode layer 2 and the negative electrode layer 3 can be formed close to each other, so that the current path is shortened and the inductance is reduced. Can be smaller.

The positive electrode layer 2 in each of the capacitive elements
Since the direction of the current flowing through the negative electrode layer 3 is opposite to the direction of the current flowing through the negative electrode layer 3, the inductance cancels out in each of the positive electrode layer 2 and the negative electrode layer 3, and the generated inductance can be reduced.

Further, since the external terminal electrodes used for contact with the outside can be formed on the uppermost electrode layers 2 and 3, mounting is facilitated.

The laminated type thin film capacitor of the present invention will be described with reference to FIG. According to FIG. 5, a dielectric layer and an electrode layer are further laminated on the single-plate type thin film capacitor shown in FIG.

That is, a pair of capacitance elements A and B, which are formed by alternately laminating the electrode layers 2 and 3 and the dielectric layer 1, are juxtaposed. In these capacitance elements A and B, the electrode layers 2 and 3 are arranged in the laminating direction. The positive electrode layer 2 and the negative electrode layer 3 are alternately formed. The electrode layers 2 and 3 formed at opposing positions of the pair of capacitance elements A and B are electrode layers 2 and 3 having different polarities, and the positive electrode layer 2 and the negative electrode layer of the pair of capacitance elements A and B are formed. 3, a connection terminal electrode 5 protruding toward the opposing capacitance elements A and B is formed. The connection terminal electrodes 5 of the electrode layers 2 and 3 having the same polarity are electrically connected to each other.

The thin film capacitor of the present invention is generally formed on the surface of the substrate as described above, but may be used by being built in the substrate. When the external electrode terminal is built in the substrate, the external electrode terminal is, for example, a through-hole conductor formed in the substrate, whereby the capacitance is taken out.

Further, although the example in which the shape of the electrode layers 2 and 3 is rectangular has been described, any shape such as square or circular may be used.

Incidentally, a plurality of the thin film capacitors of the present invention described above may be connected and used.

In such a case, the current path is divided into n current paths, and the effective inductance is further increased by a factor of 1 / n. Such a thin film capacitor may be built in the substrate.

[0045]

【Example】

Example 1 An electrode layer and a dielectric layer were all formed by using a high-frequency magnetron sputtering method. Ar gas was introduced into the process chamber as a sputtering gas, and the pressure was maintained at 6.7 Pa by evacuation.

A substrate holder and three target holders are provided in the process chamber, and sputtering from three types of target materials is possible. At the time of sputtering, the substrate holder was moved to the target position of the kind of the material to be formed, and the distance between the substrate and the target was fixed at 60 mm.

A high frequency voltage of 13.56 MHz is applied between the substrate holder and the target by an external high frequency power supply, and a high density plasma is generated near the target by a magnetron magnetic field formed by a permanent magnet installed on the back of the target. Then, the target surface was sputtered.

High-frequency voltage can be applied to three targets independently. In this embodiment, plasma is generated by applying only to the target closest to the substrate. The substrate holder had a heating mechanism using a heater, and was controlled so that the substrate temperature during sputter deposition was constant.

Further, three types of metal masks having a thickness of 0.05 mm are provided on the target side of the substrate placed on the substrate holder, and necessary masks can be set on the substrate deposition surface according to the deposition pattern. Structured.

First, a pair of electrode layers having connection terminal electrodes as shown in FIG. 4A are formed on a 0.25 mm-thick alumina sintered body substrate by sputtering a platinum target with a first mask pattern. Followed by Pb
Using a (Mg _1/3 Nb _2/3 ) O ₃ sintered body, a second mask pattern was set, the substrate temperature was 535 ° C., and the high frequency power was 2
Under a condition of 00 W, a pair of dielectric layers having connection terminal electrodes as shown in FIG. 4B was formed. Next, a third mask pattern was set, and a pair of electrode layers as shown in FIG. 4C was formed by sputtering a platinum target. The area of the outer shape of the electrode layer was 0.6 mm ² .

1 MHz of the manufactured multilayer thin film capacitor
The impedance characteristics at 1.8 GHz can be measured using an impedance analyzer (HP by Hewlett-Packard Company).
As a result of measurement using 4291A), the capacitance component was 12.
A value of 5 nF and an inductance component of 150 pH was obtained. After the above measurement, when the cross section of the thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.3 μm.

As a comparative example, except that the structure of a conventional general thin-film capacitor as shown in FIG. When the components were measured, a capacitance component of 12.6 nF and an inductance component of 380 pH were obtained. In FIG. 6, the conventional thin film capacitor is configured by sequentially laminating a positive electrode layer 21, a dielectric layer 22, and a negative electrode layer 23 on the upper surface of a substrate 20, and the positive electrode layer 21, the negative electrode layer 23 A capacity take-out portion 24 is formed on the opposite side.

Example 2 A laminated thin-film capacitor having 10 dielectric layers was fabricated in exactly the same manner as in Example 1, and evaluated by the same method as in Example 1. The capacitance component was 126.1 nF, and the inductance component was 1
A value of 40 pH was obtained. After the above measurement, when the cross section of the multilayer thin film capacitor was observed by SEM, the thickness of each dielectric layer was 0.3 μm.

Example 3 A substrate material, an electrode material, an electrode forming method, a shape and dimensions were exactly the same as in Example 1, and only a dielectric film was formed by a sol-gel method. The procedure for producing a film by the sol-gel method was as follows.

Mg acetate and Nb ethoxide were weighed at a molar ratio of 1: 2, and refluxed in 2-methoxyethanol (1).
24 hours at 24 ° C.), and a MgNb composite alkoxide solution (Mg = 4.95 mmol, Nb10.05 mmol)
1, 2-methoxyethanol 150 mmol) was synthesized. Next, 15 mmol of lead acetate (anhydride) and 150 mmol
l of 2-methoxyethanol was mixed, and a Pb precursor solution was synthesized by a distillation operation at 120 ° C.

The MgNb precursor solution and the Pb precursor solution were mixed at a molar ratio of Pb: (Mg + Nb) = 1: 1,
Stir well at room temperature and add Pb (Mg _1/3 Nb _2/3 ) O ₃ (P
(MN) precursor solution was synthesized.

The solution was diluted about 3-fold with 2-methoxyethanol to obtain a coating solution. Next, on the electrode layer,
The coating solution was applied by a spin coater, dried, and then heat-treated at 300 ° C. for 1 minute to form a gel film. After repeating the application of the coating solution and the heat treatment, 8
Firing at 30 ° C. for 1 minute (in air) is performed, and Pb (Mg
_{A 1/3} Nb _2/3 ) O ₃ thin film was obtained.

A resist is applied on the obtained dielectric thin film, exposed and developed by a photolithography process, and the dielectric film is patterned into the same pattern shape as in Example 1 by wet etching using the resist as a mask. Then, the same thin-layer capacitor as in Example 1 was manufactured.

1 MHz of the manufactured laminated thin film capacitor
The impedance characteristics at 1.8 GHz can be measured using an impedance analyzer (HP by Hewlett-Packard Company).
4291A). As a result, a capacitance component of 50.2 nF and an inductance component of 160 pH were obtained. After the above measurement, the cross-sectional SEM
Upon observation, the thickness of each dielectric layer was 0.5 μm.

[0060]

As described above in detail, in the thin film capacitor of the present invention, the first electrode layer (positive electrode layer) and the second electrode
Since the electrode layer (negative electrode layer) is formed, the distance between the positive electrode layer and the negative electrode layer can be reduced, the current path can be shortened, and the inductance can be reduced. In addition, since each electrode layer can be connected at the connection terminal electrode, lamination becomes easy. Further, since the external terminal electrodes used for contact with the outside can be formed on the uppermost electrode layer, mounting is facilitated. Therefore, according to the present invention, a low-inductance thin-film capacitor that can be easily stacked and mounted can be provided.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view showing a thin film capacitor of the present invention.

FIG. 2 is a plan view of the thin film capacitor of the present invention.

FIG. 3 is a side view of the vicinity of a positive electrode connecting portion in FIG. 2;

FIG. 4 is a plan view showing an electrode layer and a dielectric layer.

FIG. 5 is an exploded perspective view showing a laminated type thin film capacitor.

FIG. 6 is an exploded perspective view showing a conventional thin film capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Dielectric layer 2 ... Positive electrode layer (1st electrode layer) 3 ... Negative electrode layer (2nd electrode layer) 4 ... Substrate 5 ... Connection terminal electrode A, B ...・ Capacitance element 7 ・ ・ ・ Positive electrode connection 8 ・ ・ ・ Negative electrode connection

Claims (2)

[Claims] 1. A first capacitor having a first electrode layer formed on an upper surface of a dielectric layer and a second electrode layer formed on a lower surface, a second electrode layer formed on an upper surface of the dielectric layer, and a first electrode layer formed on a lower surface. Are formed side by side, and the first and second electrode layers of the first and second capacitance elements are connected to each other via connection terminal electrodes. Characteristic thin film capacitor. 2. A first capacitive element comprising a plurality of electrode layers and a plurality of dielectric layers alternately laminated, wherein the first and second electrode layers are alternately formed as a first electrode layer or a second electrode layer from below. A plurality of electrode layers and a plurality of dielectric layers are alternately stacked, and the electrode layers are arranged side by side with a second capacitor element having a second electrode layer or a first electrode layer alternately from below. And a first electrode layer and a second electrode layer of the first and second capacitor elements are connected to each other via connection terminal electrodes.