JP2002231575A - Thin film capacitor and capacitor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an easy-to-mount thin film capacitor having a low inductance structure which can be multilayered easily. SOLUTION: Capacitance generating regions A, B and C each having a first electrode layer 2 and a second electrode layer 3 formed, respectively, on the lower surface and upper surface of a dielectric layer 1 are juxtaposed at specified intervals. A plurality of first terminal electrode layers 4 for interconnecting the first electrode layers 2 and a plurality of second terminal electrode layers 5 for interconnecting the second electrode layers 3 are provided, at specified intervals, between respective capacitance generating regions A, B and C. Assuming the pitch of the first terminal electrode layers and the second terminal electrode layers is Y (mm) and the number of terminal electrode layers provided in the interval on one side of the capacitance generating region is n, a following relation is satisfied; 1/10<2(n-1)/(273×Y+35).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film capacitor, for example, a low-inductance thin-film capacitor and a capacitor provided in an electric circuit operating at a high speed and used for bypassing high-frequency noise or preventing fluctuations in power supply voltage. It relates to a substrate.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there has been a growing demand for electronic components installed in the electronic devices to be smaller, thinner, and compatible with high frequencies. Particularly in a high-speed digital circuit of a computer which needs to process a large amount of information at high speed, the clock frequency in the CPU chip is as high as 100 MHz to several hundred MHz, and the clock frequency of the bus between chips is as high as 30 MHz to 100 MHz even at the personal computer level. Is remarkable.

As the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to reduce power consumption. Speeding up these IC circuits,
With the increase in density and the reduction in voltage, it has become essential for passive components such as capacitors to exhibit excellent characteristics with respect to high-frequency or high-speed pulses in addition to increasing the size and capacity.

[0004] In order to make a capacitor compact and have a high capacity, it is most effective to make a dielectric material sandwiched between a pair of electrodes thin and thin. The thinning also conforms to the above-mentioned tendency of voltage drop.

On the other hand, various problems associated with the high-speed operation of the IC circuit are more serious than miniaturization of each element. Of these, the most important in the function of removing high-frequency noise, which is the role of the capacitor, is to instantaneously supply the energy stored in the capacitor to the instantaneous drop in the power supply voltage that occurs when logic circuits switch simultaneously. This is a function that can be reduced by doing so. A capacitor having such a function is a so-called decoupling capacitor.

[0006] The performance required of the decoupling capacitor lies in how quickly the current can be supplied in accordance with the current fluctuation of the load section faster than the operating frequency. Therefore, when used for a clock frequency of 30 MHz to several hundred MHz, it must function reliably as a capacitor in the frequency range of 100 MHz to 1 GHz. That is, in this frequency range, the impedance of the capacitor must be small.

An actual capacitor element has a resistance component and an inductance component depending on the shape and structure of the electrodes and the like constituting the capacitance generation region in addition to the capacitance component. While the impedance of the capacitance component decreases with increasing frequency, the impedance of the inductance component increases with increasing frequency. Therefore, as the operating frequency increases, the transient current to be supplied by the inductance due to the electrodes in the capacitance generating region of the capacitor element is limited, and the power supply voltage on the logic circuit side drops instantaneously or new voltage noise is generated. . As a result, an error occurs in the logic circuit.

Particularly in recent LSIs, the power supply voltage has been reduced in order to suppress an increase in power consumption due to an increase in the total number of elements.
The allowable fluctuation range of the power supply voltage is also small. Therefore, it is very important to reduce the inductance of the decoupling capacitor element itself in order to minimize the voltage fluctuation width during high-speed operation.

There are three ways to reduce inductance. A first method is a method of minimizing the length of a current path, and a second method is a method of offsetting and reducing a magnetic field formed by one current path by a magnetic field formed by another current path adjacent thereto. The third method is a method of distributing the current path into n pieces to reduce the effective inductance to 1 / n. The present inventors have combined these methods and studied repeatedly, and as a result, have proposed several low-inductance thin-film capacitors such as Japanese Patent Application Laid-Open No. 2000-114099.

[0010]

As a result of such studies, it has been found that in order to produce a thin-film capacitor with low inductance, it is necessary to consider several important parameters in combination. The range of the inductance was found. On the other hand, a thin film capacitor is limited by its use in external size, electrostatic capacity, insulation characteristics, and the like, and a thin film capacitor having characteristics other than low inductance that is optimal for the application is required.

Until now, in order to obtain a thin film capacitor having characteristics suitable for the application including low inductance,
Design, trial production, and evaluation have to be repeated several times based on experience, which has required a great deal of labor.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a low-inductance thin-film capacitor having characteristics suitable for use, easy to mount, and easy to laminate. It is to provide a capacitor substrate easily without trial and error.

[0013]

The single-plate type thin film capacitor of the present invention has a first electrode layer on the lower surface of the dielectric layer and a second electrode layer on the upper surface of the dielectric layer.
A plurality of first terminal electrode layers for connecting the first electrode layers to each other between three capacitor generating regions formed with electrode layers at predetermined intervals, and between each of the capacitor generating regions;
A plurality of second terminal electrode layers for connecting the second electrode layers to each other are provided alternately at predetermined intervals, and the first terminals provided at one side interval of the centrally located capacitance generation region An electrode layer and the first terminal electrode layer provided at an interval on the other side are provided so as to substantially face each other, and the second terminal electrode layer provided at an interval on one side of the center capacitance generating region; In the thin film capacitor provided with the second terminal electrode layer provided at the other side interval substantially opposed to the first terminal electrode layer adjacent to each other at one side interval of the capacitance generating region located at the center, When the pitch Y (mm) with the second terminal electrode layer and the total number n (number) of the first terminal electrode layer and the second terminal electrode layer are 1/10 <2 (n−1) / (273 × Y + 35) A.

The laminated thin film capacitor according to the present invention comprises a plurality of dielectric layers and a plurality of electrode layers alternately laminated, and the electrode layers are alternately formed as a first electrode layer or a second electrode layer from below. The three capacitance generating regions are arranged side by side at predetermined intervals, and between each of the capacitance generating regions, a plurality of first terminal electrode layers connecting the first electrode layers and the second electrode layers are connected. A plurality of second terminal electrode layers to be connected are alternately provided at predetermined intervals, and a plurality of second terminal electrode layers are provided at an interval between the first terminal electrode layers provided on one side of the capacitance generating region located at the center and the other side. The provided first terminal electrode layer is provided so as to substantially face the first terminal electrode layer, and the second terminal electrode layer provided at one side interval of the capacitance generating region located at the center is provided at the other side interval. A thin-film capacitor provided with the second terminal electrode layer substantially opposed to the second terminal electrode layer; A pitch Y (mm) between the first and second terminal electrode layers adjacent to each other at one side interval of the capacitance generating region located at the center, and the first and second terminal electrode layers. Satisfies the range of 1/10 <2 (n−1) / (273 × Y + 35), further comprising a first terminal electrode layer and a second terminal electrode. An external terminal is provided on the layer, and the external terminal preferably has a bump shape.

Further, the capacitor substrate of the present invention has the above-mentioned thin film capacitor provided on the surface and / or inside of the substrate.

According to the basic structure of the thin film capacitor of the present invention, three (region) capacitance generating regions are juxtaposed at a predetermined interval, and a plurality of first terminal electrode layers and a second terminal electrode layer provided between the capacitance generating regions are provided.
In the terminal electrode layer, the first electrode layer and the second electrode layer of each capacitance generating region are connected to each other, and the first terminal electrode layer and the second terminal electrode layer are provided alternately at predetermined intervals, The first terminal electrode layer and the second terminal electrode layer on both sides of the capacitance generating region are provided so as to face each other. With such a structure, the first terminal electrode layer and the second terminal electrode layer are provided adjacent to each other, so that the effective current path is shortened and the direction of the current flowing through the electrode layer is widely spread. , The magnetic fields formed by the current paths cancel each other out,
The inductance can be made extremely small.

That is, the smaller the pitch between the first terminal electrode layer and the second terminal electrode layer and the larger the number of terminal electrode layers provided between the capacitance generating regions, the smaller the inductance. However, in manufacturing a thin film capacitor, there is a substantial limit to the interval and the number of terminal electrode layers due to limitations on the external size, capacitance, insulation characteristics, and the like. The inductance L (p
H) and a pitch Y between the first terminal electrode layer and the second terminal electrode layer.
(Mm) and the number n (pieces) of the terminal electrode layers provided between the capacitance generating regions is as follows: 1 / L = 2 (n−1) / L (Y) where L (Y) = 273 × Y + 35 (where Y is the distance through which the current flows, and substantially indicates the pitch (mm) between the terminal electrode layers), and 1/10 <2 (n−1) / (273 × Y + 35) Otherwise, the required inductance cannot be obtained. That is, when the right side of the above equation is smaller than 1/10, the pitch Y (mm) between the first terminal electrode layer and the second terminal electrode layer is long, or the pitch of the terminal electrode layer provided between the capacitance generating regions is large. Because the number n (pieces) is small, or for both reasons,
The inductance increases.

In addition, since the external terminal used for the contact with the outside can be formed on the first and second terminal electrode layers between the capacitance generating regions where the dielectric layer does not exist directly below, the external terminal can be formed at the time of forming the external terminal or Damage to the capacity generating region due to thermal stress at the time of mounting can be prevented, and there is no need to consider the adverse effects, so that manufacturing and mounting are facilitated.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIGS. 1 and 2, a single-plate type thin film capacitor of the present invention has a first electrode layer 2 as a positive electrode on the lower surface of a dielectric layer 1 and a negative electrode on the upper surface, for example. As for the capacitance generating regions formed by forming a certain second electrode layer 3, three capacitance generating regions A, B, and C are juxtaposed at a predetermined interval. In FIG. 2, the dielectric layer 1 is indicated by a broken line.

A plurality of first terminal electrode layers 4 and a plurality of second terminal electrode layers 5 are formed at respective intervals between the capacitance generating regions A, B, and C, and the first electrode layer of each of the capacitance generating regions A, B, and C is formed. The two are connected via a plurality of first terminal electrode layers 4, respectively.
The second electrode layers 3 of each of the capacitance generating regions A, B, and C are connected to each other through a plurality of second terminal electrode layers 5.

The first terminal electrode layer 4 and the second terminal electrode layer 5 are formed at both sides of the center of the capacitance generation region B, but are formed at one side of the center of the capacitance generation region. The first terminal electrode layer provided on the second side and the first terminal electrode layer provided on the other side are provided substantially facing each other, and provided on one side of the capacitance generating region located at the center. The second terminal electrode layer and the second terminal electrode layer provided on the other side are provided so as to substantially face each other.

That is, the interval on one side of the capacitance generation region B located at the center, which is on the left side in FIG. 2, the interval between the capacitance generation region A and the capacitance generation region B, and the other of the capacitance generation region B located at the center 2, which is on the right side in FIG. 2, and the distance between the capacitance generation area B and the capacitance generation area C located at the center includes:
The first terminal electrode layer 4 and the second
The terminal electrode layers 5 are formed alternately. Note that a predetermined distance (actually, the electrode width of each of the first terminal electrode layer 4 and the second terminal electrode layer 5) is provided between the first terminal electrode layer 4 and the second terminal electrode layer 5 formed at the same distance. Pitch Y (m
m)) are provided.

The first terminal electrode layer 4 provided at one side interval of the capacitance generating region B located at the center, the first terminal electrode layer 4 provided at the other side interval, and the second terminal electrode layer 4 provided at the one side interval. The terminal electrode layer 5 and the second terminal electrode layer 5 provided at the interval on the other side are substantially opposed to each other with a distance X (mm) therebetween.

That is, n terminal electrode layers 4 and 5 having different polarities are formed at intervals on one side or the other side, respectively, at both sides of the capacitance generating region B located at the center.
They are formed facing each other. The figure shows a case where the number of terminal electrode layers at one side (the sum of the number of first terminal electrodes and the number of second terminal electrode layers) n = 8.

The protective film 8 is formed so as to expose the terminal electrode layers 4 and 5 and completely cover the capacitance generating regions A, B and C. The exposed part of each of the terminal electrode layers 4 and 5 is supplied with a signal from an external circuit by forming an external terminal or the like.

The thin film capacitor including the three capacitance generating regions A, B, and C, the plurality of first and second terminal electrode layers 4, 5, and the protective film 8 is formed on the upper surface of the substrate 6.

FIG. 3 shows a plan view of the dielectric layer 1, the first and second electrode layers 2, 3, and the first and second terminal electrode layers 4, 5, respectively. As shown in FIG. 3A, the dielectric layer 1 is formed in a rectangular shape having a size to cover the first electrode layer 2 or the second electrode layer 3.

The dielectric layers 1 may be separated from each other at predetermined intervals as shown in FIG.
As shown in FIG. 3B, the dielectric layer 1 may be formed by connecting the connection portions 9 made of the same material as the dielectric layer 1 so that the terminal electrode layers 4 and 5 are exposed. . By forming such a connection portion 9, the insulation between the first and second terminal electrode layers 4, 5 having different polarities can be improved. When the connecting portion 9 made of the same material as the dielectric layer 1 is formed in this way, the capacitance forming region including the first electrode layer 2, the dielectric layer 1, and the second electrode layer 3 does not change at all. FIG.
In (a) and (b), the dielectric layer 1 and the connection layer 9 are indicated by hatched regions.

The first and second electrode layers 2 and 3 correspond to FIG.
As shown in (c) and (d), the three first electrode layers 2 are connected by the first terminal electrode layer 4, and the three second electrode layers 3 are also connected by the second terminal electrode layer 5. ing.
The first and second terminal electrode layers 4, 5 are formed at positions where their surfaces are exposed to the outside when the first and second electrode layers 2, 3 or the dielectric layer 1 are laminated.

The first and second electrode layers 2 and 3 do not need to be rectangular, but may be, for example, projecting portions slightly exposed from the dielectric layer 1 as shown in FIGS. 3 (e) and 3 (f). May be used. Such first and second
In the case of the electrode layers 2 and 3, for example, the first electrode layer 2 is formed using the first and second terminal electrode layers 4 and 5 as shown in FIG.
The second electrode layers 3 can be connected to each other.
Note that, in FIG. 3G, the second terminal electrode layer 5 is indicated by a hatched area.

In the thin film capacitor of the present invention, as shown in FIG. 2, the pitch Y (mm) between the first terminal electrode layer 4 and the second terminal electrode layer 5 is 1/10 <2 (n-1). / (2
73 × Y + 35). Note that the pitch Y (m
In the measurement of m), the distance between the centers of the first and second terminal electrodes exposed from the protective film 8 is shown. The shorter the pitch Y (mm) of the first and second terminal electrode layers 4 and 5 having different polarities, the shorter the current path and the smaller the inductance, but the first and second terminal electrodes having different polarities. As the pitch Y (mm) of the layers 4 and 5 becomes shorter, it becomes more difficult to secure insulation between the electrodes.

Here, the inductance L (d) (unit: pH), which is the denominator on the right side, is related to the distance d (unit: mm) through which the current flows between the conductors, and L (d) = 273 × d
+35 (L (d) indicates inductance (pH) and d indicates distance (mm)). This equation is an equation obtained from an experiment. The distance between terminals d (mm) is changed, and the obtained inductance is evaluated.
(Mm) and the relationship between the inductance L (pH) were investigated. FIG. 4 shows the results. From this figure, it can be seen that at least in such an experimental range, the distance between terminals and the inductance have a linear relationship, and the approximate expression L (d) = 27
3d + 35 (L (d) is inductance (pH), d
Indicates the distance (mm)).

The first and second intervals are defined on one side interval between the capacitance generation region A and the capacitance generation region B located at the center and on the other side between the capacitance generation region B and the capacitance generation region C located at the center.
Although the case where the terminal electrode layers 4 and 5 are formed in total of eight (n = 8) has been described, the number n (pieces) of the plurality of terminal electrode layers 4 and 5 between the capacitance generating regions A, B and C is as follows. 1/10 <2 (n-1) / (273 × Y + 35)
(Where Y represents the pitch (mm)).

As the number of the first and second terminal electrode layers 4 and 5 increases, the number of divisions of the current path increases and the inductance can be reduced, but the shape of the thin film capacitor increases.

As described above, the inductance of the capacitor element can be reduced by reducing the distance between the terminals or by increasing the number of terminals. However, each has a limit, and the desired inductance and other characteristics are reduced. In order to achieve this, it is necessary to consider these balances. The present invention facilitates consideration of this balance.
If 0 <2 (n−1) / (273 × Y + 35), the terminal pitch Y (mm), and the number of terminals n (number), a desired inductance can be obtained.

Next, FIG. 5 shows a structure having external terminals for facilitating connection between the first terminal electrode 4 and the second terminal electrode 5 of the thin film capacitor of the present invention and an external circuit.

A protective film is formed on the upper surfaces of, for example, eight first terminal electrode layers 4 connecting the first electrode layers 2 and the upper surfaces of eight second terminal electrode layers 5 connecting the second electrode layers 3. 8
External terminals 7 are respectively formed in portions exposed from the outside. In FIG. 5, for convenience, the second electrode layer 3 and the second
The external terminal 7 formed on the first terminal electrode layer 4 is shown in black, and the external terminal 7 formed on the second terminal electrode layer 5 is shown in white. FIG.
5B is a cross-sectional view taken along the line B ″ -B ″ in FIG. 5A, and FIG. 5C is a cross-sectional view taken along the line C ″ -C ″ in FIG. FIG.

When such external terminals 7 are formed,
It is better to apply the distance between the centers of the external terminals 7 as the distance Y (mm) between the first and second terminal electrode layers 4 and 5 because this reflects the actual situation.

The shape of the external terminal 7 is desirably the bump shape shown in FIG. 5, and in addition, there are a foil shape, a plate shape, a line shape, a paste shape, etc., and there is no particular limitation. Is also good. However, in order to sufficiently draw out the characteristics of a low-inductance thin-film capacitor, it is necessary to reduce the inductance of the external terminal 7 itself connected to an external circuit of the mounting board. A bump shape is desirable.

The material of the external terminal 7 is solder, P
There are b, Sn, Ag, Au, Cu, Pt, Al, Ni, and a conductive resin, and the like is not particularly limited, and a plurality of them may be combined.

The thickness of the dielectric layer 1 and the electrode layers 2 and 3 is 0.05 to 1 μm, and the size is 0.1 to 3 mm on one side. The thickness and size of each layer can be appropriately changed depending on the material and the application.

The substrate 6 used in the present invention is preferably made of alumina, sapphire, MgO single crystal, SrTiO ₃ single crystal, SiO ₂ coated silicon, glass, or the like. In particular, alumina, sapphire, and the like are preferable in consideration of low reactivity with a thin film, high strength, and crystallinity of a dielectric film or an electrode film.

Further, the first and second electrode layers 2 of the present invention,
3, the first and second terminal electrode layers 4 and 5 include gold (Au), platinum (Pt), palladium (Pd), copper (C
u), silver (Ag), titanium (Ti), chromium (Cr), and nickel (Ni) thin films. Among them, gold (Au), which has low reactivity with the dielectric and is hardly oxidized, A low copper (Cu) thin film is optimal. These may be used alone or in combination of two or more.

Further, the dielectric layer 1 may have a high dielectric constant in a high-frequency region, but its thickness is 1
μm or less is desirable. For example, as a metal element, Pb, M
It is preferable to use a dielectric thin film made of a perovskite-type composite oxide crystal containing g and Nb and having a relative dielectric constant of 1000 or more at a measurement frequency of 300 MHz (room temperature). Further, for example, a perovskite-type composite oxide crystal containing Ba and Ti, PZT, PLZT, SrTiO _3, Ta ₂ O _{5 and the} like may be used, and are not particularly limited.

Such a dielectric layer 1 is formed by PVD, CV
It is produced by a known method such as a method D or a sol-gel method.

The thin-film capacitor configured as described above has the first and second electrode layers 2 in the capacitance generating regions A, B, and C.
3 are connected by a plurality of first and second terminal electrode layers 4 and 5, respectively, the distance between the capacitance generation region A and the capacitance generation region B located at the center, and the capacitance generation region B and the capacitance generation region located at the center. C, the first terminal electrode layer 4
And the second terminal electrode layer 5 are provided alternately at a predetermined pitch Y (mm) in a total of n, and the first terminal electrode layers 4 provided on both sides of the capacitance generating region B are connected to each other. The distances Y (mm) between the first terminal electrode layer and the second terminal electrode layer and the number n (pieces) of the terminal electrode layers provided between the capacitance generating regions are substantially the same. /10<2(n-1)/(273.times.Y+35), so that the thin-film capacitor has characteristics suitable for applications such as external size, capacitance and insulation characteristics, and has extremely small inductance. Can be. Further, since the inductance of the thin film capacitor can be calculated using the above equation, a thin film capacitor having desired characteristics other than the inductance can be easily manufactured without repeating trial production.

Further, in the thin film capacitor of the present invention, since the external terminals 7 serving as contacts with the external circuit can be formed on the first and second terminal electrode layers 4, 5, respectively.
This means that the external terminals 7 of the positive and negative electrodes are exposed upward,
For example, the external terminals 7 can be mounted on the mounting board on which the electrodes and the wiring conductors are formed by joining the external terminals 7 to the electrodes and the wiring conductors, and the mounting on the board or the like becomes easy.

Next, the laminated thin film capacitor of the present invention will be described with reference to FIG. According to FIG. 6, the laminated thin film capacitor is obtained by further laminating a dielectric layer and an electrode layer on the single plate type thin film capacitor shown in FIG.

That is, in FIG. 6, on the upper surface of the substrate 6, the lower first electrode layer 2a corresponding to three regions from the bottom, the first dielectric layer 1a corresponding to three regions, and the lower first electrode layer 1a corresponding to three regions. 2 electrode layer 3
a, the second dielectric layer 1b for three regions, the upper first electrode layer 2b for three regions, the third dielectric layer 1c for three regions,
The second electrode layer 3b on the upper layer side of the region is sequentially formed by deposition. That is, each of the capacitance generation regions A, B, and C has a structure in which three capacitance components are connected in series in the thickness direction.

In the same manner as in FIG. 1, the first and second terminal electrode layers 4 are provided at respective intervals between the capacitance generating regions A, B, and C.
a, 4b, 5a, and 5b are respectively formed. For example, the lower first layer corresponding to each of the capacitance generation areas A, B, and C
The electrode layer 2a is connected to the lower first terminal electrode layer 4a at intervals between the capacitance generating regions A, B, and C. Also,
The lower second electrode layers 3a corresponding to the capacitance generating regions A, B, and C are connected by the lower second terminal electrode layers 5a at intervals of the capacitance generating regions A, B, and C. The upper first electrode layer 2b corresponding to each of the capacitance generating regions A, B, and C is connected to the upper first terminal electrode layer 4b at an interval between the capacitance generating regions A, B, and C. I have. In addition, the upper second electrode layer 3b corresponding to each of the capacitance generating regions A, B, and C
Is the distance between the capacitance generating areas A, B, and C,
They are connected by the terminal electrode layer 5b.

In addition, the first terminal electrode layer 4a on the lower layer and the first terminal electrode layer on the upper layer are located between the capacitance generating regions A, B, and C.
The terminal electrode layer 4b is laminated to form a first terminal electrode having a laminated structure. Further, at the intervals between the capacitance generating regions A, B and C, the lower second terminal electrode layer 5a and the upper second
The terminal electrode layer 5b is laminated to form a second terminal electrode having a laminated structure.

In this laminated thin-film capacitor, as in the case of the single-plate thin-film capacitor, the first terminal electrodes (the first terminal electrode layer 4a and the first terminal electrode layer 4a) are formed by laminating the first terminal electrode layers 4a and 4b. 4b for convenience).
And a second terminal electrode formed by laminating the second terminal electrode layers 5a and 5b (the combination of the second terminal electrode layers 5a and 5b is denoted by a reference numeral 5 for convenience) is the distance between the capacitance generating regions A, B and C. , And a total of n pieces are provided alternately at a predetermined pitch Y (mm),
In addition, the first terminal electrode layers 4 of the laminated structure provided at both sides of the capacitance generating region B on the center side are connected to the second terminal electrodes 4 of the laminated structure.
The terminal electrode layers 5 are provided substantially facing each other.

The protective film 8 is formed of the first and second layers of each laminated structure.
The terminal electrode layers 4 and 5 are exposed, and the capacitance generation areas A, B, and C are exposed.
Is formed so as to cover completely. The exposed portions of the first and second terminal electrodes 4 and 5 of each laminated structure are supplied with signals from an external circuit by forming external terminals. In FIG. 6, reference numerals 8a to 8d denote through portions exposing a part of the terminal electrodes 4 and 5 having a laminated structure. For example, the through portion 8a is formed between the capacitance generation region A and the capacitance generation region B located at the center. The through-hole 8b is provided to expose the second terminal electrode layer 5 of the laminated structure formed at an interval, and the first terminal of the laminated structure formed at the interval between the capacitance generating region A and the capacitance generating region B located at the center. The through-hole 8 c exposes the electrode layer 4, and exposes the second terminal electrode layer 5 having a laminated structure formed at a distance between the capacitance generation region B and the capacitance generation region C located at the center. The penetrating portion 8d exposes the first terminal electrode layer 4 having a laminated structure formed at a distance between the capacitance generation region B and the capacitance generation region C located at the center.

Such a thin film capacitor having a laminated structure is
It is formed on the upper surface of the substrate 6.

The laminated thin film capacitor also has a pitch Y between the first terminal electrode layer and the second terminal electrode layer, just like the single plate type thin film capacitor shown in FIGS. 1, 2, 3, and 5. (Mm) and the number n (number) of terminal electrode layers provided between the capacitance generating regions are in the range of 1/10 <2 (n-1) / (273 × Y + 35), so that the external size of the thin film capacitor is In addition, it has characteristics suitable for applications such as capacitance and insulation characteristics, and can extremely reduce inductance. Further, since the inductance of the thin film capacitor can be calculated using the above equation, a thin film capacitor having desired characteristics other than the inductance can be easily manufactured without repeating trial production. Further, since the external terminals 7 can be formed from the penetrating portions 8a to 8b of the protective film 8, mounting is facilitated. The external terminals 7 are substantially the first terminal electrode layers 4b on the upper layer side of the first terminal electrode layers 4 having a laminated structure.
It is formed on the first terminal electrode layer 5b on the upper layer side of the second terminal electrode layer 5 having a laminated structure.

Further, since the first and second electrode layers 2 and 3 and the dielectric layer 1 are alternately laminated, a high capacity is obtained. As an example of the multilayer capacitor, an example of a three-layer dielectric has been described, but it is not particularly limited.

Further, since the dielectric layer 1 does not exist directly below the first and second terminal electrode layers 4 and 5 of the laminated structure, the dielectric layers 1a to 1c due to thermal stress when external terminals are formed or mounted.
Can be prevented from being damaged.

The first and second electrode layers 2 and 3 are shown as examples of a laminated thin film capacitor using the examples of FIGS. 3C and 3D, but are shown in FIGS. 3E and 3F. The first and second electrode layers 2 and 3 having such protrusions may be used. In this case, after the electrode layers 2 and 3 and the dielectric layer 1 are sequentially laminated, the terminal electrode layers 4 and 5 are formed as shown in FIG. 2
The electrode layers can be connected to each other.

The thin-film capacitor of the present invention is generally used by being formed on the surface of the substrate 6 as described above, but it can also be used by being built in a multilayer-structured substrate.

When a multilayer thin film capacitor is incorporated in a substrate, the terminal electrode layers are connected to each other by, for example, through-hole conductors formed in the substrate, and external terminals are also formed by through-hole conductors. Thus, conduction of each electrode layer can be secured, and the capacitance is taken out.

Although an example has been described in which the shape of the electrode layers 2 and 3 is rectangular, any shape such as a square or a circle may be used.

[0061]

EXAMPLES (Example 1) An electrode layer, a terminal electrode layer and a dielectric layer were all formed by a high-frequency magnetron sputtering method. A in the process chamber as a sputtering gas
r gas was introduced, and the pressure was maintained at 6.7 Pa by evacuation.

First, a Ti target was sputtered on an alumina sintered body substrate having a thickness of 0.25 mm, and then an Au target was sputtered. Next, the first electrode layers 2 were patterned into electrode layers connected by the first terminal electrode layers 4 as shown in FIG.

Next, the target was (Ba _0.5 Sr _0.5 ) T
iO ₃ sintered body, substrate temperature 600 ° C, high frequency power 4
Under a condition of 00 W, a dielectric layer having a thickness of 0.2 μm was formed. Then, the dielectric layer was patterned into a dielectric layer 1 as shown in FIG. 3A by using a photolithography technique.

Next, sputtering of an Au target is performed, and subsequently, using photolithography technology, the second electrode layers 3 are connected to the electrode layers connected by the second terminal electrode layers 5 as shown in FIG. Pattern processed. Next, in order to improve the connection state of the solder bumps, a Ni target is sputtered, and then a new terminal electrode layer is formed by sputtering an Au target, and as shown in FIG. Processed into a unique pattern. Thereafter, a photosensitive BCB was applied, exposed, and developed to form a protective film 8 having a through hole with a diameter of 80 μm so that a part of the terminal electrode was exposed.

Solder bumps were formed on the terminal electrode layers of the manufactured single-plate type thin film capacitor, and a thin film capacitor as shown in FIG. 5 was manufactured and mounted on an evaluation board. The prepared thin film capacitor has a solder bump interval Y = 0.2
5 mm and n = 8, which is designated as Sample 1. For the evaluation, the impedance characteristics at 1 MHz to 1.8 GHz were measured using an impedance analyzer (HP4291A, manufactured by Agilent Technologies).

In the same process as in Sample 1, a sample was prepared in which the distance between the solder bumps (substantially the pitch Y (mm), the number n (number) of solder bumps between the capacitance generating regions, and the number of stacked layers) were changed. The obtained characteristics were compared with the inductance calculated from 1 / L = 2 (n-1) / (273 × Y + 35).
Shown in

[0067]

[Table 1]

In Table 1, the mark * is out of the scope of the present invention and is a comparative example. It can be seen that L1 (experimental value) and L2 (calculated value) in the samples 1 to 4 of the present invention and the samples 5 to 9 of the comparative examples are in good agreement within a range of ± 10%. Example 2 A substrate material, an electrode material, an electrode forming method, a shape, and dimensions were exactly the same as those of the sample 1 of Example 1, and only a dielectric layer was formed by a sol-gel method in the following procedure.

Pb (Mg _1/3 N) synthesized by the sol-gel method
b _2/3 ) O ₃ —PbTiO ₃ —PbZrO ₃ coating solution is applied by spin coating, dried, heat-treated at 380 ° C., baked at 815 ° C., and Pb (Mg _1/3 N
b _2/3 ) O ₃ —PbTiO ₃ —PbZrO ₃ dielectric layer was formed. Photolithography technology was used for pattern processing as in Example 1.

The manufactured thin film capacitor was evaluated in the same manner as in Example 1. As a result, the capacitance component was 28 nF and the inductance component was 5 pH. The inductance component has a value equivalent to that of the sample 1 of Example 1, and it can be seen that the same result can be obtained even if the method of forming the dielectric layer and the dielectric material are changed.

[0071]

According to the present invention, the pitch Y (mm) between the different terminal electrode layers, which are parameters for reducing the inductance of the thin film capacitor, and the terminal electrodes provided on one side of the capacitance generating region located at the center. The number n of
Since the relationship between (unit) and the inductance was found, a low-inductance thin-film capacitor having desired characteristics can be easily manufactured.

Further, in the thin film capacitor of the present invention, the dielectric layer and the electrode layer can be easily laminated, and external terminals used for contact with the outside can be formed on the terminal electrode layer where the dielectric layer is not formed. With the structure, it is not necessary to consider the damage to the capacitance generating region due to the thermal stress generated when the external terminals are formed, and the mounting becomes easy.

By forming such a thin film capacitor on the surface or inside of the substrate, a low inductance capacitor substrate can be easily formed.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view showing a single-plate type thin film capacitor of the present invention.

2A is a plan view of FIG. 1, and FIG. 2B is B ′ of FIG.
FIG. 3C is a cross-sectional view along the line B ′, and FIG. 3C is a cross-sectional view along the line C′-C ′ in FIG.

3A is a diagram illustrating a dielectric layer, FIG. 3B is a diagram illustrating a structure in which dielectric layers are connected to each other at a connection portion, FIG. Is the second electrode layer
(E) a first electrode layer having a protrusion, (f) a second electrode layer having a protrusion,
(G) is a plan view showing first and second terminal electrode layers.

FIG. 4 is a characteristic diagram illustrating a relationship between a distance between terminals and an inductance.

5A is a plan view showing a single-plate type thin film capacitor having an external terminal according to the present invention, and FIG.
FIG. 3C is a cross-sectional view along the line B ″, and FIG. 3C is a cross-sectional view along the line C ″ -C ″ in FIG.

FIG. 6 is an exploded perspective view showing a multilayer thin film capacitor of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Dielectric layer 2, 2a, 2b ... 1st electrode layer 3, 3a, 3b ... 2nd electrode layer 4, 4a, 4b ... 1st terminal electrode layer 5, 5a, 5b ... ..Second terminal electrode layer 6 ... Substrate 7 ... External terminal 8 ... Protective film A, B, C ... Capacity generation region

Claims (5)

[Claims] A first electrode layer is formed on a lower surface of a dielectric layer and a second electrode layer is formed on an upper surface of the dielectric layer.
A plurality of first terminal electrode layers for connecting the first electrode layers to each other between the capacitance generating regions, wherein three capacitance generating regions formed by forming the electrode layers are juxtaposed at predetermined intervals; A plurality of second terminal electrode layers for connecting the second electrode layers are alternately provided at predetermined intervals, and the first terminal electrodes provided at one side interval of the centrally located capacitance generation region The first layer provided at an interval from the layer to the other side;
A terminal electrode layer substantially opposed to the second electrode layer, and the second electrode electrode layer is provided at one side interval of the capacitance generating region located at the center.
In a thin film capacitor provided with a terminal electrode layer and the second terminal electrode layer provided at an interval on the other side substantially opposed to each other, the first adjacent ones at an interval on one side of the capacitance generating region located at the center are provided. When the pitch Y (mm) between the terminal electrode layers and the second terminal electrode layers, and the total number n (pieces) of the first terminal electrode layers and the second terminal electrode layers, 1/10 <2 (n-1) / (273 × Y + 35). 2. A capacitor generating region in which a plurality of dielectric layers and a plurality of electrode layers are alternately laminated, and the electrode layers alternately form a first electrode layer or a second electrode layer from below at a predetermined interval. A plurality of first terminal electrode layers connecting the first electrode layers and a plurality of second terminals connecting the second electrode layers between each of the capacitance generating regions. A plurality of electrode layers are alternately provided at predetermined intervals, and the first terminal electrode layer provided at one side of the capacitance generating region located at the center and the first terminal electrode provided at the other side of the capacitance generating region are provided at the other side.
A terminal electrode layer substantially opposed to the second electrode layer, and the second electrode electrode layer is provided at one side interval of the capacitance generating region located at the center.
In a thin-film capacitor in which a terminal electrode layer and the second terminal electrode layer provided on the other side are substantially opposed to each other, the first terminals adjacent to each other at one side of the center of the capacitance generating region are provided. When the pitch Y (mm) between the electrode layer and the second terminal electrode layer and the total number n (pieces) of the first terminal electrode layer and the second terminal electrode layer are 1/10 <2 (n-1) / A thin film capacitor satisfying the following range: (273 × Y + 35). 3. The thin film capacitor according to claim 1, wherein an external terminal is provided on the first terminal electrode layer and the second terminal electrode layer. 4. The thin film capacitor according to claim 3, wherein the shape of the external terminal is a bump shape. 5. A capacitor substrate comprising the thin film capacitor according to claim 1 provided on a surface and / or inside of a substrate.