JP3500277B2 - Multilayer capacitors and capacitors - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor and a capacitor, for example, a large-capacity capacitor that is provided in an electric circuit that operates at high speed and is used for bypassing high frequency noise or for preventing fluctuations in power supply voltage. The present invention relates to a low inductance multilayer capacitor and a capacitor.

[0002]

2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there have been strong demands for electronic parts installed in the electronic devices to be smaller, thinner, and compatible with high frequencies.

Particularly in a high-speed digital circuit of a computer that needs to process a large amount of information at high speed, even at the personal computer level, the clock frequency in the CPU chip is 100 MHz to several hundred MHz, and the clock frequency of the inter-chip bus is 30 MHz. The high speed of 75 MHz is remarkable.

Further, as the degree of integration of LSIs increases and the number of elements in a chip increases, the power supply voltage tends to decrease in order to suppress power consumption. As the speed, density, and voltage of these IC circuits have increased, it has become essential for passive components such as capacitors to exhibit excellent characteristics with respect to high frequency or high speed pulses, as well as with smaller size and larger capacity. There is.

In order to make the capacitor small in size and high in capacity, it is most effective to make the dielectric material sandwiched between the pair of electrodes thin and thin. The thin film also conforms to the above-mentioned tendency of voltage decrease.

On the other hand, various problems associated with high-speed operation of IC circuits are more serious than miniaturization of each element. Of these, the most important factor in the function of removing high-frequency noise, which is the role of the capacitor, is the instantaneous decrease in the power supply voltage that occurs when simultaneous switching of logic circuits occurs simultaneously. It is a function to reduce by supplying to. This is a so-called decoupling capacitor.

The performance required of the decoupling capacitor lies in how quickly the current can be supplied to the current fluctuation in the load section faster than the clock frequency. Therefore, it must function reliably as a capacitor in the frequency range from 100 MHz to 1 GHz.

However, the actual capacitor element has a resistance component and an inductance component in addition to the capacitance component. The impedance of the capacitive component decreases with increasing frequency,
The inductance component increases as the frequency increases.
Therefore, as the operating frequency becomes higher, the transient current that should be supplied by the inductance of the element is limited, and the power supply voltage on the logic circuit side is momentarily lowered or new voltage noise is generated. As a result, it causes an error on the logic circuit.

Particularly in recent LSIs, the power supply voltage is lowered in order to suppress an increase in power consumption due to an increase in the total number of elements.
The allowable fluctuation range of the power supply voltage is also small. Therefore, it is very important to reduce the inductance of the decoupling capacitor element itself in order to minimize the voltage fluctuation width during high speed operation.

There are three ways to reduce the inductance. The first is to minimize the length of the current path, the second is to make the current path into a loop structure to minimize the loop cross-sectional area, and the third is to divide the current path into n pieces to reduce the effective inductance to 1 / N.

The first method may be achieved by increasing the capacitance per unit area to reduce the size, and can be achieved by thinning the capacitor element. For the purpose of obtaining a capacitor having a large capacity and good high frequency characteristics, Japanese Patent Application Laid-Open No. 60-94716 discloses a thin film having a dielectric thickness of 1 μm or less.

The second method has the effect of offsetting and reducing the magnetic field formed by one current path by the magnetic field formed by another current path in the vicinity thereof. Therefore, a pair of electrode plates or electrodes forming a capacitor are used. The directions of the currents flowing through the layers may be set so as not to be the same.

In the third method, the inductance can be reduced by connecting the divided capacitors in parallel.
As such a capacitor, Japanese Patent Laid-Open No. 4-211191
Japanese Patent Laid-Open Publication No. 1994-242242 discloses a device using a thin film dielectric layer.

[0014]

However, when considering a decoupling capacitor that can be mounted at a desired location, the size that can be handled is 0.5 mm × 0.5.
It is necessary to have a thickness of about mm or more, and there is a limit in reducing the inductance only by the first thin film and the downsizing method.

In the second method, the positive and negative terminal electrodes need to be in the same end face or in the orthogonal direction, which is disadvantageous in mounting.

The third division parallel connection method is an advantageous means for a board built-in type, but has no degree of freedom in mounting. Further, although a normal multilayer capacitor is also connected in parallel, since the directions of the currents are the same, the magnetic fields formed by the electrode currents are superimposed. That is, the mutual inductance becomes large, so that the effective total inductance cannot be sufficiently reduced. Therefore, it was necessary to adopt the second means together, but as described above, there was a mounting problem due to the problem of the terminal electrode.

An object of the present invention is to provide a multilayer capacitor and a capacitor having a low inductance structure that is easy to mount and easy to stack.

[0018]

A multilayer capacitor of the present invention comprises a dielectric layer and a pair of electrode layers which are alternately laminated, wherein the electrode layers are alternately arranged from the bottom to the first electrode layer or the first electrode layer. Two
The first capacitance section serving as an electrode layer and the second capacitance section having the electrode layer alternately serving as the second electrode layer or the first electrode layer are arranged in parallel from the lower side, and the first capacitance section and the said first electrode layer and between the second electrode layer to each other of the second capacitor portion, before
Formed on the first electrode layer and the second electrode layer, respectively.
And a protrusion existing between the first capacitance portion and the second capacitance portion.
Section and a conductor formed in the stacking direction on the dielectric layer that connects the protruding section,
An external terminal electrode on the uppermost electrode layer and on the capacitance section.
Is formed .

The capacitor of the present invention is formed by arranging a plurality of the above-mentioned multilayer capacitors, and the uppermost first electrode layers and the uppermost second electrode layers are external terminals.
The electrodes are electrically connected to each other.

[0020]

In the multilayer capacitor of the present invention, the pair of capacitance portions are arranged in parallel at a predetermined interval, and the pair of capacitance portions have the first electrode layer (for example, the positive electrode layer) in the same plane. And the second electrode layer (for example, the negative electrode layer) is formed, and since the positive electrode layer and the negative electrode layer can be formed close to each other, the current path becomes short,
The inductance can be reduced.

Further, since the directions of the currents flowing through the positive electrode layer and the negative electrode layer of the individual capacitance portions are opposite to each other, the generated inductances can be canceled out and reduced.

Furthermore, since the first electrode layers can be connected to each other and the second electrode layers can be connected to each other by the conductors formed in the dielectric layers in the stacking direction, the stacking can be facilitated.

The capacitor of the present invention is an assembly of a plurality of the above multilayer capacitors, and electrically connects the uppermost first electrode layers and the uppermost second electrode layers of the respective multilayer capacitors. By doing so, the multilayer capacitors are electrically connected in parallel, whereby the current paths are distributed to n pieces, and the effective inductance can be further reduced by 1 / n.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION As shown in FIGS. 1 to 3, a multilayer capacitor of the present invention has a positive electrode layer 2 (first electrode layer) and a negative electrode layer 3 (first electrode layer) on the upper surface of a dielectric layer 1. 2 electrode layers) are formed, and 6 such dielectric layers 1 are laminated. That is, the dielectric layer 1 and the pair of electrode layers 2,
3 and 3 are alternately laminated.

Then, on the upper surface of the lowermost dielectric layer 1,
A positive electrode layer 2 is formed on the left side in FIG. 1 and a negative electrode layer 3 is formed on the right side so as to face each other. On the upper surface of the second dielectric layer 1 from the bottom, the negative electrode layer 3 is on the left side and the right side is on the right side in FIG. Positive electrode layer 2
Are formed to face each other, and similarly, the third dielectric layer 1 from the bottom is formed.
Has the same electrode layers 2 and 3 as the first layer from the bottom, the fourth dielectric layer 1 from the bottom has the same electrode layers 2 and 3 as the second layer from the bottom, and the fifth layer from the bottom. Electrode layers 1 and 2 similar to the first layer from the bottom are formed on the first dielectric layer 1, and electrode layers 2 and 3 similar to the second layer from the bottom are formed on the uppermost dielectric layer 1. .

That is, on the left side in FIG. 1, the capacitor portion A in which the positive electrode layers 2 or the negative electrode layers 3 are alternately formed from the bottom is formed, and on the right side, the negative electrode layers 3 or the positive electrodes are alternately formed from the bottom. Capacitance portion B in which layer 2 is formed is formed. The positive electrode layer 2 and the negative electrode layer 3 of the pair of capacitance units A and B have an electrode structure in which a protrusion 4 that protrudes toward the capacitance units A and B facing each other is formed.

In the dielectric layer 1, as shown in FIG. 3, conductors 5 connecting the electrode layers 2 and 3 of the same polarity in the pair of capacitance portions A and B are formed in the stacking direction. . The conductor 5 connects the protruding portions 4 of the electrode layers 2 and 3.

The protrusions 4 formed on the positive electrode layer 2 and the protrusions 4 formed on the negative electrode layer 3 are separated by a predetermined distance so as not to be electrically connected.

The thickness of the dielectric layer 1 is 1 to 10 μm,
The thickness of the electrode layers 2 and 3 is 0.5 to 2 μm, and the size is 0.
The width is 2 to 1.5 mm and the width is 1.5 to 0.2 mm.

In mounting the multilayer capacitor of the present invention, for example, bumps are formed as external terminal electrodes on the positive electrode layer 2 and the negative electrode layer 3 formed on the outermost layer surfaces of the capacitance parts A and B, It may be flip-chip mountable. The mounting structure in this case is such that the bumps of the multilayer capacitor of the present invention are arranged on the wiring pattern for input / output of the substrate (board),
It is mounted by heating.

The external terminal electrode may be anywhere such as the protruding portion 4 and other portions as long as it is the positive electrode layer 2 and the negative electrode layer 3 formed on the outermost layer surface.

The capacitor of the present invention is an array of a plurality of the above-mentioned laminated capacitors, and includes the positive electrode layer 2 and the negative electrode layer 3 formed on the outermost layer surfaces of the pair of capacitance portions A and B. An external terminal electrode such as solder is formed on the top of the external terminal electrode, and is connected in parallel to the capacitance parts A and B of another multilayer capacitor via these. The connection can be made, for example, by connecting a lead wire or the like to the external terminal electrode, or by disposing a plate material made of a conductive material on the external terminal electrode.

The external terminal electrodes when a plurality of multilayer capacitors are electrically connected in parallel are shaped like bumps.
There are foil shapes, plate shapes, linear shapes and the like, and there is no particular limitation, and a plurality of shapes may be combined. The material is solder, Pb, Sn, Au, Cu, Pt, Pd, Ag, A.
l, Ni, etc., and any conductive material may be used, and a plurality of materials may be combined.

Further, similarly to the above multilayer capacitor, bumps may be formed as external terminal electrodes to enable flip chip mounting. The mounting structure in this case is mounted by arranging the bumps of the capacitor of the present invention on a substrate (board) on which a wiring pattern for connecting a plurality of multilayer capacitors in parallel is formed and heating.

The dielectric layer 1 used in the present invention may be any one having a high dielectric constant in a high frequency region. For example, a perovskite type complex oxide crystal containing Ba and Ti, and a perovskite type oxide containing Pb. Crystal (PZ
T, PMN, PLZT, etc.), SrTiO ₃ , T
It may be a ₂ O ₅ or the like, or may be a compound obtained by adding or substituting another metal element thereto, and is not particularly limited. Also, the manufacturing method is not particularly limited.

The electrode layers 2 and 3 of the present invention are made of Ni, P
d, Cu, Ag, Al, Ti, Pt, Au, etc.,
These are formed by a known technique such as screen printing or sputtering. These may be used alone or in combination of two or more.

The conductor 5 for electrically connecting the electrode layers 2 and 3 of the same polarity is formed by forming a through hole in the dielectric layer 1 and filling the through hole with a conductor paste. As the method of processing the through-hole formed in 1, there are hole processing using a processing tool such as a micro drill, and hole processing and pattern processing using photolithography, which can be processed within desired dimensional tolerances. If there is,
It is not particularly limited.

The conductor 5 filling the through-holes is made of Ni, Pd, Cu, Ag, Al, Ti, P as in the electrode layers 2 and 3.
There are t, Au, etc., and these may be used alone or in combination of two or more. Also, different materials may be used as long as electrical connection with the electrode layers 2 and 3 can be secured.

In the multilayer capacitor constructed as described above, since the pair of capacitance portions A and B are formed so as to face each other, the pair of capacitance portions A and B are formed in the same plane on the positive electrode layer 2.
Since the negative electrode layer 3 and the negative electrode layer 3 are formed at a predetermined interval, and the positive electrode layer 2 and the negative electrode layer 3 can be formed close to each other, the current path is shortened and the inductance is reduced. Can be made smaller.

Further, since the directions of the currents flowing through the positive electrode layer 2 and the negative electrode layer 3 in the individual capacitor portions A and B are opposite to each other, the inductances in the positive electrode layer 2 and the negative electrode layer 3 cancel each other out, The generated inductance can be reduced.

Further, by arranging a plurality of the multilayer capacitors of the present invention and electrically connecting them in parallel, the current path is distributed to n, and the effective inductance is further reduced to 1.
/ N times can be reduced.

Further, since the external terminal electrodes used for contact with the outside can be formed on the uppermost electrode layers 2 and 3, the mounting becomes easy. A plurality of multilayer capacitors as shown in FIG. 1 may be arranged, or a plurality of multilayer capacitors of the present invention may be incorporated in the same substrate as shown in FIG. In FIG. 6, a plate material 10 made of a conductive material is arranged on the external terminal electrodes of the uppermost electrode layers 2 and 3, and two multilayer capacitors are built in and connected in parallel.

Although an example in which the electrode layers 2 and 3 have a rectangular shape has been described, any shape such as a square shape or a circular shape may be used.

[0044]

【Example】

Example 1 A dielectric powder containing barium titanate as a main component, and 1 mol part of yttrium oxide, 2 mol parts of magnesium oxide and 0.1 mol part of manganese oxide was added to 100 mol parts of the main component, Water and a dispersant were added, and the mixture was pulverized with a ball mill using ZrO ₂ balls, and then the organic binder was mixed, and the obtained slurry was formed into a tape having a thickness of 8 μm.

On the other hand, as an internal electrode, a paste prepared by adding an organic plasticizer to nickel powder was prepared, and an electrode layer having a pattern as shown in FIG. 4 (a) was formed on the tape by screen printing. Next, after a tape having a thickness of 8 μm was laminated on the upper portion, an electrode layer having a pattern as shown in FIG. 4B was formed by a screen printing method. Tape molding and formation of electrode layers having different patterns were alternately repeated to obtain a molded body.

Next, via processing was performed on the protruding portion of the electrode layer of the obtained molded body by using a microdrill. The via paste was filled with the above nickel paste by screen printing to connect the electrode layers having the same polarity.

After that, the molded body obtained was cut, then baked at an oxygen partial pressure of 1 × 10 ⁻⁶ Pa and a temperature of 1260 ° C. for 2 hours, and then heat-treated at 1 × 10 Pa and a temperature of 1000 ° C. for 1 hour. It was Next, a coating layer made of Pt was formed on the via conductor of the sintered body by using a sputtering method, and the dielectric thickness was 9 μm.
m, the number of effective dielectric layers is 20, the outer dimensions are 1.6 mm × 0.
8 mm x 0.5 mm, effective electrode area 0.7 (0.5 mm
A multilayer capacitor having a size of × 0.7 mm × 2) mm ² was obtained.

Next, a diameter of 0.2 was formed on the Pt coating layer.
Solder bumps were formed using mm solder balls, external terminal electrodes were formed, and a multilayer capacitor capable of flip-chip mounting was obtained.

Next, from 1 MHz to 1.8 of these samples.
Impedance analyzer for impedance characteristics at GHz (HP4291A manufactured by Hewlett Packard)
As a result of measurement using, the capacitance at a measurement frequency of 1 MHz is 100 nF, the resonance frequency is 50 MHz, the equivalent series resistance is 10 mΩ, and the equivalent series inductance is 100 pH.
It can be seen that a multilayer capacitor having a large capacitance and a small inductance can be manufactured.

Example 2 First, water and a dispersant were added to a dielectric powder containing lead magnesium niobate as a main component, and 10 parts by mole of lead titanate was added to 100 parts by weight of the main component. ZrO
After mixing and pulverizing with a ball mill using ₂ balls, an organic binder was added and mixed, and the obtained slurry was formed to a thickness of 8 μm.
m was formed into a tape shape.

On the other hand, as the internal electrode, a commercially available Ag-Pd is used.
A paste was prepared, and an electrode layer having a pattern as shown in FIG. 4A was formed on the tape by a screen printing method. Next, after a tape having a thickness of 8 μm was laminated on the upper portion, an electrode layer having a pattern as shown in FIG. 4B was formed by a screen printing method. Tape molding and formation of internal electrode layers having different patterns were alternately repeated to obtain a molded body.

Next, via processing was performed using a microdrill on the protruding portion of the electrode layer of the obtained molded body. The above-mentioned Ag-Pd paste was filled in this via by screen printing to connect the electrode layers.

After cutting the obtained molded body, it was baked in the atmosphere at a temperature of 1000 ° C. for 2 hours.

After that, a coating layer made of Pt is formed on the via conductor of the sintered body by a sputtering method, the dielectric thickness is 9 μm, the number of effective dielectric layers is 8 layers, and the outer dimension is 1.6 mm ×.
0.8mm × 0.4mm, effective electrode area 0.7 (0.5
A multilayer capacitor having a size of mm × 0.7 mm × 2) mm ² was obtained.

Thereafter, solder balls having a diameter of 0.2 mm were used to form solder bumps on the coating layer made of Pt, external terminal electrodes were formed, and thus a flip-chip mountable multilayer capacitor was obtained.

Next, from 1 MHz to 1.8 of these samples.
Impedance analyzer for impedance characteristics at GHz (HP4291A manufactured by Hewlett Packard)
As a result of measurement using, the capacitance at a measurement frequency of 1 MHz is 100 nF, the resonance frequency is 50 MHz, the equivalent series resistance is 10 mΩ, and the equivalent series inductance is 100 pH.
It can be seen that a multilayer capacitor having a large capacitance and a small inductance can be manufactured.

Example 3 Pt formed by the same method as in Example 1 except that the patterns of FIGS. 5 (a) and 5 (b) were used alternately for the electrode layers, and the outermost layer was formed by sputtering. A coating layer consisting of 9 μm of dielectric thickness, 23 effective dielectric layers, external dimensions of 1.6 mm × 0.8 mm × 0.5 mm, effective electrode area of 0.6 (0.5 mm × 0.3 mm × A 2 × 2) mm ² capacitor was obtained.

Thereafter, an external terminal electrode composed of a solder bump is formed on the Pt coating layer by using a solder ball having a diameter of 0.2 mm, and a plate material composed of a conductive material is arranged on the external terminal electrode, and the same polarity is provided. By connecting the electrode layers with each other, a capacitor was obtained.

As a result of measuring the impedance characteristics of the same in the same manner as in Example 1, the capacitance at a measurement frequency of 1 MHz was 100 nF, the resonance frequency was 68 MHz, the equivalent series resistance was 6 mΩ, and the equivalent series inductance was 55 pH. It can be seen that the equivalent series resistance and the equivalent series inductance are reduced to about 1/2 by connecting them in parallel.

[0060]

In the multilayer capacitor of the present invention, since the first electrode layer (positive electrode layer) and the second electrode layer (negative electrode layer) are formed in the same plane, these positive electrode layer and negative electrode layer The electrode layers can be formed close to each other, the current path can be shortened, and the inductance can be reduced. Further, by connecting a plurality of the multilayer capacitors of the present invention in parallel, the current paths are distributed to n, so that the effective inductance can be further reduced by 1 / n. Moreover, since the respective electrode layers can be connected to each other through the conductors of the dielectric layers sandwiched by the electrode layers, the lamination becomes easy. Furthermore, since the external terminal electrodes used for contact with the outside can be formed on the uppermost electrode layer, mounting becomes easy. Therefore, according to the present invention, it is possible to provide a low inductance multilayer capacitor which is easy to stack and mount.

[Brief description of drawings]

FIG. 1 is an exploded perspective view showing a multilayer capacitor of the present invention.

FIG. 2 is a plan view of FIG.

3A is a sectional view taken along line XX of FIG. 2, and FIG.
FIG. 3 is a sectional view taken along the line YY of FIG.

FIG. 4 is a plan view showing an electrode pattern of a multilayer capacitor.

FIG. 5 is a plan view showing an electrode pattern of a capacitor.

FIG. 6 is a plan view showing a capacitor including a plurality of laminated capacitors.

[Explanation of symbols]

1 ... Dielectric layer 2 ... Positive electrode layer (first electrode layer) 3 ... Negative electrode layer (second electrode layer) 4 ... Projection 5 ... conductor 10 ... Plate material made of conductive material A, B ... Capacity part

Claims (2)

(57) [Claims] 1. A first capacitor portion comprising dielectric layers and a pair of electrode layers which are alternately laminated, wherein the electrode layers are alternately arranged as a first electrode layer or a second electrode layer from the lower side, The electrode layers are alternately arranged from the bottom side with the second capacitance portions that are the second electrode layers or the first electrode layers, and the first capacitance portions and the second capacitance portions are arranged side by side.
Forming the first electrode layers and the second electrode layers of the capacitor section into the first electrode layer and the second electrode layer, respectively.
Exists between the first capacitance portion and the second capacitance portion formed.
That the projecting portion, and each connected by a conductor formed in said lamination direction in the dielectric layer for connecting the protruding portion, the volume
An outer end on the uppermost electrode layer of the quantity part and on the capacitance part
A multilayer capacitor, which is formed by forming a child electrode . 2. A plurality of multilayer capacitors according to claim 1 are arranged, and the uppermost first electrode layers and the uppermost second electrode layers are electrically connected to each other via external terminal electrodes. A capacitor characterized by being connected.