JPH1032286A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1032286A
JPH1032286A JP8187467A JP18746796A JPH1032286A JP H1032286 A JPH1032286 A JP H1032286A JP 8187467 A JP8187467 A JP 8187467A JP 18746796 A JP18746796 A JP 18746796A JP H1032286 A JPH1032286 A JP H1032286A
Authority
JP
Japan
Prior art keywords
tape
lead
chip
semiconductor chip
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8187467A
Other languages
Japanese (ja)
Inventor
Seigo Ito
誠悟 伊藤
Osatake Yamagata
修武 山方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP8187467A priority Critical patent/JPH1032286A/en
Publication of JPH1032286A publication Critical patent/JPH1032286A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To apply a pressure uniformly onto a tape with a tool to uniformly bring the tape into close contact with a chip so as to keep the chip free from a bonding failure and high in reliability by a method wherein plating is performed corresponding to all the area of a lead where the tape is stuck. SOLUTION: Bonding pads 9 formed in rectilinear rows are provided onto a semiconductor chip 1, and a plating layer 4 equal to or larger than the adhesive area of a tape bonded to the underside of a lead 3 is provided to the upside of the lead 3. An adhesive tape 2 is stuck to the semiconductor chip 1 in the direction in which the bonding pads 9 are arranged, and the leads 3 are laid on the tape 2. Then, the lead 3 is pressed against the adhesive tape 2 by a tool to bond the tape 2 to the chip 1. The plating layer 4 is present on the tape 2 through the intermediary of the lead 3, so that a force applied by the tool is uniformly applied to the tape 2, and the lead 3, the tape 2, and the chip 1 are uniformly bonded together.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、リードフレームに
半導体素子を搭載し、互いをワイヤで接続し、それらを
一体的に樹脂封止した半導体装置に関し、特にＬＯＣ
（Lead On Chip）技術を用いた半導体装置に係わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element is mounted on a lead frame, connected to each other by wires, and they are integrally sealed with a resin.
The present invention relates to a semiconductor device using (Lead On Chip) technology.

【０００２】[0002]

【従来の技術】近年、半導体メモリ製品に対して小型
化、高密度化の要求が高まっており、チップが大きくな
る傾向にあり、その一方でパッケージは小さいままにし
なければならない必要がある。この要求に対応するた
め、ＬＯＣ（Lead On Chip）と呼ばれるパッケージング
技術が用いられるようになっている。このＬＯＣ技術
は、パッケージにできるだけ大きなチップを封止しよう
とするものである。2. Description of the Related Art In recent years, demands for miniaturization and high-density of semiconductor memory products have increased, and chips have tended to be large, while packages have to be kept small. To meet this demand, a packaging technique called LOC (Lead On Chip) has been used. This LOC technique is to seal a chip as large as possible in a package.

【０００３】図４は、ＬＯＣ技術で形成された半導体装
置を示す。まず、リード３の上面にワイヤボンディング
ためのメッキ４を施す。続いて、リード３の下面にテー
プ２を張り付ける。その後、図５に示すように、ステー
ジ８上に半導体チップ１を載せ、半導体チップ１上に上
述のリード３をテープ２側がチップ１側になるように載
せる。次に、リード３上にツール７を押しつけることに
より、テープ２とチップ１とを接着させる。その後、リ
ード３上のメッキ４とチップ１の間をワイヤ５で接続す
る。続いて、樹脂６によりチップ１、リード３及びワイ
ヤ５を封止し、半導体素子のパッケージングが終了す
る。FIG. 4 shows a semiconductor device formed by the LOC technology. First, plating 4 for wire bonding is applied to the upper surface of the lead 3. Subsequently, the tape 2 is attached to the lower surface of the lead 3. Thereafter, as shown in FIG. 5, the semiconductor chip 1 is mounted on the stage 8, and the above-described leads 3 are mounted on the semiconductor chip 1 such that the tape 2 side is on the chip 1 side. Next, the tape 2 and the chip 1 are bonded by pressing the tool 7 on the lead 3. After that, the plating 5 on the lead 3 and the chip 1 are connected by the wire 5. Subsequently, the chip 1, the leads 3, and the wires 5 are sealed with the resin 6, and the packaging of the semiconductor element is completed.

【０００４】[0004]

【発明が解決しようとする課題】上述のようにリードフ
レームの表面の一部は、通常、ワイヤボンディングのた
めにメッキが施されている。ボンディングに必要な領域
だけにメッキを施すと、リード３の上下にメッキ４とテ
ープ２がある部分と、テープ２は貼られているがメッキ
４がない部分が生じる。メッキの有無によりリード３上
に段差が生じていることから、図４に示すように、リー
ド３にチップ１をマウントする際、メッキ部４にのみツ
ール７からの圧力がかかる。このため、メッキ４が配置
された部分の下部のテープとチップとの間は十分な圧力
が加わり密着性がよいが、メッキ４が配置されていない
部分の下部のテープとチップとの間に十分な圧力が加わ
らない場合が生じる。よって、チップ１とテープ２との
密着性に不均一が生じ、接着不良や信頼性不良を引き起
こすことがある。本発明は、上記課題に鑑みなされたも
のであり、チップとテープとの密着性を向上させること
を目的とする。As described above, a part of the surface of the lead frame is usually plated for wire bonding. When plating is applied only to the area necessary for bonding, there are a portion where the plating 4 and the tape 2 are located above and below the lead 3 and a portion where the tape 2 is stuck but the plating 4 is not formed. Since a step is formed on the lead 3 due to the presence or absence of plating, as shown in FIG. 4, when the chip 1 is mounted on the lead 3, pressure from the tool 7 is applied only to the plated portion 4. For this reason, sufficient pressure is applied between the tape and the chip below the portion where the plating 4 is disposed, and good adhesion is obtained. However, there is sufficient space between the tape and the chip below the portion where the plating 4 is not disposed. May not be applied. Therefore, the adhesiveness between the chip 1 and the tape 2 becomes non-uniform, which may cause poor bonding and poor reliability. The present invention has been made in view of the above problems, and has as its object to improve the adhesion between a chip and a tape.

【０００５】[0005]

【課題を解決するための手段】上記課題を解決するた
め、本発明の半導体装置は、回路が形成された半導体チ
ップの表面の近傍にリードが延在し、前記リードが前記
半導体チップにテープを介して接着され、前記リードに
おいて、下面に前記テープが接着された部分の上面には
前記テープとの接着面積と同一以上の面積を有するメッ
キが施され、前記半導体チップ及び前記リードが樹脂で
封止されている。In order to solve the above problems, a semiconductor device according to the present invention has leads extending near a surface of a semiconductor chip on which a circuit is formed, and the leads are taped to the semiconductor chip. The lead is plated with an area equal to or larger than the adhesive area with the tape on the upper surface of the part where the tape is adhered to the lower surface of the lead, and the semiconductor chip and the lead are sealed with resin. Has been stopped.

【０００６】[0006]

【発明の実施の形態】以下、図面を参照して本発明の実
施の形態を説明する。図１は、本発明の実施例の断面図
を示す。また、図２は、本発明の実施例の要部の斜視図
を示す。ただし図２において樹脂は図示していない。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a sectional view of an embodiment of the present invention. FIG. 2 is a perspective view of a main part of the embodiment of the present invention. However, the resin is not shown in FIG.

【０００７】本実施例において、半導体チップ１にはす
でに回路が形成されており、半導体チップ上にはボンデ
ィングパッド９が設けられている。ボンディングパッド
９は、例えば図２に示すように直線状で且つ複数列形成
されている。In this embodiment, a circuit is already formed on the semiconductor chip 1, and a bonding pad 9 is provided on the semiconductor chip. The bonding pads 9 are formed, for example, linearly and in a plurality of rows as shown in FIG.

【０００８】また、リード３の上面にワイヤボンディン
グためにメッキ４が施される。この際、下面にテープ２
が張り付けられるリードの直上には必ずメッキが施され
るようにする。すなわち、リード３の上面にはリード３
の下面に接着されたテープ２の接着面積と同一以上の面
積を有するメッキが施されている。Further, plating 4 is applied to the upper surface of the lead 3 for wire bonding. At this time, the tape 2
Be sure to apply plating immediately above the lead to which the is attached. That is, the lead 3
A plating having an area equal to or larger than the bonding area of the tape 2 bonded to the lower surface of the tape 2 is applied.

【０００９】続いて、半導体チップ１のボンディングパ
ッド９が設けられている面の周辺部に、ボンディングパ
ッド９が並べられた方向に沿って細長い接着剤テープ２
を貼り付ける。Subsequently, the adhesive tape 2 which is elongated along the direction in which the bonding pads 9 are arranged is provided around the surface of the semiconductor chip 1 where the bonding pads 9 are provided.
Paste.

【００１０】その後、図３に示すように、ステージ８上
に、接着剤テープ２が貼り付けられている面が表になる
ように半導体チップ１を載せる。さらに、テープ２上
に、メッキ４側がテープ２の反対側になるように複数の
リード３を載せる。この際、それぞれのリード３におい
て、下面がテープ２と接触しているリード３の直上には
必ずメッキが施されているようにする。リード２間に
は、テープ２が露出している。Thereafter, as shown in FIG. 3, the semiconductor chip 1 is mounted on the stage 8 such that the surface on which the adhesive tape 2 is attached is turned upside down. Further, a plurality of leads 3 are placed on the tape 2 such that the plating 4 side is opposite to the tape 2. At this time, in each of the leads 3, plating must be applied immediately above the leads 3 whose lower surfaces are in contact with the tape 2. The tape 2 is exposed between the leads 2.

【００１１】次に、リード３上にツール７を押圧し、リ
ード３とテープ２とを接着させ、テープ２とチップ１と
を接着させる。テープ２上にはリード３を介して必ずメ
ッキ４があるため、ツール７から加えられる力はテープ
２に均一に加わり、リード３とテープ２間及びテープ２
とチップ１間は均一に接着される。Next, the tool 7 is pressed onto the lead 3, the lead 3 and the tape 2 are bonded, and the tape 2 and the chip 1 are bonded. Since the plating 4 always exists on the tape 2 via the leads 3, the force applied from the tool 7 uniformly applies to the tape 2, and the force between the leads 3 and the tape 2 and the tape 2
And the chip 1 are uniformly bonded.

【００１２】その後、リード３のメッキ部４と半導体チ
ップ１上のボンディングパッド９とをワイヤ５で接続す
る。さらに、樹脂６によりチップ１、リード３及びワイ
ヤ５を封止する。その後、リード３を折り曲げる。こう
して半導体装置が作成される。Thereafter, the plating portion 4 of the lead 3 and the bonding pad 9 on the semiconductor chip 1 are connected by the wire 5. Further, the chip 1, the leads 3 and the wires 5 are sealed with the resin 6. After that, the lead 3 is bent. Thus, a semiconductor device is manufactured.

【００１３】[0013]

【発明の効果】以上説明したように、本発明によれば、
リードのテープが貼付されたエリア全体に対応してメッ
キを施すことにより、ツールからテープに均等に圧力を
加えることができるため、テープとチップとを均一に密
着でき、接着不良や信頼性不良を低減させることができ
る。As described above, according to the present invention,
By applying plating to the entire area where the lead tape is stuck, pressure can be applied evenly from the tool to the tape, so that the tape and the chip can be evenly adhered to each other, preventing poor adhesion and poor reliability. Can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施例の断面図。FIG. 1 is a sectional view of an embodiment of the present invention.

【図２】本発明の実施例の斜視図。FIG. 2 is a perspective view of an embodiment of the present invention.

【図３】本発明の実施例をマウントする様子を示す図。FIG. 3 is a view showing a state of mounting the embodiment of the present invention.

【図４】従来例を示す図。FIG. 4 is a diagram showing a conventional example.

【図５】従来のマウントする様子を示す図。FIG. 5 is a diagram showing a conventional mounting state.

【符号の説明】[Explanation of symbols]

１…半導体チップ、 ２…テープ、 ３…リード、 ４…メッキ、 ５…ワイヤ、 ６…樹脂、 ７…ツール、 ８…ステージ、 ９…ボンディングパッド。 1 semiconductor chip, 2 tape, 3 lead, 4 plating, 5 wire, 6 resin, 7 tool, 8 stage, 9 bonding pad.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 回路が形成された半導体チップの表面の
近傍にリードが延在し、前記リードが前記半導体チップ
にテープを介して接着され、前記リードにおいて、下面
に前記テープが接着された部分の上面には前記テープと
の接着面積と同一以上の面積を有するメッキが施され、
前記半導体チップ及び前記リードが樹脂で封止されてい
ることを特徴とする半導体装置。1. A lead extending near a surface of a semiconductor chip on which a circuit is formed, the lead being bonded to the semiconductor chip via a tape, and a portion of the lead where the tape is bonded to a lower surface. The upper surface is plated with an area equal to or greater than the adhesive area with the tape,
A semiconductor device, wherein the semiconductor chip and the lead are sealed with a resin. 【請求項２】 回路が形成された半導体チップの表面の
近傍に複数のリードが延在し、前記複数のリードが、一
体化されたテープを介して前記半導体チップに接着さ
れ、前記リードの各々において、下面に前記テープが接
着された部分の上面には前記テープとの接着面積と同一
以上の面積を有するメッキが施され、前記メッキは前記
半導体チップ上に設けられたパッドとワイヤを介して電
気的に接続され、前記半導体チップ及び前記複数のリー
ドが樹脂で封止されていることを特徴とする半導体装
置。2. A plurality of leads extend near a surface of a semiconductor chip on which a circuit is formed, and the plurality of leads are bonded to the semiconductor chip via an integrated tape, and each of the leads is In the above, the upper surface of the portion where the tape is bonded to the lower surface is plated with an area equal to or larger than the bonding area with the tape, and the plating is performed via pads and wires provided on the semiconductor chip. A semiconductor device electrically connected, wherein the semiconductor chip and the plurality of leads are sealed with a resin.
JP8187467A 1996-07-17 1996-07-17 Semiconductor device Pending JPH1032286A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8187467A JPH1032286A (en) 1996-07-17 1996-07-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8187467A JPH1032286A (en) 1996-07-17 1996-07-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1032286A true JPH1032286A (en) 1998-02-03

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JP8187467A Pending JPH1032286A (en) 1996-07-17 1996-07-17 Semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100652517B1 (en) 2004-03-23 2006-12-01 삼성전자주식회사 semiconductor package having leads directly attached to chip, manufacturing method and apparatus thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100652517B1 (en) 2004-03-23 2006-12-01 삼성전자주식회사 semiconductor package having leads directly attached to chip, manufacturing method and apparatus thereof

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