KR20010017143A - Stacked flip chip package using carrier tape - Google Patents
Stacked flip chip package using carrier tape Download PDFInfo
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- KR20010017143A KR20010017143A KR1019990032515A KR19990032515A KR20010017143A KR 20010017143 A KR20010017143 A KR 20010017143A KR 1019990032515 A KR1019990032515 A KR 1019990032515A KR 19990032515 A KR19990032515 A KR 19990032515A KR 20010017143 A KR20010017143 A KR 20010017143A
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- carrier tape
- bump
- bumps
- substrate
- metal thin
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- 239000004065 semiconductor Substances 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000010408 film Substances 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000010409 thin film Substances 0.000 claims abstract description 24
- 229910000679 solder Inorganic materials 0.000 claims abstract description 11
- 238000000465 moulding Methods 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 239000011347 resin Substances 0.000 claims abstract description 9
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 239000002313 adhesive film Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 239000000806 elastomer Substances 0.000 abstract description 3
- 229920001971 elastomer Polymers 0.000 abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 239000010931 gold Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 캐리어 테이프(Carrier tape)를 이용한 적층형 플립 칩 패키지(Stacked flip chip package)에 관한 것이며, 더욱 구체적으로는 범프들이 형성된 반도체 칩들이 패키지 조립 레벨(Package assembly level)에서 플립 칩 본딩 기술을 이용하여 상하부에 적층될 수 있도록 형성된 캐리어 테이프를 이용하여 형성된 적층형 플립 칩 패키지의 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked flip chip package using a carrier tape, and more specifically, semiconductor chips having bumps using flip chip bonding technology at a package assembly level. The present invention relates to a structure of a stacked flip chip package formed by using a carrier tape formed to be stacked on upper and lower portions thereof.
플립 칩을 이용하여 칩 스케일 패키지(CSP ; Chip Scale Package)를 구현하는 방법은 반도체 제조 분야에서 널리 활용되고 있으며, 더 나아가 플립 칩을 적층시킨 칩 스케일 패키지 형태의 소위 적층형 플립 칩 패키지가 개발되고 있다.A method of implementing a chip scale package (CSP) using a flip chip is widely used in the semiconductor manufacturing field, and a so-called stacked flip chip package in the form of a chip scale package in which flip chips are stacked has been developed. .
기존의 적층형 플립 칩 패키지는 웨이퍼 레벨에서 반도체 칩 위로 배선을 재배열하는 공정(Redistribution)을 통하여 반도체 칩들을 적층시킴으로서 구현되거나, 또는 패키지 조립 레벨에서 한 개의 반도체 칩이 기판에 플립 칩 본딩된 후 그 위로 다른 반도체 칩이 와이어 본딩을 통해 적층되는 등의 방법으로 구현되었다.Existing stacked flip chip packages are implemented by stacking semiconductor chips through redistribution of wiring over semiconductor chips at the wafer level, or at the package assembly level, a single semiconductor chip is flip chip bonded onto a substrate and then Back to top Other semiconductor chips have been implemented, for example, by wire bonding.
웨이퍼 레벨에서 배선을 재배열하는 공정을 통해 적층되는 반도체 칩들의 경우에는 모든 반도체 칩에 대하여 공정이 진행되지만, 실제 그 수율에 있어서는 배선을 재배열하는 공정의 난이도에 따라 최종적인 반도체 칩의 수율이 저하되어 적층형 플립 칩 패키지의 신뢰도가 낮아질 수 있다.In the case of semiconductor chips stacked by wafer rearrangement, the process proceeds for all semiconductor chips, but in actual yield, the yield of the final semiconductor chip depends on the difficulty of rearranging the wiring. The reliability of the stacked flip chip package may be lowered.
또한, 기존의 반도체 칩들을 직접 이용하지 못하고 배선을 재배열하는 공정을 거쳐야 하기 때문에 제조 비용의 단가가 상승할 수 있다.In addition, the cost of manufacturing costs may increase due to the process of rearranging the wiring without directly using the existing semiconductor chips.
기판 위로 플립 칩 본딩 후 플립 칩 본딩 된 반도체 칩 위로 다른 반도체 칩이 와이어 본딩을 통해 적층되고 이와 같이 적층된 반도체 칩들을 에폭시 몰딩 컴파운드(EMC ; Epoxy molding compound)와 같은 몰딩수지로 성형하여 구현되는 적층형 패키지의 경우에는 제조공정의 복잡화로 인한 어려움이 발생할 수 있다.A stack type that is formed by flip-bonding a chip onto a substrate and then stacking another semiconductor chip on a flip-chip bonded semiconductor chip by molding the semiconductor chips stacked with a molding resin such as an epoxy molding compound (EMC). In the case of a package, difficulties may arise due to complexity of the manufacturing process.
도 1에는 종래의 적층형 반도체 패키지(100)가 도시되어 있으며, 도 1을 참고로 하여 이를 설명하면 다음과 같다. 먼저 범프(12)가 형성된 반도체 칩(10)을 기판(30) 위에 플립 칩 본딩한 후에, 플립 칩 본딩된 반도체 칩(10) 위로 본딩패드들(22)이 위로 향하도록 다른 반도체 칩(20)을 적층 접착하고, 적층된 반도체 칩의 본딩패드들(22)을 기판(30)의 전극패드들(도시되지 않음) 위로 와이어 본딩을 한다. 이들 적층된 반도체 칩들(10, 20)과 본딩 와이어(24)를 포함하는 전기적 연결부를 몰딩수지(40)로 성형하고, 마지막으로 기판(30)의 하면에 솔더 볼들(50)과 같은 외부 접속 단자를 형성하는 등의 공정이 진행된다.1 illustrates a conventional stacked semiconductor package 100, which will be described below with reference to FIG. 1. First, the semiconductor chip 10 having the bumps 12 formed thereon is flip chip bonded onto the substrate 30, and then the other semiconductor chip 20 is disposed so that the bonding pads 22 face upward on the flip chip bonded semiconductor chip 10. Is laminated and bonded to the bonding pads 22 of the stacked semiconductor chip over the electrode pads (not shown) of the substrate 30. The electrical connection including the stacked semiconductor chips 10 and 20 and the bonding wires 24 is formed of a molding resin 40, and finally, an external connection terminal such as solder balls 50 on the bottom surface of the substrate 30. The process of forming a.
이와 같은 공정을 통하여 구현되는 적층형 패키지는 그 공정이 복잡하기 때문에 제조 비용과 제조 시간의 증가를 가져올 수 있으며, 또한 적층되는 반도체 칩들과 기판이 일정한 형태의 배열로 형성된 패드들을 구비해야 하는 강제성이 요구될 수 있다.The stacked package implemented through such a process can increase manufacturing cost and manufacturing time due to the complexity of the process, and also requires the force of having the semiconductor chips to be stacked and pads formed in a predetermined array of substrates. Can be.
본 발명의 목적은 캐리어 테이프를 이용하여 신뢰성이 높은 적층형 플립 칩 패키지를 제공하는 것이다.It is an object of the present invention to provide a highly reliable stacked flip chip package using a carrier tape.
본 발명의 다른 목적은 범프들이 형성된 반도체 칩들과 캐리어 테이프를 이용하여 구현되는 고용량·고성능의 적층형 플립 칩 패키지를 제공하는 것이다.Another object of the present invention is to provide a high capacity and high performance stacked flip chip package implemented using a carrier tape and semiconductor chips having bumps formed thereon.
도 1은 종래의 적층형 패키지를 도시한 단면도,1 is a cross-sectional view showing a conventional stacked package,
도 2는 본 발명의 일 실시예에 따른 적층형 플립 칩 패키지의 단면도,2 is a cross-sectional view of a stacked flip chip package according to an embodiment of the present invention;
도 3은 도 2의 캐리어 테이프를 분해하여 도시한 단면도,3 is an exploded cross-sectional view showing the carrier tape of FIG.
도 4는 본 발명의 다른 실시예에 따른 적층형 플립 칩 패키지의 단면도,4 is a cross-sectional view of a stacked flip chip package according to another embodiment of the present invention;
도 5a는 도 4의 캐리어 테이프를 분해하여 도시한 단면도,5A is an exploded cross-sectional view of the carrier tape of FIG. 4;
도 5b는 본 발명의 또 다른 실시예에 따른 캐리어 테이프를 도시한 단면도이다.5B is a sectional view showing a carrier tape according to another embodiment of the present invention.
〈도면의 주요 부분에 대한 설명〉<Description of Main Parts of Drawing>
10, 20, 110, 120, 210, 220 : 반도체 칩 12, 112, 212 : 범프10, 20, 110, 120, 210, 220: semiconductor chip 12, 112, 212: bump
22 : 본딩패드 24 : 본딩 와이어22: bonding pad 24: bonding wire
30, 160, 260 : 기판(Substrate) 40, 170, 270 : 성형수지30, 160, 260: Substrate 40, 170, 270: Molding resin
50, 180, 280 : 솔더 볼 100 : 적층 칩 패키지50, 180, 280: solder ball 100: laminated chip package
130, 230 : 금속 박막 132, 232 : 범프 접속부130, 230: metal thin film 132, 232: bump connection
134, 234 : 빔 리드 140 : 이방성 전도 필름(ACF)134, 234: beam lead 140: anisotropic conductive film (ACF)
142 : 전도성 입자142: conductive particles
150, 250, 250' : 캐리어 테이프(Carrier tape)150, 250, 250 ': Carrier tape
162, 262 : 기판의 상면 164, 264 : 기판의 하면162, 262: upper surface of the substrate 164, 264: lower surface of the substrate
200, 300 : 적층형 플립 칩 패키지200, 300: stacked flip chip package
240 : 탄성중합체(Elastomer) 필름240: elastomer film
242 : 개구부 290 : 접착제242: opening 290: adhesive
이러한 목적을 달성하기 위하여 본 발명은 범프 접속부들과 양단부의 빔 리드들을 포함하는 소정 패턴의 금속 박막과, 빔 리드들을 제외한 금속 박막의 상하면에 접착되어 있는 이방성 전도 필름들로 구성된 캐리어 테이프와; 범프들이 형성되어 있으며, 각 범프가 범프 접속부에 대응되면서 이방성 전도 필름 위로 접착되는 복수개의 반도체 칩들과; 반도체 칩들이 접착된 캐리어 테이프가 실장되는 상면과 솔더 볼들이 형성되는 하면을 갖는 기판; 및 기판의 상면 위로 캐리어 테이프를 포함하는 영역을 성형하는 몰딩수지;를 포함하며, 범프들이 이방성 전도 필름을 압축하여 범프 접속부에 전기적으로 연결되고, 빔 리드들이 절곡되어 기판에 전기적으로 연결되는 것을 특징으로 하는 캐리어 테이프를 이용한 적층형 플립 칩 패키지를 제공한다.In order to achieve the above object, the present invention provides a carrier tape comprising a metal thin film having a predetermined pattern including bump connecting portions and beam leads at both ends, and anisotropic conductive films adhered to upper and lower surfaces of the metal thin film except beam leads; A plurality of semiconductor chips in which bumps are formed, and each bump is bonded onto the anisotropic conductive film while corresponding to the bump connection portion; A substrate having a top surface on which a carrier tape bonded with semiconductor chips is mounted and a bottom surface on which solder balls are formed; And a molding resin for forming an area including a carrier tape over the upper surface of the substrate, wherein the bumps are electrically connected to the bump connecting portion by compressing the anisotropic conductive film, and the beam leads are bent and electrically connected to the substrate. A stacked flip chip package using a carrier tape is provided.
또한 본 발명에 따른 적층형 플립 칩 패키지는 범프 접속부들과 양단부의 빔 리드들을 포함하는 소정 패턴의 금속 박막과, 빔 리드들을 제외한 금속 박막의 상하면에 접착되고 범프 접속부들에 대응되는 개구부들이 형성된 절연성 접착 필름들로 구성된 캐리어 테이프;를 포함하며, 범프들이 개구부를 통하여 범프 접속부에 직접 접촉되어 전기적으로 연결되고, 빔 리드들이 절곡되어 기판에 전기적으로 연결되는 것을 특징으로 한다.In addition, the stacked flip chip package according to the present invention is an insulating adhesive having a predetermined pattern of a metal thin film including bump connections and beam leads at both ends, and openings formed on upper and lower surfaces of the metal thin film except for beam leads and corresponding to the bump connections. And a carrier tape composed of films, wherein the bumps are directly contacted and electrically connected to the bump connecting portion through the openings, and the beam leads are bent and electrically connected to the substrate.
이에 더하여, 반도체 칩의 범프가 금(Au) 또는 니켈(Ni) 등의 스터드(Stud) 범프일 경우에는 개구부 내에 전도성 접착제가 충진됨으로써 전도성 접착제를 통해 스터드 범프가 대응되는 범프 접속부에 접착되는 것을 특징으로 한다.In addition, when the bump of the semiconductor chip is a stud bump such as gold (Au) or nickel (Ni), the conductive adhesive is filled in the opening to bond the stud bump to the corresponding bump connection portion through the conductive adhesive. It is done.
이하 첨부도면을 참고하여 본 발명에 따른 바람직한 실시예들을 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2는 본 발명의 일 실시예에 따른 적층형 플립 칩 패키지(200)의 단면도이며, 도 3은 도 2의 캐리어 테이프(150)를 분해하여 도시한 단면도이다. 도 2 및 도 3을 참고로 하여 본 발명의 일 실시예에 따른 적층형 플립 칩 패키지(200)를 설명하면 다음과 같다.2 is a cross-sectional view of the stacked flip chip package 200 according to an embodiment of the present invention, and FIG. 3 is an exploded cross-sectional view of the carrier tape 150 of FIG. 2. Referring to FIGS. 2 and 3, a stacked flip chip package 200 according to an exemplary embodiment will be described below.
본 발명에 따른 적층형 플립 칩 패키지(200)는 돌출되어 형성된 범프들(112)을 갖는 반도체 칩들(110, 120)이 범프들(112)이 마주 향하도록 적층되고, 그 사이에 캐리어 테이프(150)가 개재되어 전기적으로 연결되며, 이와 같은 구조물이 기판의 상면(162) 위에 실장된 후 몰딩수지(170)로 성형되고, 기판의 하부(164)에 솔더 볼들(180)과 같은 외부 접속 단자가 형성된 것을 특징으로 한다.In the stacked flip chip package 200 according to the present invention, the semiconductor chips 110 and 120 having the bumps 112 protruding from each other are stacked so that the bumps 112 face each other, and the carrier tape 150 is disposed therebetween. Is interposed therebetween, and the structure is mounted on the upper surface 162 of the substrate and then molded into the molding resin 170, and an external connection terminal such as solder balls 180 is formed on the lower portion 164 of the substrate. It is characterized by.
또한, 캐리어 테이프(150)는 범프들(112)에 대응되는 범프 접속부(132)와 기판에 연결되는 빔 리드들(134)을 포함하는 소정의 형태를 갖는 금속 박막(130)과 금속 박막의 상/하면에 접착되어 있는 이방성 전도 필름(140 ; ACF ; Anisotropic Conductive Film)으로 구성되어 있다.In addition, the carrier tape 150 may include an image of the metal thin film 130 and the metal thin film having a predetermined shape including a bump connecting portion 132 corresponding to the bumps 112 and beam leads 134 connected to the substrate. It consists of an anisotropic conductive film (140; ACF) adhere | attached on / under surface.
특히, 금속 박막의 패턴 형태에 따라 적용되는 반도체 칩의 범프 형성 위치가 변형될 수 있으며, 이와 같은 패턴을 변형시킴에 따라 동종(同宗)은 물론 이종(異種)의 반도체 칩들을 적층시킬 수 있다.In particular, the bump formation position of the semiconductor chip applied according to the pattern shape of the metal thin film may be modified, and by modifying such a pattern, semiconductor chips of the same type as well as different types of semiconductor chips may be stacked.
이방성 전도 필름(140)은 절연성 재질의 필름 내에 전도성 입자들(142)이 일정한 간격으로 이격되어 균일하게 내재되어 있는 것을 특징으로 하며, 이방성 전도 필름(140)에 대하여 임의의 방향으로 힘을 가해줄 때, 힘이 가해진 방향으로 전도성 입자들(142)이 연결되어 전기적으로 연결되는 것을 특징으로 한다.The anisotropic conductive film 140 is characterized in that the conductive particles 142 are uniformly embedded in the insulating material film at regular intervals, and apply a force in an arbitrary direction to the anisotropic conductive film 140. When the conductive particles 142 are connected in the direction in which the force is applied, it is characterized in that the electrically connected.
즉, 도 2와 같이 반도체 칩들(110, 120)에서 돌출된 범프(112)가 이방성 전도 필름(140)을 누르는 힘에 의하여 일정한 간격으로 이격되어 내재된 전도성 입자들(142)이 누르는 힘의 방향으로 서로 연결되어 결국 범프(112)와 범프에 대응되는 범프 접속부(132)가 전기적으로 연결될 수 있다.That is, as shown in FIG. 2, the bumps 112 protruding from the semiconductor chips 110 and 120 are spaced apart at regular intervals by a force pressing the anisotropic conductive film 140, and thus the direction of the pressing force of the conductive particles 142 embedded therein. As a result, the bumps 112 and the bump connectors 132 corresponding to the bumps may be electrically connected to each other.
또한, 빔 리드들(134)은 본딩 툴(Bonding tool)과 같은 본딩 도구를 사용하여 기판 상면(162) 위에 형성된 전극패드(도시되지 않음)에 전기적으로 연결될 수 있다.In addition, the beam leads 134 may be electrically connected to an electrode pad (not shown) formed on the upper surface 162 of the substrate using a bonding tool such as a bonding tool.
도 4는 본 발명의 다른 실시예에 따른 적층형 플립 칩 패키지(300)의 단면도이며, 도 5a는 도 4의 캐리어 테이프를 분해하여 도시한 단면도이다. 도 4 및 도 5a를 참고로 하여 본 발명의 다른 실시예에 따른 적층형 플립 칩 패키지(300)를 설명하면 다음과 같다.4 is a cross-sectional view of a stacked flip chip package 300 according to another embodiment of the present invention, and FIG. 5A is an exploded cross-sectional view of the carrier tape of FIG. 4. Referring to FIGS. 4 and 5A, a stacked flip chip package 300 according to another exemplary embodiment of the present invention will be described below.
본 발명에 따른 적층형 플립 칩 패키지(300)는 돌출되어 형성된 범프들(212)을 갖는 반도체 칩들(210, 220)이 범프들(212)이 마주 향하도록 적층되고, 그 사이에 캐리어 테이프(250)가 개재되어 전기적으로 연결되며, 이와 같은 구조물이 기판의 상면(262) 위에 실장된 후 몰딩수지(270)로 성형되고, 기판의 하부(264)에 솔더 볼들(280)과 같은 외부 접속 단자가 형성된 것을 특징으로 한다.In the stacked flip chip package 300 according to the present invention, the semiconductor chips 210 and 220 having the bumps 212 protruding from each other are stacked so that the bumps 212 face each other, and the carrier tape 250 is interposed therebetween. Is interposed therebetween, and the structure is mounted on the upper surface 262 of the substrate and then molded into a molding resin 270, and an external connection terminal such as solder balls 280 is formed on the lower portion 264 of the substrate. It is characterized by.
또한, 캐리어 테이프(250)는 범프들(212)에 대응되는 범프 접속부(232)와 기판에 연결되는 빔 리드들(234)을 포함하는 소정의 형태를 갖는 금속 박막(230)과 금속 박막의 상/하면에 접착되어 있는 탄성중합체(Elastomer) 필름과 같은 절연성 접착 필름(240)으로 구성되어 있다.In addition, the carrier tape 250 may include an image of the metal thin film 230 and the metal thin film having a predetermined shape including a bump connecting portion 232 corresponding to the bumps 212 and beam leads 234 connected to the substrate. It consists of an insulating adhesive film 240 such as an elastomer film adhered to the underside.
절연성 접착 필름(240)에는 접착되는 반도체 칩(210, 220)의 범프들(212)에 대응되는 개구부들(242)이 형성된 것을 특징으로 하며, 도 4에 도시된 바와 같이 반도체 칩들(210, 220)에서 돌출된 범프(212)가 대응되는 개구부(242)에 끼워져 범프 접속부(232)에 직접 접촉됨으로써 범프(212)와 범프에 대응되는 금속 박막(230)의 범프 접속부(232)가 전기적으로 연결될 수 있다.Openings 242 corresponding to the bumps 212 of the semiconductor chips 210 and 220 to be bonded are formed in the insulating adhesive film 240, and the semiconductor chips 210 and 220 are illustrated in FIG. 4. Bumps 212 protruding from the first and second bumps 212 are inserted into corresponding openings 242 to be in direct contact with the bump connecting portions 232 so that the bumps 212 and the bump connecting portions 232 of the metal thin film 230 corresponding to the bumps may be electrically connected to each other. Can be.
이때, 반도체 칩의 범프가 솔더 재질로 형성된 솔더 범프(Solder bump)인 경우에는 반도체 칩이 절연성 접착 필름 위로 접착될 때 리플로우(Reflow) 되어 범프 접속부 위에 접착·고정될 수 있지만, 솔더가 아닌 금(Au) 또는 니켈(Ni) 등의 재질로 형성된 소위 스터드 범프(Stud bump)인 경우에는 용융점이 높기 때문에 리플로우 되지 않아 접착될 수 없기 때문에 신뢰성이 저하될 수 있다.In this case, when the bump of the semiconductor chip is a solder bump formed of a solder material, when the semiconductor chip is bonded onto the insulating adhesive film, the semiconductor chip may be reflowed and adhered to and fixed on the bump connection part. In the case of a so-called stud bump formed of a material such as (Au) or nickel (Ni), since the melting point is high, the reflow may not be performed due to the high melting point, and thus reliability may be degraded.
이에 도 5b에 도시된 바와 같은 캐리어 테이프(250')가 개시되어 있다. 도 5b에 도시된 캐리어 테이프(250')는 도 5a의 캐리어 테이프(250)와 동일한 구조에 더하여, 개구부들(242) 내에 전도성 접착제(290 ; Conductive adhesive)가 충진된 것을 특징으로 한다.Thus, a carrier tape 250 ′ as shown in FIG. 5B is disclosed. In addition to the same structure as the carrier tape 250 of FIG. 5A, the carrier tape 250 ′ illustrated in FIG. 5B is filled with a conductive adhesive 290 in the openings 242.
즉, 솔더(Solder)가 아닌 금(Au) 또는 니켈(Ni) 등의 재질로 제조된 스터드 범프(Stud bump)가 캐리어 테이프의 개구부 내에 끼워질 때 개구부 내에 충진되어 있는 전도성 접착제가 스터드 범프를 금속 박막의 범프 접속부에 접착·고정시킴으로서 신뢰성을 향상할 수 있다.That is, when a stud bump made of a material such as gold (Au) or nickel (Ni), not solder, is inserted into the opening of the carrier tape, a conductive adhesive filled in the opening may cause the stud bump to be metal. Reliability can be improved by bonding and fixing to the bump connection part of a thin film.
이상에서 설명한 바와 같이, 본 발명에 따른 적층형 플립 칩 패키지는 별도로 제작된 캐리어 테이프를 이용하여 반도체 칩들을 플립 칩 본딩하여 적층함으로서 제조공정을 단순화함으로써 제조비용을 절감하고 제조공정을 단축하는 등 제조공정의 효율을 향상할 수 있으며, 캐리어 테이프를 통하여 반도체 칩을 적층하기 때문에 신뢰성을 향상할 수 있는 이점이 있다.As described above, the stack type flip chip package according to the present invention is manufactured by simplifying the manufacturing process by flip-chip bonding and stacking semiconductor chips using a carrier tape manufactured separately, thereby reducing manufacturing costs and shortening the manufacturing process. The efficiency of the present invention can be improved and reliability can be improved because the semiconductor chips are laminated through the carrier tape.
즉, 종래와 같이 웨이퍼 레벨(Wafer level)에서 각 반도체 칩에 대하여 별도의 배선을 재배열하는 공정을 진행하거나 또는 패키지 조립 레벨(Package assembly level)에서 플립 칩 본딩한 다음 다시 와이어 본딩을 실시하는 등의 복잡한 공정을 본 발명에서는 미리 제조된 캐리어 테이프를 이용하여 플립 칩 본딩하여 적층함으로써 보다 단순한 공정으로 대신하여 적층형 플립 칩 패키지를 구현할 수 있다.That is, a process of rearranging separate wirings for each semiconductor chip at a wafer level as in the prior art, or flip chip bonding at a package assembly level and then wire bonding again, etc. In the present invention, a stacked flip chip package can be implemented by a simpler process by flip chip bonding and laminating using a pre-fabricated carrier tape.
또한, 캐리어 테이프 내의 금속 박막을 소정의 패턴으로 형성함으로써 다양한 종류의 반도체 칩들을 적용할 수 있으며, 이에 따라 동종(同種)의 반도체 칩들은 물론 이종(異種)의 반도체 칩들을 적용하여 적층형 플립 칩 패키지를 제조할 수 있다.In addition, various types of semiconductor chips may be applied by forming a metal thin film in a carrier tape in a predetermined pattern, and accordingly, a stack type flip chip package may be applied by applying not only the same type of semiconductor chips but also different types of semiconductor chips. Can be prepared.
본 발명에 따른 적층형 플립 칩 패키지는 금속 박막과 금속 박막의 상/하로 접착된 이방성 전도 필름 또는 개구부가 형성된 탄성중합체 필름 등과 같은 접착 필름으로 구성된 캐리어 테이프를 이용하여 반도체 칩들이 플립 칩 본딩되어 형성되는 구조를 특징으로 하며, 이러한 구조적 특징에 따라 적층형 플립 칩 패키지의 제조비용을 절감하고 제조공정을 단축하는 등 제조공정의 효율을 향상할 수 있으며, 나아가 적층형 플립 칩 패키지의 신뢰성을 향상할 수 있다.Stacked flip chip package according to the present invention is a semiconductor chip is formed by flip chip bonding using a carrier tape composed of an adhesive film such as an anisotropic conductive film or an opening formed elastomeric film bonded to the metal thin film and the metal thin film. The structure of the present invention can improve the efficiency of the manufacturing process, such as reducing the manufacturing cost of the stacked flip chip package and shortening the manufacturing process according to the structural feature, and further improving the reliability of the stacked flip chip package.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20030008450A (en) * | 2001-07-18 | 2003-01-29 | 삼성전자 주식회사 | The stack package of ball grid array type |
| KR20030057184A (en) * | 2001-12-28 | 2003-07-04 | 동부전자 주식회사 | semiconductor package and its manufacturing method |
| KR100446713B1 (en) * | 2000-05-26 | 2004-09-01 | 샤프 가부시키가이샤 | Semiconductor device and liquid crystal module |
| KR100776130B1 (en) * | 2001-03-22 | 2007-11-16 | 매그나칩 반도체 유한회사 | Stacked semiconductor package |
| KR100808582B1 (en) * | 2001-12-29 | 2008-02-29 | 주식회사 하이닉스반도체 | Chip stack package |
| KR100842921B1 (en) * | 2007-06-18 | 2008-07-02 | 주식회사 하이닉스반도체 | Method for fabricating of semiconductor package |
| US8148828B2 (en) | 2008-10-23 | 2012-04-03 | Samsung Electronics Co., Ltd. | Semiconductor packaging device |
| CN111384044A (en) * | 2020-04-26 | 2020-07-07 | 无锡中微高科电子有限公司 | Chip 3D packaging combination stacking structure and packaging method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980026241A (en) * | 1996-10-08 | 1998-07-15 | 김광호 | Multilayer Chip Package Using Anisotropic Conductive Film |
| JPH10199930A (en) * | 1996-12-28 | 1998-07-31 | Casio Comput Co Ltd | Connection structure of electronic components and connecting method therefor |
| JPH10209616A (en) * | 1997-01-17 | 1998-08-07 | Katsuya Hiroshige | Method for electrically connecting conductive board to multicontact conductive member and anisotropic conductive connecting sheet |
| JPH11204567A (en) * | 1997-10-28 | 1999-07-30 | Seiko Epson Corp | Anisotropic conductive bonding agent and forming method thereof to substrate and semiconductor-chip mounting method and semiconductor device |
-
1999
- 1999-08-09 KR KR10-1999-0032515A patent/KR100533847B1/en not_active IP Right Cessation
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100446713B1 (en) * | 2000-05-26 | 2004-09-01 | 샤프 가부시키가이샤 | Semiconductor device and liquid crystal module |
| KR100776130B1 (en) * | 2001-03-22 | 2007-11-16 | 매그나칩 반도체 유한회사 | Stacked semiconductor package |
| KR20030008450A (en) * | 2001-07-18 | 2003-01-29 | 삼성전자 주식회사 | The stack package of ball grid array type |
| KR20030057184A (en) * | 2001-12-28 | 2003-07-04 | 동부전자 주식회사 | semiconductor package and its manufacturing method |
| KR100808582B1 (en) * | 2001-12-29 | 2008-02-29 | 주식회사 하이닉스반도체 | Chip stack package |
| KR100842921B1 (en) * | 2007-06-18 | 2008-07-02 | 주식회사 하이닉스반도체 | Method for fabricating of semiconductor package |
| US7498199B2 (en) | 2007-06-18 | 2009-03-03 | Hynix Semiconductor Inc. | Method for fabricating semiconductor package |
| US8148828B2 (en) | 2008-10-23 | 2012-04-03 | Samsung Electronics Co., Ltd. | Semiconductor packaging device |
| CN111384044A (en) * | 2020-04-26 | 2020-07-07 | 无锡中微高科电子有限公司 | Chip 3D packaging combination stacking structure and packaging method thereof |
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|---|---|
| KR100533847B1 (en) | 2005-12-07 |
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