JPH10303259A - 半導体集積回路装置およびその製造方法 - Google Patents

半導体集積回路装置およびその製造方法

Info

Publication number
JPH10303259A
JPH10303259A JP9111520A JP11152097A JPH10303259A JP H10303259 A JPH10303259 A JP H10303259A JP 9111520 A JP9111520 A JP 9111520A JP 11152097 A JP11152097 A JP 11152097A JP H10303259 A JPH10303259 A JP H10303259A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
chip
semiconductor integrated
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9111520A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10303259A5 (enExample
Inventor
Hiroyuki Miyano
裕之 宮野
Kiyoshi Nakai
潔 中井
Yutaka Ito
伊藤　　豊
Chisa Makimura
智佐 牧村
Yoshirou Toho
吉郎 利穂
Takeshi Hashimoto
剛 橋本
Hidetoshi Iwai
秀俊 岩井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9111520A priority Critical patent/JPH10303259A/ja
Publication of JPH10303259A publication Critical patent/JPH10303259A/ja
Publication of JPH10303259A5 publication Critical patent/JPH10303259A5/ja
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP9111520A 1997-04-28 1997-04-28 半導体集積回路装置およびその製造方法 Pending JPH10303259A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9111520A JPH10303259A (ja) 1997-04-28 1997-04-28 半導体集積回路装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9111520A JPH10303259A (ja) 1997-04-28 1997-04-28 半導体集積回路装置およびその製造方法

Publications (2)

Publication Number Publication Date
JPH10303259A true JPH10303259A (ja) 1998-11-13
JPH10303259A5 JPH10303259A5 (enExample) 2005-02-10

Family

ID=14563418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9111520A Pending JPH10303259A (ja) 1997-04-28 1997-04-28 半導体集積回路装置およびその製造方法

Country Status (1)

Country Link
JP (1) JPH10303259A (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100385225B1 (ko) * 2001-03-23 2003-05-27 삼성전자주식회사 탐침 패드 및 범프 패드를 갖는 플립 칩형 반도체소자 및 그 제조방법
JP2005317866A (ja) * 2004-04-30 2005-11-10 Sony Corp 半導体装置およびその製造方法
JP2009212299A (ja) * 2008-03-04 2009-09-17 Fujitsu Ltd 半導体装置及びその製造方法
US7919847B2 (en) 2006-03-02 2011-04-05 Ricoh Company, Ltd. Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method
KR20140039008A (ko) * 2011-06-30 2014-03-31 어드밴테스트 (싱가포르) 피티이. 엘티디. 웨이퍼의 스크라이브 라인들에 배치된 테스트 액세스 인터페이스에 전기적으로 결합되는 반도체 다이들에 접촉하기 위한 방법, 장치, 및 시스템들
CN107680937A (zh) * 2017-09-30 2018-02-09 睿力集成电路有限公司 晶圆结构、晶圆结构切割方法及芯片

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100385225B1 (ko) * 2001-03-23 2003-05-27 삼성전자주식회사 탐침 패드 및 범프 패드를 갖는 플립 칩형 반도체소자 및 그 제조방법
JP2005317866A (ja) * 2004-04-30 2005-11-10 Sony Corp 半導体装置およびその製造方法
US7919847B2 (en) 2006-03-02 2011-04-05 Ricoh Company, Ltd. Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method
JP2009212299A (ja) * 2008-03-04 2009-09-17 Fujitsu Ltd 半導体装置及びその製造方法
KR20140039008A (ko) * 2011-06-30 2014-03-31 어드밴테스트 (싱가포르) 피티이. 엘티디. 웨이퍼의 스크라이브 라인들에 배치된 테스트 액세스 인터페이스에 전기적으로 결합되는 반도체 다이들에 접촉하기 위한 방법, 장치, 및 시스템들
CN103797570A (zh) * 2011-06-30 2014-05-14 爱德万测试(新加坡)私人有限公司 接触电性连接至位于晶圆的划片线上的测试访问接口的半导体芯片的方法、装置以及系统
JP2014526141A (ja) * 2011-06-30 2014-10-02 アドバンテスト （シンガポール） プライベート リミテッド 電気的に結合された複数の半導体ダイをウェハのスクライブライン内に位置する検査アクセスインタフェースと接触させる方法、装置、及びシステム
CN107680937A (zh) * 2017-09-30 2018-02-09 睿力集成电路有限公司 晶圆结构、晶圆结构切割方法及芯片
CN107680937B (zh) * 2017-09-30 2024-03-26 长鑫存储技术有限公司 晶圆结构、晶圆结构切割方法及芯片

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