JPH10289923A - 半導体パッケージの製造方法 - Google Patents

半導体パッケージの製造方法

Info

Publication number
JPH10289923A
JPH10289923A JP10051537A JP5153798A JPH10289923A JP H10289923 A JPH10289923 A JP H10289923A JP 10051537 A JP10051537 A JP 10051537A JP 5153798 A JP5153798 A JP 5153798A JP H10289923 A JPH10289923 A JP H10289923A
Authority
JP
Japan
Prior art keywords
chip
resin
semiconductor package
semiconductor
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10051537A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10289923A5 (enExample
Inventor
Yuichiro Furukawa
勇一郎 古川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UMC Japan Co Ltd
Original Assignee
Nippon Steel Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Semiconductor Corp filed Critical Nippon Steel Semiconductor Corp
Priority to JP10051537A priority Critical patent/JPH10289923A/ja
Publication of JPH10289923A publication Critical patent/JPH10289923A/ja
Publication of JPH10289923A5 publication Critical patent/JPH10289923A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP10051537A 1997-02-17 1998-02-17 半導体パッケージの製造方法 Pending JPH10289923A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10051537A JPH10289923A (ja) 1997-02-17 1998-02-17 半導体パッケージの製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP4691997 1997-02-17
JP9-46919 1997-02-17
JP10051537A JPH10289923A (ja) 1997-02-17 1998-02-17 半導体パッケージの製造方法

Publications (2)

Publication Number Publication Date
JPH10289923A true JPH10289923A (ja) 1998-10-27
JPH10289923A5 JPH10289923A5 (enExample) 2005-08-25

Family

ID=26387070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10051537A Pending JPH10289923A (ja) 1997-02-17 1998-02-17 半導体パッケージの製造方法

Country Status (1)

Country Link
JP (1) JPH10289923A (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001011677A1 (en) * 1999-08-09 2001-02-15 Rohm Co., Ltd. Method for manufacturing semiconductor device
KR100328834B1 (ko) * 1999-09-11 2002-03-14 박종섭 웨이퍼 레벨 칩사이즈 패키지의 제조방법
KR20020057358A (ko) * 2001-01-04 2002-07-11 마이클 디. 오브라이언 멀티칩 모듈 패키지 및 제조방법
US7723839B2 (en) 2005-06-10 2010-05-25 Sharp Kabushiki Kaisha Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device
CN119786357A (zh) * 2024-12-12 2025-04-08 中山大学 一种功率模块及其制造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001011677A1 (en) * 1999-08-09 2001-02-15 Rohm Co., Ltd. Method for manufacturing semiconductor device
US6537858B1 (en) 1999-08-09 2003-03-25 Rohm Co., Ltd. Method for manufacturing semiconductor device
KR100725319B1 (ko) * 1999-08-09 2007-06-07 로무 가부시키가이샤 반도체장치의 제조방법
KR100328834B1 (ko) * 1999-09-11 2002-03-14 박종섭 웨이퍼 레벨 칩사이즈 패키지의 제조방법
KR20020057358A (ko) * 2001-01-04 2002-07-11 마이클 디. 오브라이언 멀티칩 모듈 패키지 및 제조방법
US7723839B2 (en) 2005-06-10 2010-05-25 Sharp Kabushiki Kaisha Semiconductor device, stacked semiconductor device, and manufacturing method for semiconductor device
CN119786357A (zh) * 2024-12-12 2025-04-08 中山大学 一种功率模块及其制造方法

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