JPH10284544A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

Info

Publication number
JPH10284544A
JPH10284544A JP9092609A JP9260997A JPH10284544A JP H10284544 A JPH10284544 A JP H10284544A JP 9092609 A JP9092609 A JP 9092609A JP 9260997 A JP9260997 A JP 9260997A JP H10284544 A JPH10284544 A JP H10284544A
Authority
JP
Japan
Prior art keywords
semiconductor device
package substrate
semiconductor chip
semiconductor
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9092609A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10284544A5 (enExample
Inventor
Chuichi Miyazaki
忠一 宮崎
Ichiro Anjo
一郎 安生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9092609A priority Critical patent/JPH10284544A/ja
Publication of JPH10284544A publication Critical patent/JPH10284544A/ja
Publication of JPH10284544A5 publication Critical patent/JPH10284544A5/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
JP9092609A 1997-04-10 1997-04-10 半導体装置およびその製造方法 Pending JPH10284544A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9092609A JPH10284544A (ja) 1997-04-10 1997-04-10 半導体装置およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9092609A JPH10284544A (ja) 1997-04-10 1997-04-10 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
JPH10284544A true JPH10284544A (ja) 1998-10-23
JPH10284544A5 JPH10284544A5 (enExample) 2005-02-24

Family

ID=14059187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9092609A Pending JPH10284544A (ja) 1997-04-10 1997-04-10 半導体装置およびその製造方法

Country Status (1)

Country Link
JP (1) JPH10284544A (enExample)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340736A (ja) * 1999-05-26 2000-12-08 Sony Corp 半導体装置及びその実装構造、並びにこれらの製造方法
JP2002170905A (ja) * 2000-12-01 2002-06-14 Toppan Printing Co Ltd 配線回路基板
US6611063B1 (en) 1999-09-16 2003-08-26 Nec Electronics Corporation Resin-encapsulated semiconductor device
JP2006237324A (ja) * 2005-02-25 2006-09-07 Seiko Epson Corp 半導体装置及びその製造方法
CN100345268C (zh) * 2004-03-19 2007-10-24 尔必达存储器株式会社 半导体装置
JP2008211201A (ja) * 2007-02-01 2008-09-11 Ngk Spark Plug Co Ltd 配線基板、半導体パッケージ
JP2009038391A (ja) * 2001-02-27 2009-02-19 Chippac Inc 超薄型高速フリップチップパッケージ
JP2009100004A (ja) * 2008-12-24 2009-05-07 Oki Semiconductor Co Ltd 半導体装置の製造方法
JP2009124176A (ja) * 2001-02-01 2009-06-04 Fairchild Semiconductor Corp 半導体デバイス用非モールドパッケージ
JP2011082293A (ja) * 2009-10-06 2011-04-21 Shinko Electric Ind Co Ltd インターポーザ実装配線基板及び電子部品装置
JP2012033969A (ja) * 2011-10-31 2012-02-16 Lapis Semiconductor Co Ltd 半導体装置の製造方法
US8143108B2 (en) 2004-10-07 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
USRE44438E1 (en) 2001-02-27 2013-08-13 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000340736A (ja) * 1999-05-26 2000-12-08 Sony Corp 半導体装置及びその実装構造、並びにこれらの製造方法
US6611063B1 (en) 1999-09-16 2003-08-26 Nec Electronics Corporation Resin-encapsulated semiconductor device
JP2002170905A (ja) * 2000-12-01 2002-06-14 Toppan Printing Co Ltd 配線回路基板
JP2009124176A (ja) * 2001-02-01 2009-06-04 Fairchild Semiconductor Corp 半導体デバイス用非モールドパッケージ
US8941235B2 (en) 2001-02-27 2015-01-27 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
JP2009038391A (ja) * 2001-02-27 2009-02-19 Chippac Inc 超薄型高速フリップチップパッケージ
USRE44438E1 (en) 2001-02-27 2013-08-13 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
CN100345268C (zh) * 2004-03-19 2007-10-24 尔必达存储器株式会社 半导体装置
US8143108B2 (en) 2004-10-07 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
JP2006237324A (ja) * 2005-02-25 2006-09-07 Seiko Epson Corp 半導体装置及びその製造方法
JP2008211201A (ja) * 2007-02-01 2008-09-11 Ngk Spark Plug Co Ltd 配線基板、半導体パッケージ
JP2009100004A (ja) * 2008-12-24 2009-05-07 Oki Semiconductor Co Ltd 半導体装置の製造方法
JP2011082293A (ja) * 2009-10-06 2011-04-21 Shinko Electric Ind Co Ltd インターポーザ実装配線基板及び電子部品装置
JP2012033969A (ja) * 2011-10-31 2012-02-16 Lapis Semiconductor Co Ltd 半導体装置の製造方法

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