JPH10256702A - Manufacture of ceramic board - Google Patents

Manufacture of ceramic board

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Publication number
JPH10256702A
JPH10256702A JP7657597A JP7657597A JPH10256702A JP H10256702 A JPH10256702 A JP H10256702A JP 7657597 A JP7657597 A JP 7657597A JP 7657597 A JP7657597 A JP 7657597A JP H10256702 A JPH10256702 A JP H10256702A
Authority
JP
Japan
Prior art keywords
pattern
plating
patterns
inspection
land
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7657597A
Other languages
Japanese (ja)
Inventor
Noboru Kubo
昇 久保
Hideyo Kawaguchi
英世 河口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal SMI Electronics Device Inc
Original Assignee
Sumitomo Metal SMI Electronics Device Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal SMI Electronics Device Inc filed Critical Sumitomo Metal SMI Electronics Device Inc
Priority to JP7657597A priority Critical patent/JPH10256702A/en
Publication of JPH10256702A publication Critical patent/JPH10256702A/en
Pending legal-status Critical Current

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  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a plurality of ceramic boards for plating simultaneously the patterns of the ceramic boards, while suppressing the variations of their plating thicknesses. SOLUTION: A method of manufacturing ceramic boards has first and second processes. In the first process, connecting successively the ending point of a pattern 21 of a ceramic board belonging to each column in series with the starting point of the pattern 21 of the ceramic board following it, there are formed a paralleling pattern 23 for connecting in parallel with each other starting points 213 of the patterns 21 of the first boards belonging to the respective columns, a paralleling pattern 24 for connecting in parallel with each other ending points 214 of the patterns 21 of the final boards which belong to the respective columns, and inspecting lands 25 belonging to the respective columns, and then the patterns 21 of the boards are plated simultaneously by connecting both the paralleling patterns 23, 24 by a single power supply for plating. In the second process, after plating the patterns 21, cutting off each inspecting land 25 from the paralleling pattern 23, the presence of the current flowing through each land 25 and the paralleling pattern 24 is examined by applying different potentials from each other to both the portions to inspect the presence of any cutting in the patterns 21 connected in series with each inspecting land 25.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【技術分野】本発明は,複数のセラミック基板のパター
ンメッキを同時に実施するセラミック基板の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a ceramic substrate, which simultaneously performs pattern plating on a plurality of ceramic substrates.

【0002】[0002]

【従来技術】複数のセラミック基板を同時にパターンメ
ッキする場合には,図6に示すように,単一の基板91
上に上記セラミック基板のメッキ用パターン92をm行
n列(同図では5×5)に形成すると共に同一列に位置
するメッキ用パターン92のパターン終点922を次の
パターン92のパターン始点921に次々と連結パター
ン931により直列に接続する。そして,直列に接続し
た列の端部に位置する行のメッキ用パターン92の最端
の終点924(又は始点)を並列化パターン932によ
り連結し,並列化パターン932を図8に示すメッキ用
電源94のカソード側に接続してパターン92にメッキ
を形成する。図8において,符合96はメッキする金属
プレートである。
2. Description of the Related Art When a plurality of ceramic substrates are simultaneously subjected to pattern plating, as shown in FIG.
On the above, the plating patterns 92 of the ceramic substrate are formed in m rows and n columns (5 × 5 in the figure), and the pattern end point 922 of the plating pattern 92 located in the same column is set as the pattern start point 921 of the next pattern 92. One after another, they are connected in series by a connection pattern 931. Then, the end point 924 (or the start point) of the plating pattern 92 in the row located at the end of the column connected in series is connected by the parallel pattern 932, and the parallel pattern 932 is connected to the plating power source shown in FIG. The plating is formed on the pattern 92 by connecting to the cathode side of 94. In FIG. 8, reference numeral 96 denotes a metal plate to be plated.

【0003】そして,図7に示すように,直列に接続し
た列の端部に位置する行のパターン92の最端の始点9
23と並列化パターン932とをそれぞれ電源941の
異なった電位に接続し,最端始点923と並列化パター
ン932との間に流れる電流の有無により直列に接続し
たパターン92のいずれかにパターン切断が無いかどう
かを検査する。即ち,直列に接続したパターン92のい
ずれかにパターン切断がある場合には電流が流れないか
ら,これによってパターン不良(切断)を検知すること
ができる。そして,スイッチ99を切り換えて,すべて
の列のパターンを順次検査する。
[0003] As shown in FIG. 7, the start point 9 of the end of the pattern 92 of the row located at the end of the column connected in series
23 and the parallel pattern 932 are connected to different potentials of the power supply 941, respectively, and the pattern is cut to one of the patterns 92 connected in series depending on the presence or absence of a current flowing between the extreme start point 923 and the parallel pattern 932. Inspect for presence. That is, when there is a pattern cut in any of the patterns 92 connected in series, no current flows, so that a pattern defect (cut) can be detected. Then, the switch 99 is switched to sequentially inspect the patterns of all the columns.

【0004】[0004]

【解決しようとする課題】しかしながら,上記従来のパ
ターンメッキの方法は,図7に示すように,パターンメ
ッキ後におけるパターン切断の検査が容易であるという
利点があるが,メッキ厚さが不均一になりやすいという
問題がある。即ち,並列化パターン932(電源側)か
ら最端始点923(終端側)に近づくにつれて,メッキ
電流(従って電位)が減少するから,図5の左側の棒グ
ラフ971〜977に示すように,メッキの厚さが並列
化パターン932(電源側)からの距離と共に漸減す
る。
However, as shown in FIG. 7, the conventional method of pattern plating has an advantage that the inspection of pattern cutting after pattern plating is easy, but the plating thickness is not uniform. There is a problem that it is easy to become. That is, as the plating current (and thus the potential) decreases as the position approaches the extreme start point 923 (end side) from the parallelized pattern 932 (power supply side), as shown in the bar graphs 971 to 977 on the left side of FIG. The thickness gradually decreases with the distance from the parallelization pattern 932 (the power supply side).

【0005】本発明は,かかる従来の問題点に鑑みてな
されたものであり,メッキ厚さのばらつきを抑制しつつ
複数のセラミック基板を同時にパターンメッキすること
ができ,かつパターンの切断不良を容易に検査すること
のできるセラミック基板の製造方法を提供しようとする
ものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and it is possible to simultaneously perform pattern plating on a plurality of ceramic substrates while suppressing variations in plating thickness, and to easily perform pattern cutting defects. It is an object of the present invention to provide a method of manufacturing a ceramic substrate which can be inspected in a short time.

【0006】[0006]

【課題の解決手段】本願の発明は,同一の配線パターン
を有する複数のセラミック基板のパターンメッキを同時
に形成するセラミック基板の製造方法であって,単一の
基板上に上記セラミック基板のメッキ用パターンをm行
n列に形成すると共に同一行又は列に位置するメッキ用
パターンのパターン終点を次のパターン始点に次々と連
結パターンにより直列に接続し,直列に接続した行又は
列の両端部に位置する列または行のメッキ用パターンの
最端の始点間及び最端の終点間をそれそれ連結する並列
化パターンを設けると共に上記並列化パターンと各最端
始点間又は上記並列化パターンと各最端終点との間には
検査用のランドを形成し,上記並列化パターンの両方を
同一のメッキ用電源に接続してパターンのメッキを行う
第1の工程と,上記パターンメッキ後において,上記並
列化パターンと検査用のランドとの間をパターン切断
し,検査用のランドと他方の並列用パターンとをそれぞ
れ異なった電位に接続し両部間に流れる電流の有無によ
りその検査用のランドに直列に接続されたパターンの切
断の有無を検査する第2の工程と,上記検査後におい
て,m×n個の単一のセラミック基板のパターンに分割
する第3の工程とを有していることを特徴とするセラミ
ック基板の製造方法にある。
The invention of the present application is a method of manufacturing a ceramic substrate in which pattern plating of a plurality of ceramic substrates having the same wiring pattern is simultaneously formed, wherein the pattern for plating the ceramic substrate is formed on a single substrate. Are formed in m rows and n columns and the pattern end points of the plating patterns located in the same row or column are connected in series to the next pattern start point one after another by a connection pattern, and are located at both ends of the serially connected rows or columns. A parallel pattern is provided to connect between the most extreme start points and the most extreme end points of the plating pattern of the column or row, and between the parallel pattern and each extreme start point or the parallel pattern and each extreme. A first step of forming a test land between the end point and connecting both of the parallelized patterns to the same plating power source to perform pattern plating; After pattern plating, the pattern is cut between the parallelized pattern and the inspection land, the inspection land and the other parallel pattern are connected to different potentials, and the presence or absence of a current flowing between both parts is determined. A second step of inspecting whether or not a pattern connected in series to the inspection land is cut, and a third step of dividing the pattern into m × n single ceramic substrate patterns after the inspection. And a method for manufacturing a ceramic substrate.

【0007】本発明ににおいて特に注目すべきことの第
一点は,行又は列の両端部に位置する列または行のメッ
キ用パターンの最端の始点及び最端の終点を並列化パタ
ーンにより接続し,両方の並列化パターンを同一のメッ
キ用電源に接続してパターンのメッキを行うことであ
る。最端の始点間及び最端の終点間をそれそれ並列化パ
ターンで連結してあるから,メッキ電源とは2点(並列
化パターン)で接続すればよく,メッキ作業は容易であ
る(図1参照)。
The first point of particular interest in the present invention is that the most extreme start point and the most extreme end point of a plating pattern in a column or row located at both ends of a row or column are connected by a parallel pattern. Then, both parallel patterns are connected to the same plating power source to perform pattern plating. Since the end start points and the end end points are connected in parallel patterns, the plating power supply may be connected at two points (parallel patterns), and the plating operation is easy (FIG. 1). reference).

【0008】そして,従来の方法と異なり,最端の始点
及び最端の終点の両側を同一のメッキ用電源に接続して
パターンメッキを行う。従って,従来の方法では最大の
電位差を生ずる最端の始点及び最端の終点は,本発明の
方法では同電位となる。そして,電位の最も低い点(メ
ッキ電流の最も少なくなる点)は,本発明の方法では両
最端点の中間の点となり,従来方法の1/2の距離とな
る。
[0008] Unlike the conventional method, both sides of the extreme end start point and extreme end point are connected to the same plating power source to perform pattern plating. Therefore, the extreme start point and extreme end point that produce the maximum potential difference in the conventional method have the same potential in the method of the present invention. In the method of the present invention, the point having the lowest potential (ie, the point at which the plating current is minimized) is an intermediate point between the two extreme points, and is a half distance as compared with the conventional method.

【0009】従って,メッキ形成時における基板上のパ
ターン間の最大電位差(従ってメッキ電流差,メッキ厚
の差)は,従来方法の1/2に減少し,メッキ厚さの差
の最大値は半減する(図5参照)。言い換えれば,従来
と同じメッキ厚のばらつきを許容するならば,1工程で
従来の2倍の枚数を同時に製造することが可能となる。
Therefore, the maximum potential difference between the patterns on the substrate at the time of plating (accordingly, the difference in plating current and the difference in plating thickness) is reduced to half of the conventional method, and the maximum value of the difference in plating thickness is halved. (See FIG. 5). In other words, if the same variation in the plating thickness as in the prior art is allowed, it is possible to simultaneously manufacture twice the number of sheets in one process.

【0010】そして,本発明ににおいて特に注目すべき
ことの第二点は,並列化パターンと各最端始点間又は上
記並列化パターンと各最端終点との間には検査用のラン
ドを形成し,パターンメッキ後において,上記並列化パ
ターンと検査用のランドとの間をパターン切断し,検査
用のランドと他方の並列用パターンとをそれぞれ異なっ
た電位に接続し両部間に流れる電流の有無によりその検
査用のランドに直列に接続されたパターンの切断の有無
を検査することである。
A second point of particular interest in the present invention is that a land for inspection is formed between the parallelized pattern and each of the extreme start points or between the parallelized pattern and each of the extreme end points. After pattern plating, the pattern is cut between the parallel pattern and the inspection land, the inspection land and the other parallel pattern are connected to different potentials, and the current flowing between the two parts is reduced. The presence / absence is to inspect whether the pattern connected in series to the inspection land is cut or not.

【0011】即ち,並列化パターンと各最端点の一方と
の間に検査用のランドを形成してあるから,パターンの
検査においては並列化パターンと検査用のランドとの間
を,基板をブレークするなどの方法によりパターン切断
し,上記検査用のランドと他方の並列用パターンとをそ
れぞれ異なった電位に接続することにより,従来と同様
にパターンの切断検査を容易に行うことができる(図
3,図7参照)。
That is, since an inspection land is formed between the parallel pattern and one of the end points, the substrate is broken between the parallel pattern and the inspection land during pattern inspection. By cutting the pattern by such a method as described above, and connecting the above-mentioned inspection land and the other parallel pattern to different potentials, the pattern cutting inspection can be easily performed as in the conventional case (FIG. 3). , FIG. 7).

【0012】検査用ランドと直列に接続したパターンの
いずれかにパターン切断がある場合には,検査用のラン
ドと並列化パターン間に電流が流れないから,検査用の
ランド毎,即ち検査用ランドにつながる列又は行毎にパ
ターン不良(切断)を容易に検知することができる。上
記のように,本発明によればメッキ厚さのばらつきを抑
制しつつ複数のセラミック基板を同時にパターンメッキ
することができ,かつパターンの切断不良を容易に検査
することができる。
If there is a pattern cut in any of the patterns connected in series with the inspection land, no current flows between the inspection land and the parallelized pattern. , A pattern defect (cut) can be easily detected for each column or row. As described above, according to the present invention, a plurality of ceramic substrates can be subjected to pattern plating at the same time while suppressing variations in plating thickness, and a pattern cutting defect can be easily inspected.

【0013】[0013]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

実施形態例 本例は,図1〜図4に示すように,同一の配線パターン
11(図4)を有する複数のセラミック基板10(図
4)のパターンメッキを同時に形成するセラミック基板
の製造方法である。即ち,第1の工程では,図1に示す
ように,単数又は複数のセラミックグリーンシートに導
体ペーストで配線パターンをスクリーン印刷し,必要に
応じて複数枚を積層することで,単一の基板31上に前
記セラミック基板10のメッキ用パターン21をm行n
列(m=n=5)に形成すると共に同一列に位置するメ
ッキ用パターン21のパターン終点212を次のパター
ン21の始点211に次々と連結パターン22により直
列に接続し,直列に接続した列の両端部に位置する行の
メッキ用パターンの最端の始点213間及び最端の終点
214間をそれそれ連結する並列化パターン23,24
を設けると共に一方の並列化パターン23と各最端始点
213間との間には検査用のランド25を形成し,焼成
した後,並列化パターン23,24の両方を同一のメッ
キ用電源94に接続してパターンのメッキを行う。
Embodiment This embodiment is, as shown in FIGS. 1 to 4, a method of manufacturing a ceramic substrate in which pattern plating of a plurality of ceramic substrates 10 (FIG. 4) having the same wiring pattern 11 (FIG. 4) is simultaneously formed. is there. That is, in the first step, as shown in FIG. 1, a wiring pattern is screen-printed on one or more ceramic green sheets with a conductive paste and, if necessary, a plurality of sheets are laminated to form a single substrate 31. The plating pattern 21 of the ceramic substrate 10 is formed on m rows and n rows.
A row formed in a row (m = n = 5) and connected in series with a pattern end point 212 of the plating pattern 21 located in the same row to a start point 211 of the next pattern 21 one after another by a connection pattern 22. Parallelized patterns 23 and 24 connecting between the extreme end points 213 and the extreme end points 214 of the plating patterns in the rows located at both ends of the pattern.
And an inspection land 25 is formed between one of the parallelized patterns 23 and each of the extreme start points 213, and after firing, both the parallelized patterns 23 and 24 are connected to the same plating power source 94. Connect and perform pattern plating.

【0014】続くパターンメッキ後の第2の工程では,
始めに,図2に示すように,並列化パターン23と検査
用のランド25との間を,基板31の端部をブレークす
る方法などによりパターン切断する。続いて,図3に示
すように,単一の検査用のランド25と他方の並列用パ
ターン24とをそれぞれ異なった電位(電源42の正
負)に接続し両部間に流れる電流の有無によりその検査
用のランドに直列に接続されたパターンの切断の有無を
検査する。そして,次々とすべての検査用のランド25
について,同様の検査を実施する。そして,上記検査後
において,続く第3の工程では,図4に示すように,5
×5個の単一のセラミック基板10に切断し分割する。
In the subsequent second step after pattern plating,
First, as shown in FIG. 2, the pattern between the parallel pattern 23 and the inspection land 25 is cut by a method of breaking the end of the substrate 31 or the like. Subsequently, as shown in FIG. 3, the single inspection land 25 and the other parallel pattern 24 are connected to different potentials (positive or negative of the power source 42), respectively, and the presence or absence of a current flowing between the two parts is determined by the presence or absence of the current. An inspection is performed to determine whether or not a pattern connected in series to the inspection land is disconnected. Then, all the inspection lands 25 one after another.
The same inspection is conducted for Then, after the above inspection, in the subsequent third step, as shown in FIG.
It is cut and divided into × 5 single ceramic substrates 10.

【0015】本例の第1工程では,図1に示すように,
最端の始点213間及び最端の終点間214をそれそれ
並列化パターン23又は24で連結してあるから,メッ
キ用の電源94とは2点(並列化パターン23,24)
で接続すればよく,メッキ作業は容易である。そして,
最端の始点213及び最端の終点214の両方を電源9
4の同一の電位に接続してパターンメッキを行う。
In the first step of this embodiment, as shown in FIG.
Since the endmost start point 213 and the endmost end point 214 are connected by the parallel pattern 23 or 24, respectively, the plating power source 94 is two points (parallel patterns 23 and 24).
The plating work is easy. And
Both the extreme start point 213 and extreme end point 214 are powered by power 9
4 and connected to the same potential to perform pattern plating.

【0016】従って,メッキ時にメッキ電源に対して電
位が最も低くなる点(即ちメッキ電流の最も少なくなる
点)は,本例では両最端点213,214の中間の点と
なり,図6に示した従来方法の1/2の距離の地点とな
る。従って,メッキ形成時における基板31上のパター
ン21間の最大電位差(従ってメッキ電流差,即ちメッ
キ厚の差異)は,従来方法の1/2に減少する。
Therefore, the point at which the potential is the lowest with respect to the plating power supply during plating (that is, the point at which the plating current is minimized) is an intermediate point between the extreme ends 213 and 214 in this example, and is shown in FIG. This is a point at half the distance of the conventional method. Therefore, the maximum potential difference between the patterns 21 on the substrate 31 during the plating process (therefore, the plating current difference, that is, the plating thickness difference) is reduced to half of the conventional method.

【0017】即ち,図5の符号61及び67と符号64
の棒グラフとの間の落差が示すように,従来の方法によ
る場合の符合971と977との間の差に対して,メッ
キ厚さの差の最大値は半減する。言い換えれば,従来と
同じメッキ厚のばらつき(符合971と977との間の
差)を許容するならば,1工程で従来の2倍の枚数(1
0行×5列)を同時に製造することが可能となる。
That is, reference numerals 61 and 67 and reference numeral 64 in FIG.
The maximum value of the plating thickness difference is halved with respect to the difference between the reference numerals 971 and 977 in the case of the conventional method, as shown by the difference between the bar graphs of FIG. In other words, if the same variation in plating thickness (difference between 971 and 977) as in the prior art is allowed, the number of sheets (1
(0 rows × 5 columns) can be manufactured simultaneously.

【0018】また,第2工程では,図3に示すように,
検査用のランド25と他方の並列化パターン24とをそ
れぞれ異なった電位に接続することにより,従来と同様
にパターン21の切断検査を容易に行うことができる。
即ち,検査用ランド25と直列に接続したパターン21
のいずれかにパターン切断がある場合には,検査用のラ
ンド25と並列化パターン24間に電流が流れない。従
って,切換スイッチ41を順次切り換えて検査用のラン
ド25と並列化パターン24との間に電圧を印加し,検
査用のランド25毎に,検査用ランド25につながる列
毎にパターン不良(切断)を容易に検知することができ
る。なお,セラミック基板としては,アルミナ(Al2
3 ),窒化アルミニウム(AlN),ガラスセラミッ
ク等のいずれを用いてもよく,それらに使用される導体
ペーストはそれぞれのセラミック焼成温度で選択でき
る。また,メッキは,Ni,Au,Cuメッキ等のいず
れにも適用できる。
In the second step, as shown in FIG.
By connecting the inspection land 25 and the other parallelized pattern 24 to different potentials, the cutting inspection of the pattern 21 can be easily performed as in the related art.
That is, the pattern 21 connected in series with the inspection land 25.
If any one of the patterns has a pattern cut, no current flows between the inspection land 25 and the parallelized pattern 24. Therefore, by sequentially switching the changeover switch 41, a voltage is applied between the inspection land 25 and the parallelized pattern 24, and a pattern failure (cutting) occurs for each inspection land 25 and each column connected to the inspection land 25. Can be easily detected. As the ceramic substrate, alumina (Al 2
O 3), aluminum nitride (AlN), may be any one of a glass ceramic or the like, the conductive paste used to them can be selected in each of the ceramic sintering temperature. The plating can be applied to any of Ni, Au, Cu plating and the like.

【0019】[0019]

【発明の効果】上記のように,本発明によれば,メッキ
厚さのばらつきを抑制しつつ複数のセラミック基板を同
時にパターンメッキすることができ,かつパターンの切
断不良を容易に検査することのできるセラミック基板の
製造方法を得ることができる。
As described above, according to the present invention, it is possible to pattern-plate a plurality of ceramic substrates simultaneously while suppressing variations in plating thickness, and to easily inspect a pattern for cutting defects. Thus, a method for manufacturing a ceramic substrate that can be obtained can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施形態例の製造方法におけるメッキ工程時の
メッキ電源と基板との接続態様を示す図。
FIG. 1 is a diagram showing a connection mode between a plating power supply and a substrate during a plating step in a manufacturing method according to an embodiment.

【図2】実施形態例の製造方法における検査工程の前処
理としての基板の切断の態様を示す図。
FIG. 2 is a view showing an aspect of cutting a substrate as a pretreatment of an inspection step in the manufacturing method of the embodiment.

【図3】実施形態例の製造方法における検査工程時の検
査用電源と基板との接続態様を示す図。
FIG. 3 is a view showing a connection state between an inspection power supply and a substrate during an inspection step in the manufacturing method of the embodiment.

【図4】実施形態例の製造方法におけるセラミック基板
の切断の態様を示す図。
FIG. 4 is a view showing a mode of cutting the ceramic substrate in the manufacturing method of the embodiment.

【図5】実施形態例の方法による場合(符合61〜6
7)と従来の方法による場合(符合971〜977)の
メッキ厚の差を示す図。
FIG. 5 shows a case according to the method of the embodiment (reference numerals 61 to 6).
FIG. 7 is a diagram showing a difference in plating thickness between the case 7) and the case of the conventional method (reference numerals 971 to 977).

【図6】従来の製造方法におけるメッキ工程時のメッキ
電源と基板との接続態様を示す図。
FIG. 6 is a diagram showing a connection mode between a plating power supply and a substrate during a plating step in a conventional manufacturing method.

【図7】従来の製造方法における検査工程時のメッキ電
源と基板との接続態様を示す図。
FIG. 7 is a diagram showing a connection mode between a plating power supply and a substrate during an inspection step in a conventional manufacturing method.

【図8】メッキ工程における電気的な接続態様を模式的
に示す図。
FIG. 8 is a diagram schematically showing an electrical connection mode in a plating step.

【符号の説明】[Explanation of symbols]

21...パターン, 213...最端の始点, 214...最端の終点, 23,24...並列化パターン, 25...検査用ランド, 21. . . Pattern, 213. . . End-most starting point, 214. . . End point 23, 24. . . Parallelization pattern, 25. . . Inspection land,

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 同一の配線パターンを有する複数のセラ
ミック基板のパターンメッキを同時に形成するセラミッ
ク基板の製造方法であって,単一の基板上に上記セラミ
ック基板のメッキ用パターンをm行n列に形成すると共
に同一行又は列に位置するメッキ用パターンのパターン
終点を次のパターン始点に次々と連結パターンにより直
列に接続し,直列に接続した行又は列の両端部に位置す
る列または行のメッキ用パターンの最端の始点間及び最
端の終点間をそれそれ連結する並列化パターンを設ける
と共に上記並列化パターンと各最端始点間又は上記並列
化パターンと各最端終点との間には検査用のランドを形
成し,上記並列化パターンの両方を同一のメッキ用電源
に接続してパターンのメッキを行う第1の工程と,上記
パターンメッキ後において,上記並列化パターンと検査
用のランドとの間をパターン切断し,検査用のランドと
他方の並列用パターンとをそれぞれ異なった電位に接続
し両部間に流れる電流の有無によりその検査用のランド
に直列に接続されたパターンの切断の有無を検査する第
2の工程と,上記検査後において,m×n個の単一のセ
ラミック基板のパターンに分割する第3の工程とを有し
ていることを特徴とするセラミック基板の製造方法。
1. A method of manufacturing a ceramic substrate, comprising simultaneously forming a pattern plating of a plurality of ceramic substrates having the same wiring pattern, wherein the plating patterns of the ceramic substrate are arranged in m rows and n columns on a single substrate. The plating end points of the plating patterns formed and located on the same row or column are connected in series to the next pattern starting point one after another by a connection pattern, and the plating of columns or rows located at both ends of the serially connected rows or columns is performed. A parallel pattern is provided to connect between the end points of the end of the application pattern and between the end points of the end, and between the parallel pattern and each of the end start points or between the parallel pattern and each of the end end points. A first step of forming inspection lands and connecting both of the parallelized patterns to the same plating power source to perform pattern plating; and The pattern is cut between the parallel pattern and the inspection land, the inspection land and the other parallel pattern are connected to different potentials, and the inspection is performed based on the presence or absence of a current flowing between both parts. A second step of inspecting whether or not a pattern connected in series to the land for use is cut, and a third step of dividing the pattern into m × n single ceramic substrate patterns after the inspection. A method of manufacturing a ceramic substrate.
JP7657597A 1997-03-11 1997-03-11 Manufacture of ceramic board Pending JPH10256702A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7657597A JPH10256702A (en) 1997-03-11 1997-03-11 Manufacture of ceramic board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7657597A JPH10256702A (en) 1997-03-11 1997-03-11 Manufacture of ceramic board

Publications (1)

Publication Number Publication Date
JPH10256702A true JPH10256702A (en) 1998-09-25

Family

ID=13609064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7657597A Pending JPH10256702A (en) 1997-03-11 1997-03-11 Manufacture of ceramic board

Country Status (1)

Country Link
JP (1) JPH10256702A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009141228A (en) * 2007-12-10 2009-06-25 Panasonic Corp Board for wiring, semiconductor device for stacking using the same, and stacked type semiconductor module
CN102014580A (en) * 2010-11-24 2011-04-13 深南电路有限公司 Manufacturing technology of whole-plate gold-plated plate
CN102014583A (en) * 2010-11-24 2011-04-13 深南电路有限公司 Process for manufacturing whole gold-plated board
CN102014584A (en) * 2010-11-24 2011-04-13 深南电路有限公司 Process for manufacturing whole gold-plated board
CN102056417A (en) * 2010-11-24 2011-05-11 深南电路有限公司 Process for manufacturing partially gold-plated board
CN102076175A (en) * 2010-11-24 2011-05-25 深南电路有限公司 Full gold-plated board manufacturing technology
JP2014236154A (en) * 2013-06-04 2014-12-15 富士通株式会社 Electronic device, inspection method and wiring board

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009141228A (en) * 2007-12-10 2009-06-25 Panasonic Corp Board for wiring, semiconductor device for stacking using the same, and stacked type semiconductor module
CN102014580A (en) * 2010-11-24 2011-04-13 深南电路有限公司 Manufacturing technology of whole-plate gold-plated plate
CN102014583A (en) * 2010-11-24 2011-04-13 深南电路有限公司 Process for manufacturing whole gold-plated board
CN102014584A (en) * 2010-11-24 2011-04-13 深南电路有限公司 Process for manufacturing whole gold-plated board
CN102056417A (en) * 2010-11-24 2011-05-11 深南电路有限公司 Process for manufacturing partially gold-plated board
CN102076175A (en) * 2010-11-24 2011-05-25 深南电路有限公司 Full gold-plated board manufacturing technology
JP2014236154A (en) * 2013-06-04 2014-12-15 富士通株式会社 Electronic device, inspection method and wiring board

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