CN102014584A - Process for manufacturing whole gold-plated board - Google Patents
Process for manufacturing whole gold-plated board Download PDFInfo
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- CN102014584A CN102014584A CN 201010557163 CN201010557163A CN102014584A CN 102014584 A CN102014584 A CN 102014584A CN 201010557163 CN201010557163 CN 201010557163 CN 201010557163 A CN201010557163 A CN 201010557163A CN 102014584 A CN102014584 A CN 102014584A
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- gold
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- internal layer
- wire
- auxiliary frame
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Abstract
The invention discloses a process for manufacturing a whole gold-plated board. The process comprises the following steps: a. manufacturing inner layer leads on the inner layer of a circuit board; b. making all the patterns in the board and a conductive auxiliary frame on the surface of the outer layer of the circuit board once; c. adopting the inner layer leads as the gold-plated leads to plate gold on the gold-plated areas on the circuit board; and d. removing the conductive auxiliary frame to ensure the gold-plated areas to insulate each other, wherein the patterns in the board are provided with the gold-plated areas; one end of the inner layer leads is electrically conducted with the gold-plated areas and the other end thereof is electrically conducted with the conductive auxiliary frame; and all the gold-plated areas are electrically conducted with the conductive auxiliary frame via the inner layer leads. The process has the following advantages: the problems of seepage plating, incomplete etching and collapse of gold-plated surfaces are solved; the gold-plated patterns have high precision; and the inner layer leads are not manufactured through independent working procedure but are passingly manufactured while manufacturing the patterns on the inner layer of the circuit board, thus not adding the flow.
Description
Technical field
The present invention relates to a kind of manufacture craft of full plate coated plate.
Background technology
The manufacture craft of existing full plate coated plate adopts the preceding craft of gilding of figure, its technological process is as follows: blanking-internal layer processing-lamination-boring-heavy copper-plating-outer graphics (is made glodclad wire with big copper face, with gold-plated zone develop out carry out gold-plated)-full plate is gold-plated-outer alkaline etching (remove all dry films, etch away non-gold-plated zone)-outer inspection-welding resistance-character-surface-coated-profile-electrical measurement-one-tenth inspection-packing.
Yet technology has following defective before the figure:
A. easy gold-plated plating and etching are unclean: with big copper face as glodclad wire, cover non-gold-plated zone because there are certain problem in dry film and copper face adhesion with dry film, when gold-plated, dry film comes off or liquid medicine infiltrates under the dry film easily easily around the gold-plated zone, cause with the big copper face that is connected around the gold-plated zone plating gold to occur, it is unclean because of gold-plated etching to occur gold-plated regional copper face when etching easily;
B. gold plating quality is poor, occurs gold-plated zone easily and subsides: gold-plated peripheral region is because be connected with the copper layer, and when losing in the etched plate figure outside carrying out, the copper layer that occurs easily below the Gold plated Layer is snapped eating away, gilding occurs and subsides.
Summary of the invention
The technical problem that the present invention mainly solves provides a kind of manufacture craft of full plate coated plate, the defective that this technology can overcome that gold-plated plating, etching are clean, gold plating quality difference and gold-plated zone subside.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: a kind of manufacture craft of full plate coated plate is provided, may further comprise the steps:.
A. produce the internal layer lead-in wire at the circuit board internal layer;
B. on the outer field surface of circuit board once property make in all plates with gold-plated zone figure and the auxiliary frame of conduction, a go between end and gold-plated zone of described internal layer conducts, the other end conducts with the auxiliary frame of conduction, and all gold-plated zones conduct mutually by the auxiliary frame of internal layer lead-in wire and conduction;
C. utilize the internal layer lead-in wire to carry out gold-plated to gold-plated zone on the circuit board as glodclad wire;
D. remove the auxiliary frame of conduction, make mutually insulated between the gold-plated zone.
Wherein, in step b, on the coated plate skin, via is set, auxiliary frame of conduction and internal layer lead-in wire is conducted mutually by described via.
Wherein, in step a, the width of described internal layer lead-in wire is 0.08-0.2mm.
Wherein, in step a, described internal layer lead-in wire is arranged on the different internal layers.
Wherein, between step b and step c, also comprise step: to inspection outside figure carries out in all plates of making.
Wherein, between step b and step c, also comprise step: coated plate is carried out the welding resistance technological operation.
The invention has the beneficial effects as follows: the defective that the gold-plated plating, etching that is different from prior art is clean, gold plating quality difference and gold-plated zone subside, the present invention has following advantage:
The first, it is unclean to have solved gold-plated plating and etching: because this method is a internal layer by circuit board the internal layer lead-in wire is set, utilize the internal layer lead-in wire that the auxiliary frame of all gold-plated zones and conduction is coupled together, the disposable whole etchings of figure are come out in the outer field plate of circuit board, there is not big copper layer around it, so there is not the unclean problem of plating and etching.
The second, solved the problem that gold-plated golden face subsides: the internal layer lead-in wire is set because this method is a internal layer by circuit board, utilize the internal layer lead-in wire that the auxiliary frame of all gold-plated zones and conduction is coupled together, the disposable whole etchings of figure are come out in the outer field plate of circuit board, so around its gold-plated zone and side has all plated the nickel gold when gold-plated, so gilding can not subside.
Three, gold-plated pattern precision height: the internal layer lead-in wire is set because this method is a internal layer by circuit board, utilize the internal layer lead-in wire that the auxiliary frame of all gold-plated zones and conduction is coupled together, the disposable whole etchings of figure are come out in the outer field plate of circuit board, have higher precision so can guarantee gold-plated figure.
In addition because internal layer lead-in wire is not independent operation makes, but when making the circuitous pattern of internal layer, make, so can not increase flow process along band.
Description of drawings
Fig. 1 makes the gold-plated zone of internal layer lead-in wire, superficies and the coated plate schematic diagram behind the auxiliary frame of conduction in the embodiment of the invention;
Fig. 2 utilizes internal layer lead-in wire to carry out coated plate schematic diagram after gold-plated as glodclad wire in the embodiment of the invention;
Fig. 3 is the coated plate schematic diagram behind the auxiliary frame of mill off conduction in the embodiment of the invention.
Wherein, 1, gold-plated zone; 2, the auxiliary frame of conduction; 3, internal layer lead-in wire.
Embodiment
By describing technology contents of the present invention, structural feature in detail, realized purpose and effect, give explanation below in conjunction with execution mode and conjunction with figs. are detailed.
See also Fig. 1 to Fig. 3, the embodiment as the manufacture craft of the full plate coated plate of the present invention may further comprise the steps:
A. produce internal layer lead-in wire 3 at the circuit board internal layer;
B. on the outer field surface of circuit board once property make and have figure and the auxiliary frame 2 of conduction in all plates of gold-plated regional 1, described internal layer 3 one ends and gold-plated regional 1 that go between conduct, the other end conducts with the auxiliary frame 2 of conduction, and all gold-plated regional 1 conduct mutually by the auxiliary frame 2 of internal layer lead-in wire 3 and conduction;
C. utilize internal layer lead-in wire 3 as glodclad wire on the circuit board gold-plated regional 1 carry out gold-plated;
D. remove the auxiliary frame 2 of conduction, make gold-plated regional 1 between mutually insulated.
The defective that the gold-plated plating, etching that is different from prior art is clean, gold plating quality difference and gold-plated zone subside, the present invention has following advantage:
The first, it is unclean to have solved gold-plated plating and etching: because this method is a internal layer by circuit board internal layer lead-in wire 3 is set, utilize internal layer lead-in wire 3 that all gold-plated regional 1 are coupled together with the auxiliary frame 2 of conduction, the disposable whole etchings of figure are come out in the outer field plate of circuit board, there is not big copper layer around it, so there is not the unclean problem of plating and etching.
The second, solved the problem that gold-plated golden face subsides: internal layer lead-in wire 3 is set because this method is a internal layer by circuit board, utilize internal layer lead-in wire 3 that all gold-plated regional 1 are coupled together with the auxiliary frame 2 of conduction, the disposable whole etchings of figure are come out in the outer field plate of circuit board, so its around gold-plated regional 1 and side has all plated the nickel gold when gold-plated, so gilding can not subside.
Three, gold-plated pattern precision height: internal layer lead-in wire 3 is set because this method is a internal layer by circuit board, utilize internal layer lead-in wire 3 that all gold-plated regional 1 are coupled together with the auxiliary frame 2 of conduction, the disposable whole etchings of figure are come out in the outer field plate of circuit board, have higher precision so can guarantee gold-plated figure.
In addition because internal layer lead-in wire 3 is not independent operation makes, but when making the circuitous pattern of internal layer, make, so can not increase flow process along band.
In step b, on the coated plate skin, via is set, by described via auxiliary frame of conduction and internal layer lead-in wire are conducted mutually.
In another embodiment, remove and conduct electricity when assisting frame, adopt the mode that the auxiliary side milling of conduction is fallen.
In another embodiment, in step a, described internal layer lead-in wire can be arranged by any one deck in the circuit board internal layer, but the internal layer of preferentially selecting figure to evacuate, described internal layer lead-in wire can be arranged on the different internal layers, described internal layer wire widths is generally selected 0.08-0.2mm, and length is then not limited substantially.
In one embodiment, between step b and step c, also comprise step: to inspection outside figure carries out in all plates of making.
In one embodiment, between step b and step c, also comprise step: coated plate is carried out the welding resistance technological operation.
The above only is embodiments of the invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes specification of the present invention and accompanying drawing content to be done; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (6)
1. the manufacture craft of a full plate coated plate is characterized in that, may further comprise the steps:
A. produce the internal layer lead-in wire at the circuit board internal layer;
B. on the outer field surface of circuit board once property make in all plates with gold-plated zone figure and the auxiliary frame of conduction, a go between end and gold-plated zone of described internal layer conducts, the other end conducts with the auxiliary frame of conduction, and all gold-plated zones conduct mutually by the auxiliary frame of internal layer lead-in wire and conduction;
C. utilize the internal layer lead-in wire to carry out gold-plated to gold-plated zone on the circuit board as glodclad wire;
D. remove the auxiliary frame of conduction, make mutually insulated between the gold-plated zone.
2. the manufacture craft of full plate coated plate according to claim 1 is characterized in that: in step b, on the coated plate skin via is set, by described via auxiliary frame of conduction and internal layer lead-in wire is conducted mutually.
3. the manufacture craft of full plate coated plate according to claim 2 is characterized in that: in step a, the width of described internal layer lead-in wire is 0.08-0.2mm.
4. the manufacture craft of full plate coated plate according to claim 3 is characterized in that: in step a, described internal layer lead-in wire is arranged on the different internal layers.
5. the manufacture craft of full plate coated plate according to claim 4 is characterized in that: also comprise step between step b and step c: to inspection outside figure carries out in all plates of making.
6. the manufacture craft of full plate coated plate according to claim 5 is characterized in that: also comprise step between step b and step c: coated plate is carried out the welding resistance technological operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010557163 CN102014584B (en) | 2010-11-24 | 2010-11-24 | Process for manufacturing whole gold-plated board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010557163 CN102014584B (en) | 2010-11-24 | 2010-11-24 | Process for manufacturing whole gold-plated board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102014584A true CN102014584A (en) | 2011-04-13 |
| CN102014584B CN102014584B (en) | 2012-12-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010557163 Expired - Fee Related CN102014584B (en) | 2010-11-24 | 2010-11-24 | Process for manufacturing whole gold-plated board |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023178851A1 (en) * | 2022-03-25 | 2023-09-28 | 生益电子股份有限公司 | Preparation method for pcb, and pcb |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10256702A (en) * | 1997-03-11 | 1998-09-25 | Sumitomo Kinzoku Electro Device:Kk | Manufacture of ceramic board |
| JP2000012992A (en) * | 1998-06-25 | 2000-01-14 | Mitsumi Electric Co Ltd | Circuit board |
| CN101351085A (en) * | 2007-07-16 | 2009-01-21 | 南亚科技股份有限公司 | Gold finger for circuit board and preparation method thereof |
| CN101521997A (en) * | 2008-02-29 | 2009-09-02 | 中兴通讯股份有限公司 | Method for processing grading connecting finger |
-
2010
- 2010-11-24 CN CN 201010557163 patent/CN102014584B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10256702A (en) * | 1997-03-11 | 1998-09-25 | Sumitomo Kinzoku Electro Device:Kk | Manufacture of ceramic board |
| JP2000012992A (en) * | 1998-06-25 | 2000-01-14 | Mitsumi Electric Co Ltd | Circuit board |
| CN101351085A (en) * | 2007-07-16 | 2009-01-21 | 南亚科技股份有限公司 | Gold finger for circuit board and preparation method thereof |
| CN101521997A (en) * | 2008-02-29 | 2009-09-02 | 中兴通讯股份有限公司 | Method for processing grading connecting finger |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023178851A1 (en) * | 2022-03-25 | 2023-09-28 | 生益电子股份有限公司 | Preparation method for pcb, and pcb |
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| Publication number | Publication date |
|---|---|
| CN102014584B (en) | 2012-12-26 |
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| C14 | Grant of patent or utility model | ||
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Owner name: SHENNAN CIRCUIT CO., LTD. Free format text: FORMER NAME: SHENZHEN SHENNAN CIRCUITS CO., LTD. |
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Address after: 518053 Nanshan District, Guangdong, overseas Chinese town, No. East Road, No. 99 Patentee after: SHENZHEN SHENNAN CIRCUIT CO., LTD. Address before: 518053 Nanshan District, Guangdong, overseas Chinese town, No. East Road, No. 99 Patentee before: Shenzhen Shennan Circuits Co., Ltd. |
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Granted publication date: 20121226 Termination date: 20151124 |
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