JPH10256333A - Manufacture of evaluating semiconductor wafer - Google Patents

Manufacture of evaluating semiconductor wafer

Info

Publication number
JPH10256333A
JPH10256333A JP6092297A JP6092297A JPH10256333A JP H10256333 A JPH10256333 A JP H10256333A JP 6092297 A JP6092297 A JP 6092297A JP 6092297 A JP6092297 A JP 6092297A JP H10256333 A JPH10256333 A JP H10256333A
Authority
JP
Japan
Prior art keywords
wafer
polishing
ring
polishing tool
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6092297A
Other languages
Japanese (ja)
Inventor
Takafumi Hajime
啓文 一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Super Silicon Crystal Research Institute Corp
Original Assignee
Super Silicon Crystal Research Institute Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Super Silicon Crystal Research Institute Corp filed Critical Super Silicon Crystal Research Institute Corp
Priority to JP6092297A priority Critical patent/JPH10256333A/en
Publication of JPH10256333A publication Critical patent/JPH10256333A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor wafer for evaluation, which can measure cracks, processing strains and the like introduced in slicing highly accurately. SOLUTION: A rotary shaft 15 of a ring-shaped polishing tool 14 having the outer diameter smaller than the outer diameter of a wafer 11 is inclined by an inclination angle θ from a direction V intersecting the surface of the wafer at a right angle. The ring-shaped polishing tool 14 is made to face the surface of the wafer. The ring-shaped polishing tool 14 is pushed to the surface of the wafer 11. A ring-shaped polishing groove, which has the concentric pattern with the profile of the wafer 11 and has a partially cut part, is formed at the surface of the wafer. The wafer surface at both sides of the polishing groove remains as the unpolished initial surface. Since the long polishing groove is formed in this way, the distribution of the defect such as the cracks and the processing strains can be measured highly accurately. The depth of the defective part is also measured directly by the comparison with the initial surface on both sides of the polishing groove.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、インゴットから切り出
されたウェーハやラッピングされたウェーハの表面に導
入されているクラック,加工歪み等の欠陥部を検出する
ために使用される評価用半導体ウェーハを作成する方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an evaluation semiconductor wafer used for detecting defects such as cracks and processing distortion introduced into the surface of a wafer cut from an ingot or a wrapped wafer. How to create.

【0002】[0002]

【従来の技術】半導体ウェーハは、内歯リング,ワイヤ
ソー等でインゴットをスライスすることにより得られ
る。インゴットから切り出された半導体ウェーハには、
加工に起因するクラックや歪みが導入されている。たと
えば、図1に示すように、完全結晶シリコン1の上に弾
性変形層2を介してクラック層3,塑性流動層4等から
なる表面層が形成されている。クラック層3は、加工に
より発生した微小なクラックが分布しており、ウェーハ
表面から10μm程度の深さに達する。クラック層3の
深さに応じて後続するラッピング工程での加工条件を設
定するため、予めクラック層3の深さを測定することが
必要である。クラック層の深さ測定に使用されるサンプ
ルは、通常、角度研磨法で作成されている。角度研磨法
では、図2に示すように貼付けブロック5の傾斜面に試
験片6を貼り付け、ガイドリング7に装着し、傾斜状態
に保持された試験片6を研磨盤8で研磨している。
2. Description of the Related Art A semiconductor wafer is obtained by slicing an ingot with an internal ring, a wire saw or the like. For semiconductor wafers cut from ingots,
Cracks and distortions due to processing are introduced. For example, as shown in FIG. 1, a surface layer including a crack layer 3, a plastic flow layer 4, and the like is formed on a perfect crystal silicon 1 via an elastic deformation layer 2. In the crack layer 3, minute cracks generated by the processing are distributed and reach a depth of about 10 μm from the wafer surface. In order to set processing conditions in the subsequent lapping step according to the depth of the crack layer 3, it is necessary to measure the depth of the crack layer 3 in advance. A sample used for measuring the depth of the crack layer is usually prepared by an angle polishing method. In the angle polishing method, as shown in FIG. 2, a test piece 6 is attached to an inclined surface of an attaching block 5, attached to a guide ring 7, and the test piece 6 held in an inclined state is polished by a polishing plate 8. .

【0003】試験片6は、図3に示すように貼付けブロ
ック5の傾斜面に対応する傾斜角θをつけて表面が斜め
に研磨される。試験片6の表面にあるクラック層3は、
角度研磨によって厚み方向に広がった傾斜表面としてク
ラック層断面9が露呈する。クラック層3の厚みをDと
すると、角度研磨によって現れたクラック層断面の長さ
をLは、L=D/ sinθで表される。通常、傾斜角θを
5.7度に設定して角度研磨することから、L=D/ s
in5.7度=D×10となる。すなわち、厚みDのクラ
ック層3は、10倍に拡大された幅Lのクラック層断面
9として観察される。
As shown in FIG. 3, the surface of the test piece 6 is polished obliquely at an inclination angle θ corresponding to the inclined surface of the sticking block 5. The crack layer 3 on the surface of the test piece 6
The crack layer cross section 9 is exposed as an inclined surface spread in the thickness direction by the angle polishing. Assuming that the thickness of the crack layer 3 is D, the length of the cross section of the crack layer generated by the angle polishing is represented by L = L / Sinθ. Usually, since the angle polishing is performed by setting the inclination angle θ to 5.7 degrees, L = D / s
in 5.7 degrees = D × 10. That is, the crack layer 3 having a thickness D is observed as a crack layer cross section 9 having a width L that is magnified ten times.

【0004】[0004]

【発明が解決しようとする課題】従来の角度研磨法で
は、クラック層断面9の顕微鏡観察によりクラックを検
出する。クラックが検出された位置のウェーハ表面から
の深さは、試験片6の縁部全域が図3に示すように傾斜
したクラック層断面9となるため、試験片表面10との
比較で測定できず、角度成分に基づいて算出されてい
る。しかし、正確に設定通りの角度で試験片6が加工さ
れているか否かを知ることができず、測定された深さの
精度や信頼性が欠ける。また、貼付けブロック5に固定
した試験片6を研磨する方式であるため、クラック断面
層9の長さLが大きくなるように角度を小さくすると、
加工初期から試験片6にかかる圧力分布が場所によって
変動し易く、深さ方向への信頼性が乏しくなる。その結
果、形成可能なクラック断面層9の長さLに制約が加わ
り、クラック層3を詳細に観察できる断面層が得られな
い。本発明は、このような問題を解消すべく案出された
ものであり、深さが連続的に変化する長いリング状の研
磨溝を形成することにより、クラック層に導入される加
工歪み,クラック等の欠陥を容易に且つ高精度に検出で
きる評価用半導体ウェーハを得ることを目的とする。
In the conventional angle polishing method, cracks are detected by microscopic observation of the cross section 9 of the crack layer. The depth from the wafer surface at the position where the crack was detected cannot be measured by comparison with the test piece surface 10 because the entire edge portion of the test piece 6 becomes a crack layer cross section 9 inclined as shown in FIG. , Based on the angle component. However, it is not possible to know whether or not the test piece 6 is processed at the exactly set angle, and the accuracy and reliability of the measured depth are lacking. In addition, since the test piece 6 fixed to the attachment block 5 is polished, if the angle is reduced so that the length L of the crack section layer 9 increases,
The pressure distribution applied to the test piece 6 from the initial stage of processing tends to fluctuate from place to place, and the reliability in the depth direction becomes poor. As a result, the length L of the crack section layer 9 that can be formed is restricted, and a section layer in which the crack layer 3 can be observed in detail cannot be obtained. The present invention has been devised in order to solve such a problem. By forming a long ring-shaped polishing groove having a continuously changing depth, the processing strain introduced into the crack layer and the cracks are reduced. It is an object of the present invention to obtain an evaluation semiconductor wafer capable of easily and accurately detecting defects such as defects.

【0005】[0005]

【課題を解決するための手段】本発明の評価用半導体ウ
ェーハ作成方法は、その目的を達成するため、ウェーハ
の外径よりも小さい外径をもつリング状研磨工具の回転
軸をウェーハ表面に直交する方向から若干傾けてリング
状研磨工具をウェーハの表面に対向させ、リング状研磨
工具をウェーハの表面に押し付け、ウェーハの輪郭と同
心円状で一部途切れたリング状の研磨溝をウェーハの表
面に形成することを特徴とする。
In order to achieve the object, a method for preparing a semiconductor wafer for evaluation according to the present invention is arranged so that a rotation axis of a ring-shaped polishing tool having an outer diameter smaller than an outer diameter of a wafer is perpendicular to a wafer surface. The ring-shaped polishing tool is slightly inclined from the direction to be opposed to the wafer surface, the ring-shaped polishing tool is pressed against the wafer surface, and the ring-shaped polishing groove concentric with the wafer contour and partially cut off is formed on the wafer surface. It is characterized by forming.

【0006】[0006]

【実施の形態】本発明では、評価用半導体ウェーハを次
のように作成する。インゴットのスライスにより得られ
たウェーハ11をサンプリングし、図4に示すように研
磨ベース12の上に固定配置する。ウェーハ11の表面
に直交する方向Vと回転中心Cとの間に所定の傾斜角θ
を付けて、下面に研磨パッド13を取り付けている研磨
工具14をウェーハ11の表面に対向させる。傾斜角θ
は、研磨工具14のサイズ及び形成される研磨溝の最大
深さに応じて0.04〜0.1度の範囲に設定すること
が好ましい。この状態で研磨工具ウェーハ11を回転軸
15の軸方向に沿ってウェーハ11の表面に押し付けな
がら研磨すると、図5に示すようにウェーハ11の輪郭
と同心円状になった研磨溝15が形成される。研磨溝1
5は、ウェーハ11と研磨工具14との距離を適切に調
整することにより、一部が初期表面のままの未研磨領域
17を除いてリング状になる。未研磨領域17の反対側
は、最も深く研磨加工が施された最深部18になる。研
磨溝16は、図6に示すように未研磨領域17から最深
部18に向けて一定した勾配で徐々に深くなっている。
また、研磨溝16の両側には、研磨工具14による加工
を受けていない初期表面19が残っている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a semiconductor wafer for evaluation is prepared as follows. The wafer 11 obtained by slicing the ingot is sampled and fixedly arranged on the polishing base 12 as shown in FIG. A predetermined tilt angle θ between a direction V perpendicular to the surface of the wafer 11 and the center of rotation C
Then, the polishing tool 14 having the polishing pad 13 attached to the lower surface is opposed to the surface of the wafer 11. Tilt angle θ
Is preferably set in the range of 0.04 to 0.1 degrees depending on the size of the polishing tool 14 and the maximum depth of the polishing groove to be formed. In this state, when the polishing tool wafer 11 is polished while being pressed against the surface of the wafer 11 along the axial direction of the rotating shaft 15, a polishing groove 15 concentric with the contour of the wafer 11 is formed as shown in FIG. . Polishing groove 1
By appropriately adjusting the distance between the wafer 11 and the polishing tool 14, a portion 5 is formed in a ring shape except for an unpolished region 17 in which a part remains the initial surface. The opposite side of the unpolished region 17 is the deepest portion 18 that has been polished deepest. As shown in FIG. 6, the polishing groove 16 is gradually deepened with a constant gradient from the unpolished region 17 to the deepest portion 18.
In addition, on both sides of the polishing groove 16, initial surfaces 19 that have not been processed by the polishing tool 14 remain.

【0007】このようにして形成された研磨溝17で
は、従来の角度研磨による場合と比較して、露出したク
ラック断面層9を十分に長くできる。その結果、図6に
示すようにクラック層3と健全な結晶層1との境界が大
きな幅でクラック断面層9に露呈し、クラック,加工歪
み等の欠陥の分布及び量を正確に検出できる。しかも、
クラック断面層9の側部に初期表面19が存在するの
で、欠陥部が検出された箇所の深さを直接的に測定する
ことが可能となる。得られた測定結果は、スライシング
工程にフィードバックされ、加工条件の調整に使用され
る。また、後続するラッピング工程の条件設定にも利用
される。同様にラッピング,研削等の加工が施されたウ
ェーハについても、クラック,加工歪み等の欠陥部測定
用のサンプルが作成される。
In the polishing groove 17 thus formed, the exposed crack section layer 9 can be made sufficiently longer than in the case of the conventional angle polishing. As a result, as shown in FIG. 6, the boundary between the crack layer 3 and the healthy crystal layer 1 is exposed with a large width to the crack section layer 9, and the distribution and amount of defects such as cracks and processing strain can be accurately detected. Moreover,
Since the initial surface 19 exists on the side of the crack cross section layer 9, it is possible to directly measure the depth of the portion where the defect is detected. The obtained measurement result is fed back to the slicing step and used for adjusting the processing conditions. It is also used for setting conditions for the subsequent lapping process. Similarly, a sample for measuring a defective portion such as a crack or a processing distortion is created for a wafer subjected to processing such as lapping and grinding.

【0008】[0008]

【実施例】インゴットからスライスされた直径200m
m,平均厚み1mmのウェーハを試験片6に使用した。
研磨工具14には、不織布製の研磨パッド13を装着し
た外径150mm,内径130mmの研磨工具を使用し
た。研磨ベース12に固定配置したウェーハ11の表面
と直交する方向Vに対する回転軸15の傾斜角度を0.
04度に設定し、研磨工具14を500rpmで回転さ
せ、ウェーハ11に300N/mm2 の押圧力で押し付
けた。研磨を30分間継続した後、ウェーハ11の表面
から研磨工具14を後退させた。研磨されたウェーハ1
1の表面を観察したところ、リング状の研磨工具14が
当った箇所に、円周方向の長さが380mmで外径15
0mm,内径130mmのリング状研磨溝16が形成さ
れていた。研磨溝17の最深部18は、深さが100μ
mであった。未研磨領域17は、円周方向の長さが95
mmであった。また、研磨溝16の両側は、未研磨の初
期表面19であった。
[Example] 200m in diameter sliced from an ingot
m, a wafer having an average thickness of 1 mm was used for the test piece 6.
As the polishing tool 14, a polishing tool having an outer diameter of 150 mm and an inner diameter of 130 mm equipped with a polishing pad 13 made of nonwoven fabric was used. The inclination angle of the rotating shaft 15 with respect to a direction V orthogonal to the surface of the wafer 11 fixedly arranged on the polishing base 12 is set to 0.
The polishing tool 14 was rotated at 500 rpm, and was pressed against the wafer 11 with a pressing force of 300 N / mm 2 . After polishing was continued for 30 minutes, the polishing tool 14 was retracted from the surface of the wafer 11. Polished wafer 1
Observation of the surface of No. 1 showed that a portion having a circumferential length of 380 mm and an outer diameter of 15
A ring-shaped polishing groove 16 having a diameter of 0 mm and an inner diameter of 130 mm was formed. The deepest portion 18 of the polishing groove 17 has a depth of 100 μm.
m. The unpolished area 17 has a circumferential length of 95
mm. Both sides of the polishing groove 16 were unpolished initial surfaces 19.

【0009】研磨溝16に露呈したクラック層断面9を
観察したところ、未研磨領域17から30mmの位置ま
では多量のクラックが検出され、徐々にクラックが少な
くなり、未研磨領域17から45mm離れるとクラック
が検出されなくなった。未研磨領域17から30mm及
び45mmの位置は、両側の初期表面18と比較するこ
とにより、それぞれ20μm及び30μmの深さに相当
することが判った。このようにクラック発生量や欠陥部
の深さを精度良く測定できるため、スライシングやポリ
ッシングの条件調整に必要な高精度の情報が得られる。
Observation of the cross section 9 of the crack layer exposed to the polishing groove 16 reveals that a large number of cracks are detected up to a position 30 mm from the unpolished region 17, the number of cracks gradually decreases, and that 45 mm away from the unpolished region 17. Cracks are no longer detected. The positions 30 mm and 45 mm from the unpolished area 17 were found to correspond to a depth of 20 μm and 30 μm, respectively, by comparison with the initial surfaces 18 on both sides. As described above, since the amount of crack generation and the depth of the defective portion can be measured with high accuracy, highly accurate information necessary for adjusting the slicing and polishing conditions can be obtained.

【0010】[0010]

【発明の効果】以上に説明したように、本発明に従って
作成した評化用半導体ウェーハは、欠陥部検出用に形成
した研磨溝が連続して深くなる傾斜面になっている。そ
のため、角度研磨で作成した従来の評化用半導体ウェー
ハに比較して、欠陥部が格段に精度良く検出され、初期
表面と比較することにより欠陥部の深さも容易に且つ正
確に測定できる。
As described above, the evaluation semiconductor wafer prepared according to the present invention has an inclined surface in which the polishing grooves formed for detecting a defective portion are continuously deepened. For this reason, a defective portion is detected with much higher accuracy than a conventional evaluation semiconductor wafer prepared by angle polishing, and the depth of the defective portion can be easily and accurately measured by comparing with the initial surface.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 スライシングでクラックが導入された表面層
をもつウェーハの断面
FIG. 1 is a cross section of a wafer having a surface layer in which cracks have been introduced by slicing.

【図2】 従来の角度研磨による評価用半導体ウェーハ
の作成
FIG. 2 Preparation of a semiconductor wafer for evaluation by conventional angle polishing

【図3】 角度研磨により形成された傾斜のあるクラッ
ク層断面
FIG. 3 is a sectional view of a crack layer having an inclination formed by angle polishing.

【図4】 本発明に従った評価用半導体ウェーハの作成FIG. 4 is a view showing the preparation of a semiconductor wafer for evaluation according to the present invention.

【図5】 円周方向に延びる研磨溝が形成された評価用
半導体ウェーハ
FIG. 5 is a semiconductor wafer for evaluation in which circumferentially extending polishing grooves are formed.

【図6】 研磨溝が形成された評価用半導体ウェーハの
断面
FIG. 6 is a cross section of a semiconductor wafer for evaluation in which a polishing groove is formed.

【符号の説明】[Explanation of symbols]

1:完全結晶シリコン 2:弾性変形層 3:クラ
ック層 4:塑性流動層 5:貼付けブロック
6:試験片(ウェーハ) 7:ガイドリング 8:研磨盤 9:露呈したクラック層断面 10:
試験片表面 11:ウェーハ 12:研磨ベース
13:研磨パッド 14:研磨工具 15:回転
軸 16:研磨溝 17:未研磨領域 18:最
深部 19:初期表面 V:ウェーハの表面に直交する方向 C:研磨工具の回転中心 θ:回転軸の傾斜角
1: perfect crystalline silicon 2: elastic deformation layer 3: crack layer 4: plastic fluidized bed 5: sticking block
6: Test piece (wafer) 7: Guide ring 8: Polishing board 9: Cross section of exposed crack layer 10:
Specimen surface 11: Wafer 12: Polishing base
13: Polishing pad 14: Polishing tool 15: Rotating axis 16: Polishing groove 17: Unpolished area 18: Deepest part 19: Initial surface V: Direction perpendicular to wafer surface C: Rotation center of polishing tool θ: Rotation axis Tilt angle

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 ウェーハの外径よりも小さい外径をもつ
リング状研磨工具の回転軸をウェーハ表面に直交する方
向から若干傾けてリング状研磨工具をウェーハの表面に
対向させ、リング状研磨工具をウェーハの表面に押し付
け、ウェーハの輪郭と同心円状で一部途切れたリング状
の研磨溝をウェーハの表面に形成することを特徴とする
評価用半導体ウェーハの作成方法。
1. A ring-shaped polishing tool having a ring-shaped polishing tool having an outer diameter smaller than the outer diameter of a wafer is slightly inclined from a direction perpendicular to the wafer surface so that the ring-shaped polishing tool faces the wafer surface. And forming a ring-shaped polishing groove, which is concentric with the contour of the wafer and partially cut off, on the surface of the wafer.
JP6092297A 1997-03-14 1997-03-14 Manufacture of evaluating semiconductor wafer Pending JPH10256333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6092297A JPH10256333A (en) 1997-03-14 1997-03-14 Manufacture of evaluating semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6092297A JPH10256333A (en) 1997-03-14 1997-03-14 Manufacture of evaluating semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH10256333A true JPH10256333A (en) 1998-09-25

Family

ID=13156373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6092297A Pending JPH10256333A (en) 1997-03-14 1997-03-14 Manufacture of evaluating semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH10256333A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017034025A (en) * 2015-07-30 2017-02-09 濱田重工株式会社 Processing damage evaluation method of semiconductor wafer
CN109556938A (en) * 2018-10-22 2019-04-02 大冶特殊钢股份有限公司 A kind of cambered surface defect inspection method of workpiece

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017034025A (en) * 2015-07-30 2017-02-09 濱田重工株式会社 Processing damage evaluation method of semiconductor wafer
CN109556938A (en) * 2018-10-22 2019-04-02 大冶特殊钢股份有限公司 A kind of cambered surface defect inspection method of workpiece
CN109556938B (en) * 2018-10-22 2021-07-02 大冶特殊钢有限公司 Cambered surface defect detection method for workpiece

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