JPH08115893A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH08115893A
JPH08115893A JP25176994A JP25176994A JPH08115893A JP H08115893 A JPH08115893 A JP H08115893A JP 25176994 A JP25176994 A JP 25176994A JP 25176994 A JP25176994 A JP 25176994A JP H08115893 A JPH08115893 A JP H08115893A
Authority
JP
Japan
Prior art keywords
grinding
semiconductor
semiconductor substrate
grindstone
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25176994A
Other languages
Japanese (ja)
Inventor
Shigeo Sasaki
栄夫 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP25176994A priority Critical patent/JPH08115893A/en
Publication of JPH08115893A publication Critical patent/JPH08115893A/en
Pending legal-status Critical Current

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  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE: To provide a method for processing semiconductor devices, wherein variations in traverse rupture strength are reduced, wherein a time required for grinding is shortened, and wherein manufacturing cost is reduced. CONSTITUTION: A semiconductor substrate 28 is ground in such a way that linear streaks 30 parallel with the orientation flat 29 are formed on the underside of the substrate. Semiconductor devices 31 are so positioned that the long side x of each of them will be parallel with the streaks 30 in the semiconductor device 31. This reduces variations in traverse rupture strength from one semiconductor device 31 to another cut from the semiconductor substrate 28. In addition it is possible to obtain a required traverse rupture strength or higher even by grinding with a wheel of lover number. Grinding speed is increased, and a time required for grinding is reduced. One wheel is applicable to a larger number of workpieces, and thus the frequency of wheel change is reduced. This saves labor for grinding, and leads to the reduction of manufacturing cost.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体基板を切断分離
して複数の半導体素子を形成する半導体素子の製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor substrate is cut and separated to form a plurality of semiconductor devices.

【0002】[0002]

【従来の技術】周知の通り、半導体基板に形成された半
導体素子を個々の半導体素子に切断分離する前に、個々
の半導体素子を封入する外囲器の大きさや厚さに合わせ
て半導体基板を所定の厚さにするため、基板裏面を研削
する必要がある。このような基板裏面の研削には、イン
フィード研削及びクリープフィード研削と呼ばれる2つ
の研削方法が用いられたいた。
2. Description of the Related Art As is well known, before cutting a semiconductor element formed on a semiconductor substrate into individual semiconductor elements, the semiconductor substrate is adjusted in accordance with the size and thickness of an envelope for enclosing the individual semiconductor elements. It is necessary to grind the back surface of the substrate to obtain a predetermined thickness. Two grinding methods called in-feed grinding and creep-feed grinding have been used for grinding the back surface of the substrate.

【0003】以下、従来技術について図7乃至図10を
参照して説明する。図7は第1の従来技術であるインフ
ィード研削を示す要部の側面図であり、図8は第1の従
来技術によって研削された半導体基板の裏面図であり、
図9は第2の従来技術であるクリープフィード研削を示
す要部の側面図であり、図10は第2の従来技術によっ
て研削された半導体基板の裏面図である。
The prior art will be described below with reference to FIGS. 7 to 10. FIG. 7 is a side view of a main part showing infeed grinding which is a first conventional technique, and FIG. 8 is a back view of a semiconductor substrate ground by the first conventional technique,
FIG. 9 is a side view of an essential part showing creep feed grinding which is a second conventional technique, and FIG. 10 is a back view of a semiconductor substrate ground by the second conventional technique.

【0004】図7及び図8に示した第1の従来技術のイ
ンフィード研削において、1は研削装置の回転支持台
で、この回転支持台1はその下面側に設けられた回転軸
2によって支持面3が垂直な軸回りに回転する。4は円
板状の砥石で、この砥石4は研削面5が回転支持台1の
支持面3に対向すると共に、支持面3に平行な面内で回
転するように設けてある。
In the first conventional in-feed grinding shown in FIGS. 7 and 8, 1 is a rotary support of a grinding machine, and the rotary support 1 is supported by a rotary shaft 2 provided on the lower surface side thereof. Face 3 rotates about a vertical axis. Reference numeral 4 is a disc-shaped grindstone, and the grindstone 4 is provided so that the grinding surface 5 faces the support surface 3 of the rotary support 1 and rotates in a plane parallel to the support surface 3.

【0005】そして砥石4の回転は、回転支持台1の支
持面3の回転中心に対し偏心した回転中心を有するよう
砥石4の上面側に設けた回転軸6によって行う。また砥
石4は、研削時に図7中に白抜き矢印7で示すように研
削面5に垂直な方向に送られ、研削量を調節するように
なっている。
The grindstone 4 is rotated by a rotary shaft 6 provided on the upper surface side of the grindstone 4 so as to have a center of rotation that is eccentric to the center of rotation of the support surface 3 of the rotary support 1. Further, the grindstone 4 is fed in a direction perpendicular to the grinding surface 5 as shown by an outline arrow 7 in FIG. 7 during grinding, and the grinding amount is adjusted.

【0006】このため、半導体基板8の裏面を研削する
際には、回転支持台1の支持面3上に半導体基板8をそ
の裏面が上側となるように固定し、回転支持台1を回転
させると同時に砥石4を回転させる。この後、砥石4を
回転させた状態で白抜き矢印7の方向に送り半導体基板
8の研削を上方から実行し、半導体基板8の厚さが所定
の厚さとなるまで行う。このような研削を行った後の半
導体基板8の裏面には、図8に示すように回転軸2を中
心として旋回する円弧状の条痕9が刻まれる。
Therefore, when the back surface of the semiconductor substrate 8 is ground, the semiconductor substrate 8 is fixed on the support surface 3 of the rotation support base 1 so that the back surface is the upper side, and the rotation support base 1 is rotated. At the same time, the grindstone 4 is rotated. After that, while the grindstone 4 is rotated, the semiconductor substrate 8 is ground from above by feeding in the direction of the white arrow 7 until the semiconductor substrate 8 reaches a predetermined thickness. On the back surface of the semiconductor substrate 8 after such grinding, as shown in FIG. 8, an arc-shaped striation 9 which turns around the rotation axis 2 is engraved.

【0007】そして、裏面研削が終った半導体基板8を
次の工程に送り、複数の半導体素子10に切断分離す
る。
Then, the semiconductor substrate 8 whose back surface has been ground is sent to the next step to be cut and separated into a plurality of semiconductor elements 10.

【0008】また、図9及び図10に示した第2の従来
技術のクリープフィード研削において、11は研削装置
の支持台で、その上面が支持面12を構成している。ま
た13は円板状の砥石で、この砥石13はその下面14
が支持台11の支持面12に対向すると共に、上面側に
設けた回転軸15によって支持面12に平行な面内で回
転するように設けてある。
In the second prior art creep feed grinding shown in FIGS. 9 and 10, 11 is a support stand of the grinding machine, the upper surface of which constitutes a support surface 12. Further, 13 is a disk-shaped grindstone, and this grindstone 13 has its lower surface 14
Is provided so as to face the support surface 12 of the support base 11 and to rotate in a plane parallel to the support surface 12 by the rotating shaft 15 provided on the upper surface side.

【0009】さらに砥石13は、研削時に図9中に白抜
き矢印16で示すように、支持台11の支持面12に平
行な方向に直線的に送られるようになっている。このた
め砥石13は周縁角部17と下面14とが研削部分とな
っている。なお、1回の研削量は回転軸15の軸方向へ
の砥石13の送り出し量によって決定される。
Further, the grindstone 13 is linearly fed in a direction parallel to the support surface 12 of the support base 11 as shown by an outline arrow 16 in FIG. 9 during grinding. Therefore, the grindstone 13 has the peripheral edge portion 17 and the lower surface 14 as the grinding portion. The amount of grinding performed once is determined by the amount of feed of the grindstone 13 in the axial direction of the rotary shaft 15.

【0010】このため、半導体基板18の裏面を研削す
る際には、支持台11の支持面12上に半導体基板18
をその裏面が上側となるように固定し、砥石13を回転
させる。続いて、砥石13を回転させた状態で白抜き矢
印16の方向に送り半導体基板18の研削を側方から実
行し、半導体基板18の全体の厚さが所定の厚さとなる
まで砥石13の送り出し量を調節して行う。このような
研削を行った後の半導体基板18の裏面には、図10に
示すように一方向に並ぶ円弧状の条痕19が刻まれる。
Therefore, when the back surface of the semiconductor substrate 18 is ground, the semiconductor substrate 18 is placed on the support surface 12 of the support base 11.
Is fixed so that its back surface faces upward, and the grindstone 13 is rotated. Subsequently, while the grindstone 13 is rotated, the semiconductor substrate 18 is ground from the side by feeding in the direction of the white arrow 16, and the grindstone 13 is fed out until the entire thickness of the semiconductor substrate 18 reaches a predetermined thickness. Adjust the amount. On the back surface of the semiconductor substrate 18 after such grinding, as shown in FIG. 10, arcuate scratches 19 arranged in one direction are engraved.

【0011】そして、裏面研削が終った半導体基板18
を次の工程に送り、複数の半導体素子20に切断分離す
る。
Then, the semiconductor substrate 18 whose back surface has been ground
Is sent to the next step and is cut and separated into a plurality of semiconductor elements 20.

【0012】こうして形成された個々の半導体素子1
0,20の裏面には、上述の第1及び第2の従来技術に
よって半導体基板8,18の裏面に刻まれた円弧状の条
痕9,19が分割して刻まれており、各半導体素子1
0,20毎に条痕9,19の模様が異なることになる。
The individual semiconductor elements 1 thus formed
On the back surfaces of the semiconductor devices 0 and 20, arcuate scratches 9 and 19 formed on the back surfaces of the semiconductor substrates 8 and 18 by the above-described first and second conventional techniques are divided and carved. 1
The pattern of the scratches 9 and 19 is different for each 0 and 20.

【0013】そして、切断分離された各半導体素子1
0,20は、マウンティング(ダイ・ボンディング)工
程やボンディング工程、モールディング工程等を経て合
成樹脂やセラミックの外囲器に封入された半導体装置と
なる。
Then, each semiconductor element 1 cut and separated
The semiconductor devices 0 and 20 are encapsulated in a synthetic resin or ceramic envelope through a mounting (die bonding) process, a bonding process, a molding process, and the like.

【0014】しかし、モールディング工程等を経て外囲
器内に封入された半導体素子10,20には外囲器から
の圧縮及び引張応力が加わり、この応力によって半導体
素子10,20の内の一部が破壊してしまう虞があっ
た。これは研削によって半導体基板8,18の裏面に形
成された破砕層が原因で、この破砕層が深い場合に半導
体素子10,20の抗折応力が小さくなって発生する。
そして半導体素子10,20の抗折応力は、同一の半導
体基板8,18から切断分離したものの中でも大きくば
らつくものとなっていた。
However, compressive and tensile stresses from the envelope are applied to the semiconductor elements 10 and 20 enclosed in the envelope through the molding process and the like, and this stress causes a part of the semiconductor elements 10 and 20 to be enclosed. Could be destroyed. This is caused by the crushed layer formed on the back surfaces of the semiconductor substrates 8 and 18 by grinding, and when the crushed layer is deep, the bending stress of the semiconductor elements 10 and 20 becomes small and occurs.
The bending stress of the semiconductor elements 10 and 20 varies greatly among the semiconductor chips 10 and 18 cut and separated.

【0015】このようなことから半導体基板8,18の
裏面研削は高番手の砥石4,13によって行い、形成さ
れる破砕層が浅くなるように加工し、半導体素子10,
20の抗折応力が外囲器からの応力よりも大きくなるよ
うにしていた。こうした高番手の砥石4,13での研削
では時間を要し、また砥石の磨耗が激しくて1つの砥石
で加工できる枚数が少なく、砥石の取り換え頻度が高く
手間の掛かるものであった。また砥石のコストは高番手
のものほど高価であり、取り換え頻度が高いこと等と合
わせ製造コストを高いものにしていた。
From the above facts, the backside grinding of the semiconductor substrates 8 and 18 is carried out by the grindstones 4 and 13 of high count, and the crushed layer formed is processed to be shallow, and the semiconductor element 10 and
The bending stress of 20 was set to be larger than the stress from the envelope. Grinding with such high-count grindstones 4 and 13 takes time, and the number of pieces that can be processed by one grindstone is small because the grindstone is worn out so frequently that the grindstone has to be replaced frequently and is troublesome. Further, the cost of the grindstone is higher as the number is higher, and the manufacturing cost is high due to the high frequency of replacement.

【0016】[0016]

【発明が解決しようとする課題】上記のように従来は半
導体基板の裏面研削を行った後に切断分離して得た半導
体素子が、合成樹脂等の外囲器に封入した時に破壊しな
いよう高番手で粒子が細かい砥石によって裏面研削を行
っていた。このため研削に時間を要すると共に加工に手
間が掛かり、製造コストが高いものとなっていた。この
ような状況に鑑みて本発明はなされたもので、その目的
とするところは抗折応力のばらつきが少なくしながらも
研削時間が短縮できると共に加工に手間が掛からず、製
造コストを低減することができる半導体素子の製造方法
を提供することにある。
As described above, in the prior art, a semiconductor device obtained by cutting and separating the back surface of a semiconductor substrate and then cutting and separating it does not break when it is enclosed in an envelope made of synthetic resin or the like. Back grinding was performed with a grindstone with fine particles. For this reason, it takes time to grind, labor is required for processing, and the manufacturing cost is high. The present invention has been made in view of such a situation, and an object of the present invention is to reduce the grinding time and the processing time without reducing the variation of the transverse stress, and to reduce the manufacturing cost. It is an object of the present invention to provide a method of manufacturing a semiconductor device.

【0017】[0017]

【課題を解決するための手段】本発明の半導体素子の製
造方法は、半導体基板の裏面を所定の厚さとなるように
研削した後、該半導体基板を切断分離して複数の半導体
素子を形成するようにした半導体素子の製造方法におい
て、半導体基板の裏面に略直線状の条痕が形成されるよ
う研削することを特徴とするものであり、また、半導体
基板の裏面を所定の厚さとなるように研削した後、該半
導体基板を切断分離して複数の方形状の半導体素子を形
成するようにした半導体素子の製造方法において、半導
体基板の裏面に略直線状の条痕が形成されるよう研削す
ると共に、半導体素子の長辺と該半導体素子の条痕との
なす角度が±20度以下であることを特徴とするもので
あり、さらに、条痕とオリエンテーションフラットとの
なす角度が±20度以下であることを特徴とするもので
ある。
According to a method of manufacturing a semiconductor element of the present invention, a plurality of semiconductor elements are formed by grinding the back surface of a semiconductor substrate to a predetermined thickness and then cutting and separating the semiconductor substrate. In the method of manufacturing a semiconductor element as described above, the back surface of the semiconductor substrate is ground so that substantially linear scratches are formed, and the back surface of the semiconductor substrate has a predetermined thickness. In the method of manufacturing a semiconductor element, which is formed by cutting and separating the semiconductor substrate to form a plurality of rectangular semiconductor elements after grinding, the grinding is performed so that a substantially linear scratch is formed on the back surface of the semiconductor substrate. In addition, the angle between the long side of the semiconductor element and the striation of the semiconductor element is ± 20 degrees or less, and the angle between the striation and the orientation flat is ± 20 degrees. It is characterized by the following.

【0018】[0018]

【作用】上記のように構成された半導体素子の製造方法
は、半導体基板の裏面に略直線状の条痕が形成されるよ
う研削したり、あるいはまた半導体基板の裏面に略直線
状の条痕が形成されるよう研削すると共に、半導体素子
の長辺と該半導体素子の条痕とのなす角度が±20度以
下になるようにしているので、半導体基板を切断分離し
て得た半導体素子の抗折応力のばらつきを少なくし、ま
たその抗折応力を所定の大きさ以上のものに低番手の砥
石の研削によっても加工することができ、研削速度が増
して研削時間が短縮され、さらに1つの砥石での研削数
量が増し砥石交換の頻度が少なくなって加工に手間が掛
からず製造コストが低減できる。
According to the method of manufacturing a semiconductor device having the above-described structure, grinding is performed so that a substantially linear scratch is formed on the back surface of the semiconductor substrate, or a substantially linear scratch is formed on the back surface of the semiconductor substrate. Since the angle formed between the long side of the semiconductor element and the striation of the semiconductor element is set to ± 20 degrees or less while grinding is performed so that the semiconductor element is obtained by cutting and separating the semiconductor substrate. The variation in bending stress can be reduced, and the bending stress can be processed to a predetermined value or more by grinding a low count grindstone. The grinding speed is increased and the grinding time is shortened. The number of grinding with one grindstone increases and the frequency of grindstone replacement is reduced, so that it does not take time and labor and the manufacturing cost can be reduced.

【0019】[0019]

【実施例】以下、本発明を図面を参照して説明する。図
1は研削状況を示す要部の側面図であり、図2は研削後
の半導体基板及び半導体素子の裏面図で、図2(a)は
半導体基板の裏面図、図2(b)は半導体素子の裏面図
であり、図3は半導体基板から切断分離した半導体素子
の裏面図であり、図4は半導体素子の抗折応力試験法を
説明するための図であり、図5は抗折応力の特性図であ
り、図6は砥石コスト及び製造コストを示す図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 is a side view of an essential part showing a grinding state, FIG. 2 is a back view of a semiconductor substrate and a semiconductor element after grinding, FIG. 2 (a) is a back view of a semiconductor substrate, and FIG. 2 (b) is a semiconductor. 3 is a back view of the device, FIG. 3 is a back view of the semiconductor device cut and separated from the semiconductor substrate, FIG. 4 is a diagram for explaining a bending stress test method of the semiconductor device, and FIG. 5 is a bending stress. FIG. 6 is a characteristic diagram of FIG. 6, and FIG. 6 is a diagram showing a grindstone cost and a manufacturing cost.

【0020】先ず、実施例の説明に先立って図3乃至図
6により本発明をするに至った知見について説明する。
すなわち、上述した第1及び第2の従来技術によって研
削した半導体基板8,18からは種々の条痕9,19を
裏面に有する半導体素子10,20が切断分離される。
そこでこれらを代表させるようにして方形状の半導体素
子A,B,C,Dを作成し、これらの抗折応力を測定し
た。
First, prior to the description of the embodiments, the knowledge that has led to the present invention will be described with reference to FIGS.
That is, the semiconductor elements 10 and 20 having various scratches 9 and 19 on the back surface are cut and separated from the semiconductor substrates 8 and 18 ground by the above-mentioned first and second conventional techniques.
Then, the semiconductor elements A, B, C, and D having a rectangular shape were prepared by representing them, and the bending stress of these was measured.

【0021】半導体素子A,B,C,Dは図3に示す裏
面図の通り、一辺の長さがそれぞれx及びyの半導体素
子であり、また例えば結晶の(100)面を用いオリエ
ンテーションフラットに平行な長さがxの辺に対し、図
3(a)の半導体素子Aは条痕Pのなす角θが10度で
あり、図3(b)の半導体素子Bは条痕Pのなす角θが
30度であり、図3(c)の半導体素子Cは条痕Pのな
す角θが45度であり、図3(d)の半導体素子Dは条
痕Pのなす角θが90度である。
As shown in the back view of FIG. 3, the semiconductor elements A, B, C, and D are semiconductor elements each having a side length of x and y. For example, a (100) plane of a crystal is used for orientation flatness. The angle θ formed by the striations P in the semiconductor element A in FIG. 3A is 10 degrees and the angle formed by the striations P in the semiconductor element B in FIG. θ is 30 degrees, the semiconductor element C in FIG. 3C has an angle θ formed by the scratches P of 45 degrees, and the semiconductor element D in FIG. 3D has an angle θ formed by the scratches P of 90 degrees. Is.

【0022】そして各半導体素子A,B,C,Dの抗折
応力を図4に示す抗折応力試験法によって測定した。測
定は、外形寸法が長辺の長さx=15mm、短辺の長さ
y=5mm、厚さt=0.45mmの半導体素子A,
B,C,Dを間隔2lが10mmの支点で支え、その中
央に力を作用させて破壊したときの作用力を抗折応力と
して測定している。
The bending stress of each semiconductor element A, B, C, D was measured by the bending stress test method shown in FIG. A semiconductor element A whose outer dimensions are long side length x = 15 mm, short side length y = 5 mm, and thickness t = 0.45 mm is measured.
B, C, and D are supported by a fulcrum with an interval of 2 l of 10 mm, and the acting force when a force is applied to the center of the fulcrum to break is measured as the transverse stress.

【0023】測定結果は図5に示す通りで、長さxの辺
に対し条痕Pのなす角θが小さいほど半導体素子A,
B,C,Dの抗折応力は大きくばらついたものになる。
また研削する砥石の粒子が細かく高番手となるほど半導
体素子A,B,C,Dの抗折応力は大きくなる。そして
砥石の番手による抗折応力の差は、研削加工した時に研
削部分に形成された破砕層が低番手の砥石では深く、こ
の場合には抗折応力が小さくなり、高番手の砥石では浅
く、この場合には抗折応力が大きくなることによる。
The measurement results are as shown in FIG. 5. The smaller the angle θ formed by the striations P with respect to the side of the length x, the semiconductor element A,
The bending stresses of B, C and D are greatly varied.
Further, as the particles of the grindstone to be ground become finer and the count becomes higher, the bending stress of the semiconductor elements A, B, C, D becomes larger. And the difference in bending stress due to the count of the grindstone, the crush layer formed in the grinding portion when grinding is deep in the low count grindstone, in this case the bending stress is small, in the high count grindstone is shallow, In this case, the bending stress increases.

【0024】これに対し、モールディング工程等を経て
外囲器内に封入された半導体素子に加わる圧縮及び引張
応力は約15kg/mm2 程度であり、抗折応力が15
kg/mm2 よりも小さい半導体素子を封入した場合に
は、半導体素子が外囲器から加わる応力によって破壊し
てしまう。そこで抗折応力が約15kg/mm2 以上で
あることが半導体素子に要求される。
On the other hand, the compressive and tensile stress applied to the semiconductor element enclosed in the envelope through the molding process is about 15 kg / mm 2 , and the bending stress is 15 kg / mm 2.
If a semiconductor element smaller than kg / mm 2 is enclosed, the semiconductor element will be destroyed by the stress applied from the envelope. Therefore, the semiconductor element is required to have a bending stress of about 15 kg / mm 2 or more.

【0025】このため図5から抗折応力が約15kg/
mm2 以上である状態を見ると、番手が#600よりも
大きい砥石での裏面研削では、全ての半導体素子におい
て長さxの辺に対し条痕Pのなす角θが20度以下とな
るように研削すればよいことになる。
Therefore, from FIG. 5, the bending stress is about 15 kg /
Looking at the state of mm 2 or more, in the back surface grinding with a grindstone with a count of # 600 or more, the angle θ formed by the striation P with respect to the side of the length x is 20 degrees or less in all semiconductor elements. It should be ground to.

【0026】一方、砥石のコストは、例えば図6に白丸
印で示すように高番手のものほど高価であり、低番手の
砥石で研削を行い取り換え頻度を少なくすることで同図
に黒丸印で示すように製造コストを十分低減することが
できる。
On the other hand, the cost of the grindstone is higher for the higher count ones, as shown by the white circles in FIG. 6, for example. As shown, the manufacturing cost can be reduced sufficiently.

【0027】次に、本発明の一実施例を図1及び図2を
参照して説明する。図1は研削状況を示す要部の側面図
であり、図2は研削後の半導体基板及び半導体素子の裏
面図で、図2(a)は半導体基板の裏面図、図2(b)
は半導体素子の裏面図である。
Next, an embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1 is a side view of an essential part showing a grinding state, FIG. 2 is a back view of a semiconductor substrate and a semiconductor element after grinding, FIG. 2A is a back view of the semiconductor substrate, and FIG.
FIG. 4 is a back view of the semiconductor element.

【0028】図1及び図2において、21は研削装置の
静止状態にある固定された支持台で、その上面が支持面
22を構成している。また23は円柱状の番手が#12
00の砥石で、その研削面である円筒面24が支持台2
1の支持面22に平行であると共に、上面側に同じく支
持面22に平行に設けた回転軸25によって矢印26方
向に回転可能に設けてある。
In FIGS. 1 and 2, reference numeral 21 designates a stationary support stand of the grinding machine in a stationary state, the upper surface of which constitutes a support surface 22. In addition, the cylindrical number 23 is # 12
No. 00 grindstone, the cylindrical surface 24, which is the grinding surface, is used as the support base 2.
The rotary shaft 25 is provided parallel to the first support surface 22 and parallel to the support surface 22 on the upper surface side so as to be rotatable in the arrow 26 direction.

【0029】さらに砥石23は、研削時に図1中に白抜
き矢印27で示すように回転軸25が移動することによ
って、支持台21の支持面22に平行な方向に直線的に
送られるようになっている。
Further, the grindstone 23 is fed linearly in a direction parallel to the support surface 22 of the support base 21 by the movement of the rotary shaft 25 as shown by the white arrow 27 in FIG. 1 during grinding. Has become.

【0030】このため、結晶の(100)面を用いてな
る半導体基板28の裏面を研削する際には、支持台21
の支持面22上に半導体基板28をその裏面が上側とな
るようにし、さらにオリエンテーションフラット29が
砥石の移動方向に平行となるように固定して砥石23を
回転させる。
Therefore, when grinding the back surface of the semiconductor substrate 28 using the (100) plane of the crystal, the support 21
The semiconductor substrate 28 is placed on the supporting surface 22 of the above so that the back surface thereof faces upward, and further, the orientation flat 29 is fixed so as to be parallel to the moving direction of the grindstone, and the grindstone 23 is rotated.

【0031】続いて、砥石23を回転させた状態で白抜
き矢印27の方向に送り半導体基板28の研削を実行
し、半導体基板28の全体の厚さが所定の厚さとなるま
で行う。このような研削を行った後の半導体基板28の
裏面には、図2(a)に示すようにオリエンテーション
フラット29に平行な直線状の条痕30が刻まれる。
Subsequently, while the grindstone 23 is being rotated, the semiconductor substrate 28 is ground in the direction of the arrow 27, and is ground until the entire thickness of the semiconductor substrate 28 reaches a predetermined thickness. As shown in FIG. 2A, a linear scratch 30 parallel to the orientation flat 29 is formed on the back surface of the semiconductor substrate 28 after such grinding.

【0032】そして、裏面研削が終った半導体基板28
を次の工程に送り、オリエンテーションフラット29に
一辺が平行となる長辺がx、短辺がyである方形状の複
数の半導体素子31に切断分離する。
Then, the semiconductor substrate 28 whose back surface has been ground
Is sent to the next step, and is cut and separated into a plurality of rectangular semiconductor elements 31 whose one side is parallel to the orientation flat 29 and whose long side is x and whose short side is y.

【0033】この後、切断分離された各半導体素子31
は、マウンティング(ダイ・ボンディング)工程やボン
ディング工程、モールディング工程等を経て合成樹脂や
セラミックの外囲器に封入された半導体装置となる。
After this, each semiconductor element 31 cut and separated
Is a semiconductor device encapsulated in a synthetic resin or ceramic envelope through a mounting (die bonding) step, a bonding step, a molding step, and the like.

【0034】そして上記の各工程を経て形成された半導
体素子31は、外囲器への封入によって加わってくる約
15kg/mm2 の圧縮及び引張応力の約2倍の抗折応
力を有し、外囲器に封入され半導体装置に加工された状
態でも破壊し難いものとなる。また、本実施例で用いた
#1200の砥石23では、例えば直径が6インチの半
導体基板28の裏面研削が18000〜20000枚行
うことができるようになったのに対し、これより高番手
の#2000の砥石では約9000枚の裏面研削しか実
行できない。さらに#2000の砥石で裏面研削した半
導体基板から得られた半導体素子にはオリエンテーショ
ンフラットに直角方向の条痕を有し抗折応力が外囲器の
圧縮及び引張応力程度しかないものを含むことになって
しまものであった。
The semiconductor element 31 formed through the above steps has a compressive stress of about 15 kg / mm 2 added by the encapsulation in the envelope, and a bending stress about twice the tensile stress. Even if it is enclosed in an envelope and processed into a semiconductor device, it is difficult to destroy. Further, with the grindstone 23 of # 1200 used in this example, it is possible to grind the back surface of the semiconductor substrate 28 having a diameter of 6 inches, for example, from 18,000 to 20000 sheets, while the # With the 2000 grindstone, only about 9000 backside grindings can be performed. Further, semiconductor elements obtained from a semiconductor substrate back-ground with a # 2000 grindstone include those having ridges in a direction perpendicular to the orientation flat and having a bending stress of only the compressive and tensile stresses of the envelope. It was a nuisance.

【0035】以上記載した通り、本実施例によれば、半
導体基板28の裏面研削を直線状の条痕30が形成され
るように行うことで切断分離した複数の半導体素子31
の抗折応力のばらつきが少なくすることができる。そし
て低番手の砥石23を用いて高い抗折応力を有する半導
体素子31を得ることができ、また研削時間が短縮でき
ると共に1つの砥石23での加工数が増して砥石23の
交換の頻度が減少し、手間が掛からなくなる。さらに安
価な砥石23を用いることができるため製造コストを低
減することができる なお、上記の実施例では#1200の砥石23で、オリ
エンテーションフラット29に平行な方向を研削方向と
して半導体基板28を直線状の条痕30が形成されるよ
う研削し、長辺xが研削方向に平行、すなわち条痕30
に平行となるよう半導体素子31を切断分離している
が、略直線状の条痕が形成されるよう研削してもよく、
さらに低番手の#600までの砥石を用い、オリエンテ
ーションフラット29に対し研削方向の角度が±20度
以内となるように半導体基板28を研削したり、半導体
素子31の長辺xと条痕のなす角度が±20度以内とな
るように切断分離しても、半導体基板28の裏面研削に
手間が掛からず、半導体素子31の抗折応力が外囲器の
圧縮及び引張応力よりも大きく、半導体装置に加工され
た状態でも破壊し難いものとなり、実施例と同様の効果
が得られる。
As described above, according to the present embodiment, the back surface of the semiconductor substrate 28 is ground so as to form the linear scratches 30, and the plurality of semiconductor elements 31 are cut and separated.
It is possible to reduce the variation in the bending stress. Then, the semiconductor element 31 having a high bending stress can be obtained by using the low count grindstone 23, and the grinding time can be shortened, and the number of machining with one grindstone 23 is increased to reduce the frequency of exchanging the grindstone 23. However, it does not take time and effort. Further, since it is possible to use a cheaper grindstone 23, it is possible to reduce the manufacturing cost. In the above-described embodiment, with the grindstone 23 of # 1200, the semiconductor substrate 28 is linearly shaped with the direction parallel to the orientation flat 29 as the grinding direction. Grinding is performed so that the long side x is parallel to the grinding direction.
Although the semiconductor element 31 is cut and separated so as to be parallel to, it may be ground so as to form a substantially linear striation,
Further, by using a grindstone up to # 600 of low count, the semiconductor substrate 28 is ground so that the angle in the grinding direction with respect to the orientation flat 29 is within ± 20 degrees, or the long side x of the semiconductor element 31 and the scratches are formed. Even if the semiconductor device is cut and separated so that the angle is within ± 20 degrees, it does not take time to grind the back surface of the semiconductor substrate 28, and the bending stress of the semiconductor element 31 is larger than the compressive and tensile stresses of the envelope. Even in the state of being processed into, it becomes difficult to break, and the same effect as the embodiment can be obtained.

【0036】[0036]

【発明の効果】以上の説明から明らかなように、本発明
は、半導体基板の裏面に略直線状の条痕が形成されるよ
う研削したり、あるいはまた半導体基板の裏面に略直線
状の条痕が形成されるよう研削すると共に、半導体素子
の長辺と該半導体素子の条痕とのなす角度が±20度以
下になるよう構成したことにより、抗折応力のばらつき
が少なく、研削時間が短縮できると共に加工に手間が掛
からず、製造コストを低減することができる等の効果が
得られる。
As is apparent from the above description, according to the present invention, the back surface of the semiconductor substrate is ground so that the substantially linear scratches are formed, or the back surface of the semiconductor substrate is substantially linear. The grinding is performed so that a trace is formed, and the angle formed between the long side of the semiconductor element and the striation of the semiconductor element is ± 20 degrees or less. It is possible to obtain the effects that the manufacturing cost can be shortened, the processing cost can be reduced, and the manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における研削状況を示す要部
の側面図である。
FIG. 1 is a side view of an essential part showing a grinding situation in an embodiment of the present invention.

【図2】本発明の一実施例における研削後の半導体基板
及び半導体素子の裏面図で、図2(a)は半導体基板の
裏面図、図2(b)は半導体素子の裏面図である。
2A and 2B are rear views of a semiconductor substrate and a semiconductor element after grinding in one embodiment of the present invention, FIG. 2A is a rear view of the semiconductor substrate, and FIG. 2B is a rear view of the semiconductor element.

【図3】本発明に係る半導体基板から切断分離した半導
体素子の裏面図である。
FIG. 3 is a back view of a semiconductor element cut and separated from a semiconductor substrate according to the present invention.

【図4】本発明に係る半導体素子の抗折応力試験法を説
明するための図である。
FIG. 4 is a diagram for explaining a bending stress test method for a semiconductor device according to the present invention.

【図5】本発明に係る半導体素子の抗折応力の特性図で
ある。
FIG. 5 is a characteristic diagram of bending stress of a semiconductor device according to the present invention.

【図6】本発明に係る砥石コスト及び製造コストを示す
図である。
FIG. 6 is a diagram showing a grindstone cost and a manufacturing cost according to the present invention.

【図7】第1の従来技術であるインフィード研削を示す
要部の側面図である。
FIG. 7 is a side view of a main part showing in-feed grinding as a first conventional technique.

【図8】第1の従来技術によって研削された半導体基板
の裏面図である。
FIG. 8 is a back view of a semiconductor substrate ground by the first conventional technique.

【図9】第2の従来技術であるクリープフィード研削を
示す要部の側面図である。
FIG. 9 is a side view of a main portion showing a second conventional technique, creep feed grinding.

【図10】第2の従来技術によって研削された半導体基
板の裏面図である。
FIG. 10 is a rear view of a semiconductor substrate ground by the second conventional technique.

【符号の説明】[Explanation of symbols]

28…半導体基板 29…オリエンテーションフラット 30…条痕 31…半導体素子 x…長辺 28 ... Semiconductor substrate 29 ... Orientation flat 30 ... Striations 31 ... Semiconductor element x ... Long side

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の裏面を所定の厚さとなるよ
うに研削した後、該半導体基板を切断分離して複数の半
導体素子を形成するようにした半導体素子の製造方法に
おいて、前記半導体基板の裏面に略直線状の条痕が形成
されるよう研削することを特徴とする半導体素子の製造
方法。
1. A method of manufacturing a semiconductor element, comprising: grinding a back surface of a semiconductor substrate to a predetermined thickness; then cutting and separating the semiconductor substrate to form a plurality of semiconductor elements. A method of manufacturing a semiconductor element, which comprises grinding so that a substantially linear scratch is formed on the back surface.
【請求項2】 半導体基板の裏面を所定の厚さとなるよ
うに研削した後、該半導体基板を切断分離して複数の方
形状の半導体素子を形成するようにした半導体素子の製
造方法において、前記半導体基板の裏面に略直線状の条
痕が形成されるよう研削すると共に、前記半導体素子の
長辺と該半導体素子の前記条痕とのなす角度が±20度
以下であることを特徴とする半導体素子の製造方法。
2. A method of manufacturing a semiconductor element, comprising: grinding a back surface of a semiconductor substrate to have a predetermined thickness, and then cutting and separating the semiconductor substrate to form a plurality of rectangular semiconductor elements. The back surface of the semiconductor substrate is ground so as to form substantially linear scratches, and the angle between the long side of the semiconductor element and the scratches of the semiconductor element is ± 20 degrees or less. Manufacturing method of semiconductor device.
【請求項3】 条痕とオリエンテーションフラットとの
なす角度が±20度以下であることを特徴とする請求項
1または請求項2記載の半導体素子の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the angle formed between the streak and the orientation flat is ± 20 degrees or less.
JP25176994A 1994-10-18 1994-10-18 Manufacture of semiconductor device Pending JPH08115893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25176994A JPH08115893A (en) 1994-10-18 1994-10-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25176994A JPH08115893A (en) 1994-10-18 1994-10-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH08115893A true JPH08115893A (en) 1996-05-07

Family

ID=17227651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25176994A Pending JPH08115893A (en) 1994-10-18 1994-10-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH08115893A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6951800B2 (en) 2001-10-19 2005-10-04 Fujitsu Limited Method of making semiconductor device that has improved structural strength
JP2008010213A (en) * 2006-06-27 2008-01-17 Matsushita Electric Works Ltd Device and method for manufacturing sealed glass tube for electrodeless lamp
JP2009069759A (en) * 2007-09-18 2009-04-02 Disco Abrasive Syst Ltd Method for machining liquid crystal substrate
US7579205B2 (en) 2004-04-27 2009-08-25 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device and thus-fabricated light emitting device
US7663151B2 (en) 2004-04-27 2010-02-16 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device and thus-fabricated light emitting device
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US7745246B2 (en) 2005-05-31 2010-06-29 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device
US7825008B2 (en) 2006-03-07 2010-11-02 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device and thus-fabricated light emitting device
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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6951800B2 (en) 2001-10-19 2005-10-04 Fujitsu Limited Method of making semiconductor device that has improved structural strength
KR100736347B1 (en) * 2001-10-19 2007-07-06 후지쯔 가부시끼가이샤 Method of making semiconductor device that has improved structural strength
US7579205B2 (en) 2004-04-27 2009-08-25 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device and thus-fabricated light emitting device
US7663151B2 (en) 2004-04-27 2010-02-16 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device and thus-fabricated light emitting device
US7745246B2 (en) 2005-05-31 2010-06-29 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device
US7825008B2 (en) 2006-03-07 2010-11-02 Shin-Etsu Handotai Co., Ltd. Method of fabricating light emitting device and thus-fabricated light emitting device
JP2008010213A (en) * 2006-06-27 2008-01-17 Matsushita Electric Works Ltd Device and method for manufacturing sealed glass tube for electrodeless lamp
JP2009069759A (en) * 2007-09-18 2009-04-02 Disco Abrasive Syst Ltd Method for machining liquid crystal substrate
JP2010103192A (en) * 2008-10-21 2010-05-06 Disco Abrasive Syst Ltd Grinding method
WO2016207941A1 (en) * 2015-06-22 2016-12-29 オリンパス株式会社 Imaging device for endoscope
JPWO2016207941A1 (en) * 2015-06-22 2018-04-05 オリンパス株式会社 Endoscopic imaging device
US10484581B2 (en) 2015-06-22 2019-11-19 Olympus Corporation Image pickup apparatus for endoscope

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