US5993292A - Production of notchless wafer - Google Patents

Production of notchless wafer Download PDF

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Publication number
US5993292A
US5993292A US09/036,944 US3694498A US5993292A US 5993292 A US5993292 A US 5993292A US 3694498 A US3694498 A US 3694498A US 5993292 A US5993292 A US 5993292A
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Prior art keywords
wafer
notch
mark
ingot
crystal orientation
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US09/036,944
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Hiroshi Oishi
Keiichiro Asakawa
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Super Silicon Crystal Research Institute Corp
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Super Silicon Crystal Research Institute Corp
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Assigned to SUPER SILICON CRYSTAL RESEARCH INSTITUTE CORP. reassignment SUPER SILICON CRYSTAL RESEARCH INSTITUTE CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ASAKAWA, KEIICHIRO, OISHI, HIROSHI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)

Abstract

A shallow notch 1 as a tentative mark is engraved on a periphery of an ingot at a position corresponding to a predetermined crystal orientation in the step of grinding the periphery of the ingot. After the ingot is sliced to wafers, a mark 2 for indication of a crystal orientation is carved on a sliced wafer at a position determined on the basis of the notch 1 by laser marking. Thereafter, the wafer is chamfered to a round shape, and the notch 1 is removed by the chamfering. Since a part where the mark 2 shall be carved is determined on the basis of the notch 1, the mark 2 is efficiently carved on the wafer without the necessity of subjecting each wafer to an X-ray analyzer.

Description

BACKGROUND OF THE INVENTION
The present invention relates to a method of producing a round-shape wafer on which a laser mark for indication of a crystal orientation is put instead of a notch or orientation flat.
A wafer sliced off an ingot is processed in various steps such as lapping, chamfering and etching. A mark for indication of a crystal orientation is carved on an edge of the wafer used in these steps. The mark is used for setting the wafer, when the wafer is scribed along a cleavage plane for instance.
Such marks are put on wafers by various methods.
OF method is the most popular one by which an orientation flat is formed at an edge of a wafer. The orientation flat is used for specifying a crystal orientation of the wafer in the subsequent processing steps. However, it is difficult to precisely align a wafer using the orientation, since the orientation flat is formed in a relatively broad area crossing an edge of the wafer at an obtuse angle. Besides, the orientation flat puts restrictions on a shape of an electrostatic chuck used for handling the wafer and causes harmful effects on dynamic balance during spin rotation of the wafer.
A notch engraved on an edge of a wafer is also used as a mark for indication of a crystal orientation. In this case, a notched edge shall be polished to specular glossiness, so as to distinctly detect the notched part during measuring in the subsequent steps. Engravement of the notch likely causes induction of residual stresses at the notched part. Although residual stresses put harmful influences on properties of the wafer, it is difficult to completely remove residual stresses.
Notchless wafers having laser marks for indication of a crystal orientation have been recently used in order to avoid these problems. The laser mark is carved on a front or back side of a wafer by partially melting a surface layer of the wafer with irradiation of a laser beam.
In a conventional laser marking method, each wafer is tested by an X-ray analyzer to detect a crystal orientation of the wafer, and a mark for indication of crystal orientation is put on at a proper position. A commonly used crystal orientation is <110>±1 degree. This method requires a marking operation for each wafer, resulting in poor productivity and heavy duty on the X-ray analyzer.
SUMMARY OF THE INVENTION
The present invention aims at efficient production of a notchless wafer without the necessity of testing each wafer for detecting a crystal orientation.
According to the present invention, a shallow notch extending along an axial direction of an ingot is engraved as a tentative mark for indication of a crystal orientation on a periphery of the ingot at a position corresponding to a predetermined crystal orientation in a step of grinding the periphery of the ingot. After the ingot is sliced to wafers, a mark for indication of the crystal orientation is put on a sliced wafer at a position determined on the basis of the notch. Thereafter, the sliced wafer is chamfered to a round shape, and the notch is removed by the chamfering.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flowchart for explaining the steps of producing a notchless wafer according to the present invention.
FIG. 2 is a schematic view illustrating a device for manually determining a position for carving a mark for indication of a crystal orientation on a wafer
PREFERRED EMBODIMENT OF THE INVENTION
In the newly proposed method, a notch 1 extending along an axial direction of an ingot is engraved on a periphery of the ingot at a position indicating a predetermined crystal orientation, when the ingot is ground at its periphery. The crystal orientation is measured by the same X-ray analyzer as that used for production of a notchless wafer in a conventional method.
Since the notch 1 will be removed in a chamfering step succeeding to carving a mark for indication of a crystal orientation, the notch 1 of 0.2-0.7 mm in depth is engraved on the periphery of the ingot. The notch 1 is as approximately a third shallow as a conventional notch for indication of a crystal orientation, so that the notch 1 can be easily engraved by slight grooving.
After the notch 1 is engraved on the periphery of the ingot, the ingot is sliced to wafers having a predetermined thickness by an inner diameter saw, a wire saw or the like.
Thereafter, a mark 2 for indication of a crystal orientation is carved on the sliced wafer using a hard laser marking device which outputs high energy laser beams. A position to be carved by the laser marking is determined on the basis of the notch 1 without necessity of subjecting every one wafer to an X-ray analyzer as in a conventional method.
The mark 2 for indication of a crystal orientation is carved in such depth that the mark 2 of 10 μm or deeper will remain in a finished wafer. Such depth of the mark 2 is easily controlled by adjustment of a laser power.
Other marks for indication of specification, identification, production number, user need, etc. may be carved by the same way in addition to the mark 2 for indication of a crystal orientation. These marks may be put on as a bar code at a position apart from the mark 2 for indication of a crystal orientation so as to distinguish them from the mark 2.
In order to automate the laser marking, a position of the notch 1 is detected by a video camera and an image processor, and a part where the mark 2 shall be carved is calculated from the detection result.
A device shown in FIG. 2 is used in case of manually determining a position for carving the mark 2. The device has rollers 4 for supporting a wafer 3 at one side. A notch pin 6 is pressed onto the opposite side of the wafer 3 by a spring 5. When the wafer 3 is in-plane rotated, the notch 1 moves along a peripheral direction and accepts the notch pin 6. As a result, the wafer 3 is fixed, and a position where the mark 2 shall be carved is specified.
After the mark 2 is carved on the wafer 3, the wafer 3 is chamfered to a round shape. The notch 1 is removed by the chamfering. Hereon, the notch 1 can be easily removed by slight chamfering, since the notch 1 is shallow compared with a notch engraved as a mark for indication of a crystal orientation in a conventional method.
The round wafer 3 is then lapped, polished and finished to a final product.
As mentioned above, a position where the mark 2 for indication of a crystal orientation shall be carved is determined on the basis of the notch 1, so that the mark 2 is efficiently put on the wafer 3 by laser marking without the necessity of subjecting each wafer to an X-ray analyzer as in a conventional method.
EXAMPLE
When a periphery of an ingot of 200 mm in diameter was ground, a notch 1 of 0.5 mm in depth extending along an axial direction of the ingot was engraved on the periphery of the ingot. The ingot was then sliced to wafers of 0.9 mm in average thickness by a wire saw.
A mark 2 for indication of a crystal orientation was carved at a depth of 0.09 mm on an edge of the wafer 3 at a position opposite to the notch 1 by a hard laser marking device with a laser power of 50 W. The edge of the wafer was then chamfered by 1.2 mm in diameter. The notch 1 was removed by this chamfering, and the wafer 3 was reformed to a round-shape 7 of 200 mm in diameter.
After the round-shape wafer 7 was lapped, polished and finished to a final state, depth of the mark 2 was 0.01 mm. Although the mark 2 became relatively shallower by these processes, the mark 2 of such depth was effective for detection of a crystal orientation.
According to the present invention as aforementioned, a shallow notch is engraved on a periphery of an ingot, the ingot is sliced to wafers, and then a mark for indication of a crystal orientation is carved on the sliced wafer by laser marking. Thereafter, the marked wafer is chamfered to a round shape, and the notch is removed by the chamfering.
Since a position where the mark shall be carved is determined on the basis of the notch, notchless wafers are efficiently produced without the necessity of subjecting each wafer to an X-ray analyzer as in a conventional. The marked wafer obtained in this way has improved handling ability in the subsequent steps due to its round shape.

Claims (2)

What is claimed is:
1. A method of producing a notchless wafer, comprising the steps of:
engraving a notch extending along an axial direction of an ingot on a periphery of said ingot at a position corresponding to a predetermined crystal orientation during grinding a periphery of said ingot;
slicing said ingot to wafers;
carving at least one laser mark for indication of a crystal orientation on said wafer at a position determined on the basis of said notch; and
chamfering said wafer to a round shape,
wherein said notch is engraved to a depth such that said notch is removed by said chamfering.
2. The method according to claim 1, wherein another laser mark for indication of identification of the wafer is carved on an edge of the wafer at a position apart from the laser mark for indication of crystal orientation.
US09/036,944 1997-03-11 1998-03-09 Production of notchless wafer Expired - Lifetime US5993292A (en)

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JP05599597A JP3213563B2 (en) 1997-03-11 1997-03-11 Manufacturing method of notchless wafer
JP9-055995 1997-03-11

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WO2001066361A1 (en) * 2000-03-09 2001-09-13 Intergen, Inc. Silicon wafer manufacturing system and method
US6659098B1 (en) * 1999-11-10 2003-12-09 Disco Corporation Rotary tool including a cutting blade and cutting apparatus comprising the same
EP1541286A1 (en) * 2003-12-11 2005-06-15 Gabriele Santi Method for obtaining laminar elements
US20060131696A1 (en) * 2001-03-21 2006-06-22 Kabushiki Kaisha Toshiba Semiconductor wafer with ID mark, equipment for and method of manufacturing semiconductor device from them
US20100300259A1 (en) * 2009-05-29 2010-12-02 Applied Materials, Inc. Substrate side marking and identification
CN101330000B (en) * 2001-03-21 2011-06-08 株式会社东芝 Semiconductor wafer with id mark, equipment for and method of manufacturing semiconductor device from them
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
CN103489752A (en) * 2013-09-26 2014-01-01 中国科学院半导体研究所 Surface orientation identification method of crystal bar with polygonal cross section and substrate slice
US20150083104A1 (en) * 2013-09-26 2015-03-26 Siltronic Ag Method for simultaneously cutting a multiplicity of wafers from a workpiece
CN105765702A (en) * 2013-12-03 2016-07-13 信越半导体株式会社 Chamfering device and notchless wafer manufacturing method
US9536838B1 (en) * 2015-08-10 2017-01-03 Infineon Technologies Ag Single crystal ingot, semiconductor wafer and method of manufacturing semiconductor wafers
US9589901B2 (en) 2014-02-11 2017-03-07 Samsung Electronics Co., Ltd. Semiconductor wafers including indications of crystal orientation and methods of forming the same
CN106571320A (en) * 2015-10-08 2017-04-19 英飞凌科技股份有限公司 Method of manufacturing semiconductor wafers and method of manufacturing semiconductor device
US9806036B2 (en) 2016-01-08 2017-10-31 Samsung Electronics Co., Ltd. Semiconductor wafer, semiconductor structure and method of manufacturing the semiconductor wafer
CN112720885A (en) * 2020-12-15 2021-04-30 西安奕斯伟硅片技术有限公司 Crystal bar slotting method and crystal bar slotting device
US11854995B2 (en) * 2020-04-29 2023-12-26 Semiconductor Components Industries, Llc Supports for thinned semiconductor substrates and related methods

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JP6427320B2 (en) * 2014-01-27 2018-11-21 株式会社東京精密 Wafer grinding apparatus and wafer manufacturing method
JP6286256B2 (en) * 2014-03-31 2018-02-28 株式会社東京精密 Wafer marking / grinding apparatus and wafer marking / grinding method
JP6328485B2 (en) * 2014-05-13 2018-05-23 株式会社ディスコ Wafer processing method
JP6672053B2 (en) * 2016-04-18 2020-03-25 株式会社ディスコ Wafer processing method
CN106370679A (en) * 2016-11-02 2017-02-01 中国电子科技集团公司第四十六研究所 Semiconductor wafer notch groove crystal orientation measuring device and use method

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US5227339A (en) * 1990-05-18 1993-07-13 Fujitsu Limited Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device composed of the substrate
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Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6659098B1 (en) * 1999-11-10 2003-12-09 Disco Corporation Rotary tool including a cutting blade and cutting apparatus comprising the same
WO2001066361A1 (en) * 2000-03-09 2001-09-13 Intergen, Inc. Silicon wafer manufacturing system and method
US6482661B1 (en) * 2000-03-09 2002-11-19 Intergen, Inc. Method of tracking wafers from ingot
US20060131696A1 (en) * 2001-03-21 2006-06-22 Kabushiki Kaisha Toshiba Semiconductor wafer with ID mark, equipment for and method of manufacturing semiconductor device from them
US7700381B2 (en) * 2001-03-21 2010-04-20 Kabushikia Kaisha Toshiba Semiconductor wafer with ID mark, equipment for and method of manufacturing semiconductor device from them
CN101330000B (en) * 2001-03-21 2011-06-08 株式会社东芝 Semiconductor wafer with id mark, equipment for and method of manufacturing semiconductor device from them
EP1541286A1 (en) * 2003-12-11 2005-06-15 Gabriele Santi Method for obtaining laminar elements
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
US9390906B1 (en) 2007-06-01 2016-07-12 Rubicon Technology, Inc. Method for creating asymmetrical wafer
US8623136B1 (en) 2007-06-01 2014-01-07 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
US20100300259A1 (en) * 2009-05-29 2010-12-02 Applied Materials, Inc. Substrate side marking and identification
US9333673B2 (en) * 2013-09-26 2016-05-10 Siltronic Ag Method for simultaneously cutting a multiplicity of wafers from a workpiece
KR101670132B1 (en) 2013-09-26 2016-10-27 실트로닉 아게 Method for simultaneously cutting a multiplicity of wafers from a workpiece
CN104511975A (en) * 2013-09-26 2015-04-15 硅电子股份公司 Method for simultaneously cutting a multiplicity of wafers from a workpiece
US20150083104A1 (en) * 2013-09-26 2015-03-26 Siltronic Ag Method for simultaneously cutting a multiplicity of wafers from a workpiece
CN103489752A (en) * 2013-09-26 2014-01-01 中国科学院半导体研究所 Surface orientation identification method of crystal bar with polygonal cross section and substrate slice
KR20150034658A (en) * 2013-09-26 2015-04-03 실트로닉 아게 Method for simultaneously cutting a multiplicity of wafers from a workpiece
CN105765702B (en) * 2013-12-03 2018-11-06 信越半导体株式会社 The manufacturing method of chamfer processing method and device and non-incision wafer
US10002753B2 (en) 2013-12-03 2018-06-19 Shin-Etsu Handotai Co., Ltd. Chamfering apparatus and method for manufacturing notchless wafer
CN105765702A (en) * 2013-12-03 2016-07-13 信越半导体株式会社 Chamfering device and notchless wafer manufacturing method
US9589901B2 (en) 2014-02-11 2017-03-07 Samsung Electronics Co., Ltd. Semiconductor wafers including indications of crystal orientation and methods of forming the same
US9536838B1 (en) * 2015-08-10 2017-01-03 Infineon Technologies Ag Single crystal ingot, semiconductor wafer and method of manufacturing semiconductor wafers
CN106449361A (en) * 2015-08-10 2017-02-22 英飞凌科技股份有限公司 Single crystal ingot, semiconductor wafer and method of manufacturing semiconductor wafers
CN106449361B (en) * 2015-08-10 2019-10-15 英飞凌科技股份有限公司 Single-crystal boule, semiconductor crystal wafer and the method for manufacturing semiconductor crystal wafer
CN106571320A (en) * 2015-10-08 2017-04-19 英飞凌科技股份有限公司 Method of manufacturing semiconductor wafers and method of manufacturing semiconductor device
CN106571320B (en) * 2015-10-08 2019-12-31 英飞凌科技股份有限公司 Method of manufacturing semiconductor wafer and method of manufacturing semiconductor device
US9806036B2 (en) 2016-01-08 2017-10-31 Samsung Electronics Co., Ltd. Semiconductor wafer, semiconductor structure and method of manufacturing the semiconductor wafer
US11854995B2 (en) * 2020-04-29 2023-12-26 Semiconductor Components Industries, Llc Supports for thinned semiconductor substrates and related methods
CN112720885A (en) * 2020-12-15 2021-04-30 西安奕斯伟硅片技术有限公司 Crystal bar slotting method and crystal bar slotting device
CN112720885B (en) * 2020-12-15 2023-02-03 西安奕斯伟材料科技有限公司 Crystal bar slotting method and crystal bar slotting device

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JPH10256106A (en) 1998-09-25
KR100458694B1 (en) 2005-01-15
DE19810546A1 (en) 1998-09-17
JP3213563B2 (en) 2001-10-02
KR19980080076A (en) 1998-11-25

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