JPH10256332A - Method and equipment for manufacturing semiconductor wafer for evaluation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor wafer for evaluation, which enables measurement of cracks, processing strains and the like introduced in slicing. SOLUTION: A wafer as a test piece 6 is fixed on a stage 11. A polishing tool 12 facing the surface of the wafer is lowered by the distance in proportion to the moving distance of the stage 11 moving in one direction. At the surface of the test piece 6, a polishing groove 17, which is extending into the direction of the wafer diameter and continuously becomes deep, is formed. The wafer surface at both sides of the polishing groove 17 remains as the unpolished initial surface. Since the long polishing groove 17 is formed in this way, the distribution of the defect such as the cracks, the processing strains and the like can be measured highly accurately. The depth of the defective part is also measured directly by the comparison with the initial surface at both sides of the polishing groove 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer for evaluation used to detect a defect such as a crack or a processing strain introduced into the surface of a wafer cut out of an ingot or a wrapped wafer. The present invention relates to a manufacturing method and an apparatus.

[0002]

2. Description of the Related Art A semiconductor wafer is obtained by slicing an ingot with an internal ring, a wire saw or the like. For semiconductor wafers cut from ingots,
Cracks and distortions due to processing are introduced. For example, as shown in FIG. 1, a surface layer including a crack layer 3, a plastic flow layer 4, and the like is formed on a perfect crystal silicon 1 via an elastic deformation layer 2. In the crack layer 3, minute cracks generated by the processing are distributed and reach a depth of about 10 μm from the wafer surface. In order to set processing conditions in the subsequent lapping step according to the depth of the crack layer 3, it is necessary to measure the depth of the crack layer 3 in advance. A sample used for measuring the depth of the crack layer is usually prepared by an angle polishing method. In the angle polishing method, as shown in FIG. 2, a test piece 6 is attached to an inclined surface of an attaching block 5, attached to a guide ring 7, and the test piece 6 held in an inclined state is polished by a polishing plate 8. .

As shown in FIG. 3, the polished test piece 6 is polished obliquely at an inclination angle θ corresponding to the inclined surface of the attaching block 5. The crack layer 3 on the surface of the test piece 6 exposes the crack layer cross section 9 as an inclined surface that spreads in the thickness direction by angle polishing. Assuming that the thickness of the crack layer 3 is D, the length of the cross section of the crack layer generated by the angle polishing is represented by L = L / Sinθ. Normal,
Since the angle polishing is performed by setting the inclination angle θ to 5.7 degrees,
L = D / sin 5.7 degrees = D × 10. That is, the crack layer 3 having a thickness D is observed as a crack layer cross section 9 having a width L that is magnified ten times.

[0004]

In the conventional angle polishing method, cracks are detected by microscopic observation of the cross section 9 of the crack layer. The depth from the wafer surface at the position where the crack was detected cannot be measured by comparison with the test piece surface 10 because the entire area of the edge of the test piece 6 becomes a crack layer section 9 inclined as shown in FIG. , Based on the angle component. However, it is not possible to know whether or not the test piece 6 is processed at the exactly set angle, and the accuracy and reliability of the measured depth are lacking. In addition, since the test piece 6 fixed to the attachment block 5 is polished, if the angle is reduced so that the length L of the crack section layer 9 increases,
The pressure distribution applied to the test piece 6 from the initial stage of processing tends to fluctuate from place to place, and the reliability in the depth direction becomes poor. As a result, the length L of the crack section layer 9 that can be formed is restricted, and a section layer in which the crack layer 3 can be observed in detail cannot be obtained. The present invention has been devised in order to solve such a problem. By forming a processing groove extending in the diameter direction of the wafer and having a continuously changing depth, the processing distortion introduced into the crack layer is provided. It is an object of the present invention to obtain an evaluation semiconductor wafer capable of easily and accurately detecting defects such as cracks and the like.

[0005]

In order to achieve the object, a method for preparing a semiconductor wafer for evaluation according to the present invention comprises: a polishing tool having a wafer as a test piece fixed on a stage and facing a wafer surface; Lowering the wafer by a distance proportional to the moving distance of the stage moving in one direction, forming polishing grooves extending in the wafer diameter direction and continuously deepening on the wafer surface, leaving the wafer surface on both sides of the polishing grooves unpolished It is characterized by the following. In addition, the apparatus for producing a semiconductor wafer for evaluation includes a movable stage on which the wafer is fixedly arranged,
A vertically movable polishing tool arranged opposite to the wafer surface,
A control mechanism for outputting a control signal for lowering the polishing tool in proportion to the moving distance of the stage moving in one direction to the lifting mechanism of the polishing tool, wherein the outer diameter of the polishing tool is smaller than the surface area of the wafer. .

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An evaluation semiconductor wafer preparing apparatus according to the present invention includes a movable stage 11 and a vertically movable polishing tool 12, as shown in FIG. Polishing tool 12
Has a diameter sufficiently smaller than the surface area of the wafer as the test piece 6, and has a polishing pad 16 attached to the lower end. A plurality of position sensors 13 are arranged along the moving direction of the stage 11, and a signal detected by the position sensor 13 is input to the control mechanism 14. Control mechanism 1
In step 4, the polishing tool 12
Is calculated, and a control signal s is output to the elevating device 15 provided with a step motor or the like.

The height of the polishing tool 12 is adjusted in proportion to the amount of movement of the stage 11, and a polishing groove 17 that is continuously deepened by the polishing pad 16 is formed on the surface of the test piece 6.
Since the surface area of the test piece 6 is sufficiently larger than that of the polishing tool 12, the polishing groove 17 becomes longer in the diameter direction as shown in FIG. Further, since both sides of the polishing groove 17 are not processed by the polishing tool 17, the unpolished initial surface 18 remains. When the polishing grooves 17 are formed in this manner, the length of the crack section layer 9 that is sufficiently exposed can be increased as compared with the case of the conventional angle polishing. In addition, as shown in FIG. 6, since the boundary between the crack layer 3 and the healthy crystal layer 1 is exposed to the crack cross-section layer 9 with a large width, the distribution and amount of defects such as cracks and processing distortion can be accurately detected. In addition, since the initial surface 18 is present on the side of the crack section layer 9, it is possible to directly measure the depth of the portion where the defect is detected. The obtained measurement result is fed back to the slicing step and used for adjusting the processing conditions. It is also used for setting conditions for the subsequent lapping process. Similarly, a sample for measuring a defective portion such as a crack or a processing distortion is created for a wafer subjected to processing such as lapping and grinding.

[0008]

[Example] 200m in diameter sliced from an ingot
m, a wafer having an average thickness of 1 mm was used for the test piece 6.
As the polishing tool 12, a polishing tool having an outer diameter of 20 mm to which a polishing pad 16 made of nonwoven fabric was attached was used. The stage 11 on which the test piece 6 was fixedly arranged was moved in one direction at a speed of 1 mm / min. While the stage 11 is moving, the polishing tool 12
The sample was rotated at 500 rpm while being lowered at a speed of m / min, and pressed against the test piece 6 with a pressing force of 300 N / mm ² . After polishing was continued for 40 minutes, the polishing tool 12 was raised. Observation of the polished surface of the test piece 6 revealed that a polishing groove 17 having a length of 40 mm extending in the diameter direction was formed. The polishing groove 17 has a width of 20 mm and has a test piece 6 at the beginning.
At the end and 40 μm deep at the end. Also, both sides of the polishing groove 17 are the unpolished initial surface 1
It was 8.

Observation of the crack layer cross section 9 exposed in the polishing groove 17 revealed that a large number of cracks were detected up to a position 20 mm from the start end, the cracks gradually decreased, and no cracks were detected 30 mm away from the start end. . The positions 20 mm and 30 mm from the starting end were found to correspond to a depth of 20 μm and 30 μm, respectively, by comparison with the initial surfaces 18 on both sides. As described above, since the amount of crack generation and the depth of the defective portion 8 can be measured with high accuracy, highly accurate information necessary for adjusting the slicing and polishing conditions can be obtained.

[0010]

As described above, the evaluation semiconductor wafer prepared according to the present invention has an inclined surface in which the polishing grooves formed for detecting a defective portion are continuously deepened. For this reason, a defective portion is detected with much higher accuracy than a conventional evaluation semiconductor wafer prepared by angle polishing, and the depth of the defective portion can be easily and accurately measured by comparing with the initial surface.

[Brief description of the drawings]

FIG. 1 is a cross section of a wafer having a surface layer in which cracks have been introduced by slicing.

FIG. 2 Preparation of a semiconductor wafer for evaluation by conventional angle polishing

FIG. 3 is a sectional view of a crack layer having an inclination formed by angle polishing.

FIG. 4 is a view showing the preparation of an evaluation semiconductor wafer according to the present invention.

FIG. 5 is a semiconductor wafer for evaluation on which polishing grooves extending in the diameter direction are formed.

FIG. 6 is a cross section of a semiconductor wafer for evaluation in which a polishing groove is formed.

[Explanation of symbols]

1: perfect crystalline silicon 2: elastic deformation layer 3: crack layer 4: plastic fluidized bed 5: sticking block
6: Test piece (wafer) 7: Guide ring 8: Polishing board 9: Cross section of exposed crack layer 10:
Specimen surface 11: Stage 12: Polishing tool
13: Position sensor 14: Control mechanism 15 :: Elevating mechanism 16: Polishing pad 17: Polishing groove 18:
Initial surface θ: inclination angle D: crack layer thickness L: length of exposed crack layer cross section

Claims (2)

[Claims] 1. A wafer as a test piece is fixed on a stage, a polishing tool opposed to a wafer surface is lowered by a distance proportional to a moving distance of a stage moving in one direction, and extends in a wafer diameter direction. A method for producing a semiconductor wafer for evaluation, in which a polishing groove that becomes continuously deep is formed on a wafer surface, and the wafer surface on both sides of the polishing groove is left unpolished. And a control signal for lowering the polishing tool in proportion to the moving distance of the stage moving in one direction. And a control mechanism for outputting the polishing tool to a lifting / lowering mechanism of the polishing tool, wherein the polishing tool has an outer diameter smaller than the surface area of the wafer.