JPH10221413A5 - - Google Patents

Info

Publication number
JPH10221413A5
JPH10221413A5 JP1997369910A JP36991097A JPH10221413A5 JP H10221413 A5 JPH10221413 A5 JP H10221413A5 JP 1997369910 A JP1997369910 A JP 1997369910A JP 36991097 A JP36991097 A JP 36991097A JP H10221413 A5 JPH10221413 A5 JP H10221413A5
Authority
JP
Japan
Prior art keywords
integrated circuit
operating
debug interface
target system
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1997369910A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10221413A (ja
Filing date
Publication date
Priority claimed from US08/766,660 external-priority patent/US5828824A/en
Application filed filed Critical
Publication of JPH10221413A publication Critical patent/JPH10221413A/ja
Publication of JPH10221413A5 publication Critical patent/JPH10221413A5/ja
Pending legal-status Critical Current

Links

JP9369910A 1996-12-16 1997-12-16 拡張されたオペレーティング・モードを用いて集積回路をデバッグする方法 Pending JPH10221413A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US766660 1996-12-16
US08/766,660 US5828824A (en) 1996-12-16 1996-12-16 Method for debugging an integrated circuit using extended operating modes

Publications (2)

Publication Number Publication Date
JPH10221413A JPH10221413A (ja) 1998-08-21
JPH10221413A5 true JPH10221413A5 (enExample) 2005-07-28

Family

ID=25077130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9369910A Pending JPH10221413A (ja) 1996-12-16 1997-12-16 拡張されたオペレーティング・モードを用いて集積回路をデバッグする方法

Country Status (3)

Country Link
US (1) US5828824A (enExample)
EP (1) EP0848329A3 (enExample)
JP (1) JPH10221413A (enExample)

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