JPH10221413A - 拡張されたオペレーティング・モードを用いて集積回路をデバッグする方法 - Google Patents

拡張されたオペレーティング・モードを用いて集積回路をデバッグする方法

Info

Publication number
JPH10221413A
JPH10221413A JP9369910A JP36991097A JPH10221413A JP H10221413 A JPH10221413 A JP H10221413A JP 9369910 A JP9369910 A JP 9369910A JP 36991097 A JP36991097 A JP 36991097A JP H10221413 A JPH10221413 A JP H10221413A
Authority
JP
Japan
Prior art keywords
debug
test
interface
integrated circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9369910A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10221413A5 (enExample
Inventor
Gary L Swoboda
エル．スウオボダ ゲイリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH10221413A publication Critical patent/JPH10221413A/ja
Publication of JPH10221413A5 publication Critical patent/JPH10221413A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Debugging And Monitoring (AREA)
JP9369910A 1996-12-16 1997-12-16 拡張されたオペレーティング・モードを用いて集積回路をデバッグする方法 Pending JPH10221413A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US766660 1996-12-16
US08/766,660 US5828824A (en) 1996-12-16 1996-12-16 Method for debugging an integrated circuit using extended operating modes

Publications (2)

Publication Number Publication Date
JPH10221413A true JPH10221413A (ja) 1998-08-21
JPH10221413A5 JPH10221413A5 (enExample) 2005-07-28

Family

ID=25077130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9369910A Pending JPH10221413A (ja) 1996-12-16 1997-12-16 拡張されたオペレーティング・モードを用いて集積回路をデバッグする方法

Country Status (3)

Country Link
US (1) US5828824A (enExample)
EP (1) EP0848329A3 (enExample)
JP (1) JPH10221413A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000030499A (ja) * 1998-06-12 2000-01-28 Waferscale Integration Inc 汎用ポ―トをｊｔａｇポ―トとして利用可能なメモリチップ
JP2001189387A (ja) * 1999-10-28 2001-07-10 Advantest Corp システムオンチップの設計検証方法および装置
JP2004500712A (ja) * 2000-01-18 2004-01-08 ケイデンス・デザイン・システムズ・インコーポレーテッド 多数の回路ブロックを有するチップ用階層試験回路構造

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000030499A (ja) * 1998-06-12 2000-01-28 Waferscale Integration Inc 汎用ポ―トをｊｔａｇポ―トとして利用可能なメモリチップ
JP2010160895A (ja) * 1998-06-12 2010-07-22 St Microelectron Inc 汎用ポートをｊｔａｇポートとして利用可能なメモリチップ
JP2001189387A (ja) * 1999-10-28 2001-07-10 Advantest Corp システムオンチップの設計検証方法および装置
JP2004500712A (ja) * 2000-01-18 2004-01-08 ケイデンス・デザイン・システムズ・インコーポレーテッド 多数の回路ブロックを有するチップ用階層試験回路構造

Also Published As

Publication number Publication date
US5828824A (en) 1998-10-27
EP0848329A2 (en) 1998-06-17
EP0848329A3 (en) 1998-11-04

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