GB2430768A

GB2430768A - Reconfigurable integrated circuits

Info

Publication number: GB2430768A
Application number: GB0519741A
Authority: GB
Inventors: Klaus Dieter Mcdonald-Maier; Andrew Brian Thomas Hopkins
Original assignee: University of Kent at Canterbury
Current assignee: University of Kent at Canterbury
Priority date: 2005-09-28
Filing date: 2005-09-28
Publication date: 2007-04-04
Also published as: GB0519741D0; WO2007036723A1

Abstract

An integrated circuit assembly comprises first function circuitry (100,106) and debug circuitry (112) for testing of the first function circuitry. The debug circuitry comprises detection circuitry (120,122) for monitoring signals of the first function circuitry and a controller (123) for controlling the configuration of the detection circuitry (120,122). The detection circuitry is configurable into a plurality of different configurations in which different detection circuitry resources are allocated to the detection of different signals of the first function circuitry. This enables the debug circuitry to be configurable in response to the configuration of the function circuitry.

Description

RECONFIGURABLE INTEGRATED CIRCUiTS

Field of the invention

This invention relates generally to the configuration of integrated circuits, and particularly but not exclusively to the control of a debug system of an integrated circuit assemb]y in which the circuitry being tested is reconfigurable.

Background of the invention

An integrated circuit assembly is usually a sub-assembly of a larger assembly known as the I 0 system. The integrated circuit assembly contains function circuits to implement part or all of the system's intended behaviour, infrastructure circuits that support other circuits by providing features such as on-chip communication, test circuits and debug circuits.

A debug support strategy is a means for aiding the development of both the system and the integrated circuit assembly. By convention, methods of realising a debug support strategy include supplenienting the function circuits with debug circuits designed primarily for aiding development of the system, and test circuits to allow testing of the system integrity.

Typical system development tasks include testing, verification and debugging. Debugging is where the sources of behavioural anomalies are identified and the system changed such that the system behaviour is closer to the system specification. The debug circuits usually include a means of communicating with an external development tool such as a debug host computer.

The conventional approach for debugging is to use a condition detection unit to monitor specific bussed signals from a single statically associated function circuit, such that a debug event is generated when the value of the signal matches a predetermined condition loaded into compare register debug circuits using the external tool. For example, a bussed signal value may he determined to fall within a specified range of interest. This debug event is used to initiate a predeterthined action within the integrated circuit assembly; example actions include starting/stopping function circuits such as a processor core, and signalling debug circuits to take action. Typical actions for the debug circuits include controlling a trace of the signals fron-i a function circuit.

Various improvements have been proposed to condition detection debug circuits such as using: multiple detection units combined in one detection assembly to detect complex conditions involving different signals from the same function circuit; multiple detection units and/or detection assemblies that monitor signals from different function circuits creating cross-triggers; sequential circuits such as counters or state-machines to detect sequences of operation; and a multiplexer so that the developer can use the external tool to change which data path through a communication switch is monitored by a detection assembly.

Combinations of the above improvements have been proposed.

Provision of a debug support strategy is a compromise between useful debugging resources and circuit area. One disadvantage of a static association / attachment of detection assemblies with a single bussed signal from a single function circuit is that the balance of monitoring resources between each bussed signal and/or each function circuit cannot be adjusted to achieve best results for a given debugging challenge. For example, some signals may require few detection units whereas other signals from other function units may require many detection units but will be allocated insufficient resources, while other bussed signals have idle detection units.

A solution allowing the developer to choose which one of a plurality of data paths is monitored by a detection assembly may also be inadequate, as while monitoring one path, important information will be unmonitored on the others.

Therefore a solution is required that can monitor all bussed signals from all function circuits but has the ability to ensure that best use is made of the available resources.

Summary of the invention

According to the invention, there is provided an integrated circuit assembly, comprising: first function circuitry; and debug circuitry for monitoring and testing of the first function circuitry, wherein the debug circuitry comprises: detection circuitry for monitoring signals of the first function circuitry; and a controller for controlling the configuration of the detection circuitry, such that the detection circuitry is configurable into a plurality of different configurations in which different detection circuitry resources are allocated to the detection of different signals of the first function circuitry.

In this arrangement, debug circuitry is reconfigurable so that the debug resources can be matched to the configuration of the circuitry being monitored, and this allows the efficient and dynamic allocation of the debug capability.

A basic dedicated condition detection assembly can be connected to individual or bussed signals from the function circuitry that are likely to be of significant interest to the developer.

This plurality of basic detection assemblies detects basic conditions such as an address being within a range. The information collected by this first arrangement of detection circuitry are then used by one or more debug control units to make active decisions about the level of resources required by each function circuit and its bussed signals.

A second supplementary arrangement of condition detection assemblies can then each be cormected to several bussed signals from several function circuits by way of a multiplexer or similar to create a hierarchical structure of detection units. Each level may monitor the same or different bussed signals and could extend to a third or greater level. The debug control unit can then actively control the bussed signals that each condition detection unit monitors while the system operates either with or without interaction from the external tool or impacting the system behaviour.

The debug controller can make adjustments to the compare registers used within the condition detection units in all levels of the detection hierarchy based on the information collected from a wide variety of sources, not just from the signals being actively monitored. For example, in an integrated circuit where the function circuitry can be reconfigured at runtime, the debug control unit can act on the changes to the architecture or similar to make dynamic adjustments to the debug resource allocations.

In general terms, a first arrangement of circuitry adapts its architecture to changes in architecture of a second arrangement of circuitry. In some configurations, bussed signals may become redundant allowing resources to be moved entirely to other signals, such resources may include trace generation and qualification circuits. Another specific advantage of this method is that resources are shared between function units potentially allowing a reduced number of detection units to provide more comprehensive / improved monitoring of both symmetric and asymmetric multi-processing systems. Changes made by the debug control unit or a potential inability to meet the resource requirements can be reported to the developer using the trace infrastructure that is already part of the debug circuitry, as used to record to the behaviour of the function circuits.

The debug controller preferably has a processing and control capability and the detection units have a monitoring capability. The resources can then be used to provide condition monitoring of the integrated circuit assembly andlor the system when not being used for conventional development support purposes. The decisions made based on information collected while providing condition monitoring can be used by the function circuits to shut part or all of the system down in a controlled manner. This is useful in safety critical systems where function units may operate in parallel on identical or complementary data inputs and should generate identical or complementary outputs.

As mentioned above, the detection circuitry may comprise a first plurality of detection circuits and a second plurality of detection circuits. Each one of the first plurality of detection circuits can be associated with a predetermined resource of the first function circuitry, and each one of the second plurality of detection circuits can be configurable to be associated with a selected one of a plurality of the predetermined resources of the first function circuitry. This provides a first level of non-configurable detection circuits and a second level of configurable detection circuits.

The configuration of the detection circuitry can be variable based on configuration information of the first function circuitry, so that the debug configurations responds to the configuration of the circuit being tested/monitored.

The first function circuitry may comprise one or more of processor circuits, interface circuits, memory circuits.

The debug circuitry can further comprise a switching unit for switching between configurations of the detection circuitry under the control of the controller. The detection circuitry can be configurable between a first configuration in which a first set of signals the first function circuitry are monitored and a second configuration in which one or more of the first set of signals the first function circuitry are not monitored. This allows configurations in which certain signals/components of the function circuitry do not need to be monitored.

Test circuitry can be provided, communicating with the controller for testing of the debug and/or function circuitry. For example, with the test circuitry testing the debug circuitry, the configuration of the detection circuitry can be variable by the controller in response to the test results. With the test circuitry testing the function circuitry, the configuration of the function circuitry can be variable by the controller in response to the test results.

The configuration of the detection circuitry can be changed automatically (i.e. without intervention from an external development tool) by the controller in response to a change in the configuration of the first function circuitry.

The invention also provides an integrated circuit assembly, comprising first circuitry, and second circuitry for communication with the first circuitry, wherein the first circuitry is configurable between a plurality of configurations, and wherein the second circuitry comprises a plurality of circuit elements, each communicating with portions or signals of the first circuitry, a controller for controlling the configuration of the plurality of circuit elements, such that the plurality of circuit elements is configurable into a plurality of different configurations in which different circuit elements communicate with different portions or signals of the first circuitry in dependence on the configuration of the first circuitry.

The invention also provides a method of performing a debug operation within an integrated circuit assembly, for debugging of first function circuitry (100,106), wherein the method comprises: controlling the configuration of detection circuitry forming part of the integrated circuit assembly in dependence on the configuration of the first function circuitry, wherein different detection circuitry resources are allocated to the detection of different signals of the first function circuitry in the different configurations; using the detection circuitry to monitor signals of the first function circuitry; and providing the monitored signals to an external development tool.

Brief description of the drawings

Specific embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:- Figure 1 illustrates the integrated circuit assembly with debug support circuitry of the invention connected to the external tool; Figure 2 illustrates a first more detailed example of the invention, in which the debug support circuitry has condition detection assemblies and in which the bussed signal associated with supplementary detection assemblies is dynamically adaptable; Figure 3 illustrates a second more detailed example of the invention, in which the debug support circuitry has condition detection assemblies and in which the bussed signal associated with all detection assemblies is dynamically adaptable; and Figure 4 illustrates a third more detailed example of the invention in which the debug support circuitry has runtime test circuitry.

Detailed description

An aspect of the invention provides an integrated circuit assembly with debug support circuits comprising decision making circuitry that receives information from a first arrangement of condition detection circuits that monitor signals associated with the function circuitry being monitored. The decision making circuitry uses collected information to make decisions about how best to control the condition detection circuitry. This condition detection circuitry may include one or several supplementary arrangements of reconfigurable condition detection circuits.

Figure 1 is a schematic diagram and is used to explain the invention in general terms, and Figure 2 shows a first more detailed embodiment.

The invention can be considered to implement a "debug condition detection system". This is used to detect the condition of the circuitry under test and thereby to control the configuration of the debug system.

Referring to the drawings, the debug condition detection system 126 is part of the debug circuitry 112 which is used to aid use of the function circuitry 100 106. The function circuitry includes active circuits 1 00 such as a processor or fast peripheral and other passive peripheral circuits 106 such as a memory.

Infrastructure circuits 104 provide services used by both function circuitry 100 106 and debug circuitry 112. Function circuitry 100 106 and debug circuitry 112 and infrastructure circuitry 104 are all components of the integrated circuit assembly 11 0 which is part of the overall system 111.

The function circuitry 100 is monitored by the condition detection circuits via a data interface 101 which provides details of data related accesses, and a state interface 102 which provides details of the function circuit behaviour such as: mode, status and or program.

The debug condition detection system contains decision making circuitry 123 which uses information collected via the data interface 101 and state interface 102 to control the settings of a first arrangement of detection circuits 120 and a supplementary arrangement of detection circuits 122 (shown in Figure 2).

The decision making circuitry 123 acts as a controller for controlling the configuration of the detection circuitry, and selects the signals monitored by the plurality of detection circuits 120 122 using a switching unit 121. The switching unit 121 also provides a means to change the function circuitry that is traced by debug trace circuitry 125 under control of the decision making circuitry 123. The trace generated by the trace circuitry is transferred by means of trace infrastructure circuits 124 to a debug trace interface 103 which is used to communicate with an external tool 108 which is not part of the system.

Iii the preferred embodiment, each circuit of the first arrangement of detection circuits 120 is associated with a single bussed signal, such as a bus or program address from a single function circuit assembly. The supplementary detection circuits 122 are constructed such that each detection circuit can be connected to all or any one of a subset of the signals from all or a subset of the function circuits 100. This connection is made using one or several switching units 121 under the control of the decision making circuitry 123. Thus, the debug circuitry 112 is dynamically adaptable.

The decision making circuitry 123 is a debug control unit which uses a program means or similar to make active decisions about the best configuration based on a program which can be static or adaptive. The condition detection circuitry 120 122 contams compare circuits similar to those used in conventional debug systems that generate an event when certain conditions are met, such as the monitored signal value being within a range defined by compare registers.

Unlike conventional detection systems, the values held in the compare registers of this invention are modifiable by the decision making circuits 123 without intervention of the external tool 108.

The decision to switch supplementary detection circuitry 122 between different signals of the function circuitry 100 is also made without intervention from the external tool. Circuit settings can be adjusted using the external tool 108 as an overriding control means. The decision making circuitry 123 optionally reports its actions and status such as a shortage or failure of resources to the external tool 108 and developer using the trace infrastructure 124, trace generation circuitry 125 and either a trace interface 103 or other external infrastructure interface 107.

When not used for conventional debug purposes the decision making circuitry 123 optionally uses the condition detection circuitry 120 122 to monitor the overall system 111 as a means of detecting degradation of mechanical parts or sensors via analysis of data inputs. The status information collected by the decision making circuitry 123 is supplied to the active function circuitry 100 by placing it in shared peripheral function circuitry 106 using the infrastructure circuitry 104.

A second embodiment shown in Figure 3 has the first arrangement of detection circuits connected to the data interface 101 and state interface 102 via one or several switching units 121 so that a set of signals identified as potentially interesting by the integrated circuit assembly/designer can be configured to have no associated detection circuitry 120 122. This embodiment allows the invention to be used with reconfigurable function circuits where some signals may not be used in all configurations. In this embodiment, the decision making circuitry receives information detailing reconfiguration activity via the state interfaces 102 so that it can autonomously respond to configuration changes in the function circuitry 100 106 and or infrastructure circuitry 104 by reallocating debug circuit resources to the most appropriate signals. Hence, a first arrangement of circuitry adapts its architecture to changes in architecture of a second arrangement of circuitry. - 10-

A third embodiment shown in Figure 4 has runtime test circuitry 128 connected to the decision making circuitry 123 and a test interface 127 to receive test signals from the rest of the integrated circuit assembly 110 as a means of diagnosis, so that dynamically adaptable parts of the integrated circuit assembly 110 can be reconfigured to not use defective circuitry. As an example; In reference to Figure 4 and the supplementary detection circuitry 122; a defective first supplementary detection circuit 129 could be disabled and a second supplementary detection circuit 130 switched in circuit as a replacement. Alternatively the debug circuitry 112 may adapt its configuration to accommodate changes in the function circuitry 100 106 or infrastructure circuitry 1 04.

When not used for conventional debug support purposes the debug reconfigurable resources can be configured for system condition monitoring.

In the examples above, debug circuitry is reconfigurable in response to the configuration of circuitry being tested/monitored. However, the invention can be applied to other situations in which the configuration of one circuit can vary based on the configuration of another. Thus, in more general terms, the invention provides an integrated circuit assembly, comprising first circuitry and second circuitry for communication with the first circuitry. The first circuitry is configurable between a plurality of configurations, and the second circuitry comprises a plurality of circuit elements, each communicating with portions or signals of the first circuitry.

A controller then controls the configuration of the plurality of circuit elements, such that the plurality of circuit elements is configurable into a plurality of different configurations in which different circuit elements communicate with different portions or signals of the first circuitry in dependence on the configuration of the first circuitry.

This arrangement can be used to configure debug resources in an efficient manner, but it can also configure other secondary circuit functions so as to interact more efficiently with a primary circuit. Examples include: a primary circuit which provides processing and a secondary circuit which provides increased memory performance or capacity (i.e. a cache, prefetching circuitry or compression circuitry); a primary circuit which provides processing and a secondary circuit which provides communication infrastructure to other function circuits such as memory and peripherals; a primary circuit which provides signal conditioning and a secondary circuit which provides processing or signal conversion.

The function circuitry which is monitored by the debug arrangement typically comprises digital circuits, but may contain analogue circuits or parts. The debug support assists in development of software, hardware or both software and hardware. The function circuitry can be any circuits having functionality which can be subjected requiring testing or monitoring, such as memory, processing, 110 interface circuits, internal interface circuits (including busses and similar), internal or external device drivers, etc. As will be apparent to those skilled in the art, a debug operation typically comprises monitoring, observation, calibration and dynamic testing of a system.

Various modifications will be apparent to those skilled in the art. - 12-

Claims

CLAiMS 1. An integrated circuit assembly, comprising: first function

circuitry (100,106); and debug circuitry (112) for monitonng and testing of the first function circuitry, wherein the debug circuitry comprises: detection circuitry (120,122) for monitoring signals of the first function circuitry; and a controller (123) for controlling the configuration of the detection circuitry (120,122), such that the detection circuitry is configurable into a plurality of different configurations in which different detection circuitry resources are allocated to the detection of different signals of the first function circuitry.
2. An assembly as claimed in claim 1, wherein the detection circuitry comprises: a first plurality of detection circuits (120); and a second plurality of detection circuits (122).
3. An assembly as claimed in claim 2, wherein each one of the first plurality of detection circuits (120) is associated with a predetermined resource of the first function circuitry, and wherein each one of the second plurality of detection circuits (122) is configurable to be associated with a selected one of a plurality of the predetermined resources of the first function circuitry.
4. An assembly as claimed in any preceding claim, wherein the configuration of the detection circuitry is variable based on configuration information of the first function circuitry (100,106).
5. An assembly as claimed in any preceding claim, wherein the first function circuitry comprises one or more of processor circuits, interface circuits, memory circuits.

- 13 -
6. An assembly as claimed in any preceding claim, wherein the debug circuitry further comprises a switching unit (121) for switching between configurations of the detection circuitry under the control of the controller (123).
7. Au assembly as claimed in any preceding claim, wherein detection circuitry is configurable between a first configuration in which a first set of signals the first function circuitry are monitored and a second configuration in which one or more of the first set of signals the first function circuitry are not monitored.
8. An assembly as claimed in any preceding claim, further comprising test circuitry (128) communicating with the controller (123) for testing of the debug and/or function circuitry (100,106).

9. An assembly as claimed in any claim 8, wherein the test circuitry (128) is for testing of the debug circuitry, and wherein the configuration of the detection circuitry is variable by the controller in response to the test results..
9. An assembly as claimed in any claim 8 or 9, wherein the test circuitry (128) is for testing of the function circuitry, and wherein the configuration of the function circuitry is variable by the controller in response to the test results.
10. An assembly as claimed in any preceding claim, further comprising a debug trace interface (103) for communication with an external development tool.
11. An assembly as claimed in claim 10, further comprising trace transfer circuits for providing data to the debug trace interface (103).
12. A system as claimed in any preceding claim, wherein a state interface is provided for communication of state information concerning the first function circuitry (100,106) to the debug circuitry (112). - 14-
13. A system as claimed in claim 12, wherein the controller controls the configuration of the detection circuitry based on the state information.
14. A system as claimed in claim 13, wherein the control of the configuration of the detection circuitry based on the state information is overridable based on external inputs to the debug circuitry.
15. An assembly as claimed in any preceding claim, wherein the configuration of the detection circuitry is changed automatically by the controller in response to a change in the configuration of the first function circuitry.
16. An integrated circuit assembly, comprising: first circuitry (100,106); and second circuitry (112) for communication with the first circuitry, wherein the first circuitry is configurable between a plurality of configurations, and wherein the second circuitry comprises: a plurality of circuit elements, each communicating with portions or signals of the first circuitry; a controller (123) for controlling the configuration of the plurality of circuit elements (120,122), such that the plurality of circuit elements is configurable into a plurality of different configurations in which different circuit elements communicate with different portions or signals of the first circuitry in dependence on the configuration of the first circuitry.
1 7. An assembly as claimed in claim 16, wherein the second circuitry comprises circuitry for monitoring or testing the first circuitry.
18. A method of performing a debug operation within an integrated circuit assembly, for debugging of first function circuitry (100,106), wherein the method coniprises: controlling the configuration of detection circuitry (120,122) forming part of the integrated circuit assembly in dependence on the configuration of the first function circuitry, - 15 - wherein different detection circuitry resources are allocated to the detection of different signals of the first function circuitry in the different configurations; using the detection circuitry to monitor signals of the first function circuitry; and providing the monitored signals to an external development tool.