JPH10186001A - Method and device for calculating electric power consumption of electronic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To calculate the electric power consumption value close to actual operation in an electronic circuit such as LSI. SOLUTION: With respect to all logical elements usable in an intended LSI, all possible states, considering the operation within the logic elements, are determined on the basis of the combination of signal values of input and output signals, and power consumption in the respective state transitions is preliminarily calculated by circuit simulation, and stored in a design data base DB 710. The power consumption in non-operation and the electric power consumption such as change of output signal are similarly calculated by circuit simulation, and stored in the design DB 710. A power consumption calculating part 721 calculates the electric power consumption of all the logic elements of the intended LSI to all state transitions causing power consumption. A load capacity calculating part 722 calculates the load capacity of the logic elements, and reflects it to the calculation of electric power consumption such as output change.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method and an apparatus for calculating power consumption of an electronic circuit, and is used for designing a CMOS LSI or other semiconductor integrated circuits.
The present invention relates to a technique for performing power consumption estimation and power consumption calculation close to the time of actual operation.

[0002]

2. Description of the Related Art Physically, for example, a CMOS LSI
The average power consumption is the power consumption due to the through current that flows steadily irrespective of the state transition of the circuit, and the power consumption due to the current due to the charging and discharging of the MOS capacitor that occurs transiently immediately after the switching of the signal potential. The sum can be calculated by time averaging. Therefore, conventionally, when a semiconductor integrated circuit is designed based on design data, the power consumption due to the through current of each circuit and the power consumption of the circuit itself when the output signal of the circuit is switched once by circuit simulation,
A method has been adopted in which the power consumption generated for driving the load when a unit capacity is assumed as a load is calculated, and the power consumption is calculated based on this value.

[0003]

In the above prior art, the number of state transitions of the circuit is the same as the number of times of switching of the output signal of the circuit. Inverter, NAND,
In a basic circuit such as a NOR circuit, the number of times of switching of the output signal matches the number of times of operation of the circuit. Therefore, power consumption can be calculated by using the number of times of switching of the output signal. However, inverter, NAN
In a composite cell made by combining D, NOR, and the like, the first-stage circuit operates by switching of the input signal, but the output signal may not change. Does not reflect the number of switching. In a flip-flop, the data signal and the clock signal are independent as events, and if the clock signal is switched without switching the data signal,
Since the circuit that operates depending on the clock signal such as the clock enable is operating, there is a problem that the number of switching of the output signal of the data system alone does not reflect the number of operation of the circuit. It is impossible to calculate well.

An object of the present invention is to enable accurate calculation of power consumption in an electronic circuit such as a semiconductor integrated circuit even when the number of times of operation of the circuit cannot be counted from only the number of times of switching of output signals. It is another object of the present invention to provide a power consumption calculation method and apparatus capable of obtaining a value closer to the power consumption value during actual operation.

[0005]

The function of each logic element (cell) constituting an electronic circuit is defined by an output signal value corresponding to a combination of signal values of an input signal, and an operation state of the logic element is determined by an input signal. All can be specified by a combination of the signal value of the output signal. Therefore, according to the present invention, for each type of logic element constituting the electronic circuit, among the states defined by the combination of the input signal and the output signal of the logic element,
With respect to all state transitions that cause power consumption due to state transitions, the power consumption Enc that occurs every time a state transition occurs is obtained by circuit simulation and defined as a library. Similarly, the circuit simulation shows that the power consumption Er caused by the through current with respect to the logic element regardless of the input / output signal, the power consumption Eon generated regardless of the size of the load when the output signal is switched,
And the power consumption ΔEn generated when the output terminal is assumed to be a unit capacitance, is defined as a library. On the other hand, the transition probability γ for each state transition and the transition probability γo at which the output net is switched are defined in advance as a library for each logic element by statistics or the like.

From the above Er, Enc, Eon, ΔEn, γ, γo, the power consumption of the target electronic circuit is

[0007]

(Equation 3)

[0008] Here, assuming that the operating frequency of the electronic circuit is f, Nc = γ · f and Nn = γo · f.

The load capacitance CL of each logic element is determined based on the design data of the electronic circuit.

[0010]

(Equation 4)

Is calculated by Here, Cw means the total capacitance of the wiring portion connected to the output terminal of the logic element, and ΔCin means the total input capacitance of the subsequent logic element connected to the wiring.

In the present invention, in order to increase the accuracy of the power consumption calculation for the flip-flop, Er, Enc, Eon, ΔE
n, γ, γo, etc. are separately defined in the library for the data signal system and the clock signal system. The power consumption of the flip-flop is calculated by separately treating the events of the data signal system and the event of the clock signal system.

In the present invention, the transition of the operation state of each logic element constituting an electronic circuit such as an LSI is defined based on a combination of an input signal and an output signal. Does not switch,
Power consumption generated when only the input signal is switched can also be added. For flip-flops, the clock signal and data signal state transitions are treated separately, and the power consumption of the clock signal state transition and the data signal state transition are separately calculated and added. Is not switched, the power consumption caused by the switching of the clock signal can be added without omission.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings.

First, the calculation of power consumption for one logic element will be described with reference to FIG. 1 using logic elements (cells) having four states 101 to 104 as an example. The state transition in the logic element of FIG.
There is a street. Among these, regarding the four state transitions indicated by 117 to 120, the state of the circuit does not change even if the state transition occurs, so that there is no power consumption accompanying the state transition. On the other hand, the 12 state transitions denoted by reference numerals 105 to 116 involve a change in the state of the circuit, so that power consumption occurs. Therefore, for 12 state transitions of 105 to 116, the power consumption Enc generated each time one state transition occurs is obtained in advance by circuit simulation. Regarding circuit simulation, for example, Masayoshi Esashi, “Basics of Semiconductor Integrated Circuit Design” (Baifukan) 16
This is described in detail on pages 4-185. In addition, the logic element has power consumption due to a through current during non-operation, power consumption that occurs regardless of the size of a load when an output signal is switched,
In addition, there is power consumption due to charging and discharging of a MOS capacitor or the like which occurs transiently immediately after the switching of the potential of the output signal. Therefore, similarly, by circuit simulation, the power consumption Er due to the through current flowing constantly irrespective of the state transition of the logic element, the power consumption Eon generated every time the state transition of the output signal occurs once, and the unit of output terminal The power consumption ΔEn per operation when a capacity is assumed as a load is obtained in advance.
Further, for example, statistically, a transition probability γ at which 12 kinds of state transitions of 105 to 116 of the logic element occur and a transition probability γo of the output signal are obtained.

On the other hand, a table as shown in FIG. 2 is prepared for the logic element of FIG. 1, and the above-mentioned Er, Enc, Eon, Δ
En, γ, and γo are defined as libraries. In FIG. 2, Er, Eon, ΔEn, and γo have the same value for each state transition, but Enc and γ have different values for each state transition.

The power consumption Pd for the logic element of FIG.
In equation (1), assuming N = 1,

[0018]

(Equation 5)

Is calculated by Here, Nc = γ ×
f, Nn = γo × f (f is the operating frequency of the circuit). Further, CL is calculated from design data such as an LSI using Expression (2). This will be described later.

Next, a state defined by a combination of input / output signals will be described using the logic element shown in FIG. 3 as an example.
The logic element 300 shown in FIG.
Input signals IN1, IN2, IN3, IN4 and 305
Has one output signal OUT. The circuit is composed of three basic circuits 306 to 308. The signal value of the output signal of 306 is A, and the signal value of the output signal of 307 is B. FIG. 4 shows IN1, IN2,
The combination of signal values that can be taken by IN3 and IN4 and A, B,
The signal value of OUT is shown as a truth table.

The state of the logic element 300 in FIG.
07, 308, ie, a combination of three circuit states,
It is determined by the combination of the signal values of A, B, and OUT. In this example, there are four states shown in FIG. I / O signal IN
The correspondence between the signal values of 1, IN2, IN3, IN4, and OUT and the four states is as shown in FIG. Here, in the state transition between the states 1 to 3, the output value OUT of the logic element 300 remains “0” or the circuits 306 to 307
Output values A and B change, so that power consumption occurs.
When the present invention is applied, the power consumption associated with all the state transitions between the states 1 to 3 can be calculated without exception.

FIG. 7 is a schematic block diagram of a system configuration for realizing the power consumption calculation method of the present invention. The design database 710 includes, in addition to the original design data of an electronic circuit such as an LSI, the logic elements Er, Enc, Eon, ΔEn, γ,
γo, Cwo, Cin, etc. (hereinafter, these are collectively referred to as library data). The power consumption processing device (CPU) 720 includes a power consumption calculation unit 721 and a load capacity calculation unit 722. The power consumption calculation unit 721 calculates the power consumption Pd of the electronic circuit to be designed based on the above equation (1). In the negative capacity calculator 722, the above equation (2) is used.
Is calculated based on the load capacitance CL of each logic element constituting the electronic circuit to be designed. The memory device 730 stores design data and library data read from the design database 710, and intermediate results of calculations in the power consumption calculation unit 721 and the load capacity calculation unit 722.

FIGS. 8 to 10 show the design database 710.
2 shows a detailed configuration of the content. FIG. 8 shows original design data of an electronic circuit such as an LSI, which generally includes logical diagram information of an electronic circuit to be designed shown in (A) and wiring information shown in (B). FIG. 9 shows E related to the logic element of the library data.
This is a table group that holds r, Enc, Eon, ΔEn, γ, γo, and Cin, and has the table for each type (logical type) of a logic element constituting an electronic circuit. Here, these tables will be referred to as library data tables. Note that the transition probabilities γ and γo are held for each logic element included in the type of the logic element, and each can be identified by the element name. FIG. 10 shows Cwo of library data, which is provided for each wiring layer.

Next, the procedure of an embodiment of a power consumption calculating method according to the present invention will be described with reference to FIG. In FIG. 11, only the steps are the processing of the load capacity calculation unit 722, and the further steps are the processing of the power consumption calculation unit 721.

First, as preparation for the power consumption calculator 721 and load capacity calculation, the design data, operating frequency f, and library data of the target electronic circuit are read from the design database 710 into the memory device 730 (step 110).
1). Then, the power consumption Pd0 of the electronic circuit is cleared (step 1102).

Next, the first logic element (i = 1) is selected based on the logic diagram information of the design data (step 1103), and a library data table corresponding to the type of the logic element is selected (step 1103). 110
4). Here, the power consumption associated with the state transition defined by the combination of the input and output signals of the logic element is P ₀ , and the power consumption associated with the state transition of the output signal is P ₁ . That is, P ₀ = Σ (E
nc × Nc), P ₁ = (Eon + ΔEn × CL) × Nn.
As initial settings, P ₀ and P ₁ are cleared (step 1105).

[0027] step 1106 to 1110 is a processing procedure for calculating the P _0. First, the first state transition (j = 1) corresponding to the logic element is selected from the library data table selected in step 1104 (step 110).
6), the power consumption Enc and the transition probability γ of the state transition are obtained (step 1107). Next, the number of transitions Nc of the state transition is obtained by Nc = γ × f (step 1108),
To calculate the P ₀ + Enc × Nc (the initial value of P ₀ is 0), and updates the P ₀ (step 1109). Thereafter, it is determined whether there is another state transition (step 1110), and if so, the processing of steps 1106 to 1109 is repeated. In this way, the power consumption P ₀ associated with all possible state transitions of the logic element is calculated.

[0028] Step 1111 to 1,116 is a processing procedure for calculating a P _1. If it is determined in step 1110 that there is no other state transition of the logic element, first, in step 1111, the load capacitance CL connected to the output terminal of the logic element is calculated. The load capacity CL is obtained by the above equation (2), and FIG. 12 is a diagram for explaining this.
That is, assuming that the total capacitance of the wiring portion connected to the output terminal of the logic element 1200 is Cw, this forms a net on the output side of the logic element 1200 for each wiring layer based on the wiring information of the design data. The length can be obtained by calculating the length of each line segment (this is referred to as a segment length) and multiplying this by the unit capacity Cwo. Logic element 12 in FIG.
The 00 load capacity CL is obtained by adding the sum of Cw and Cin. Note that Cin is the input capacitance of the subsequent element of the logic element 1200, and can be easily obtained by searching the table shown in FIG. 9 from the type of the logic element in the logic diagram information of FIG. Also, Cwo can be obtained by searching FIG. 10 based on the wiring layer of the wiring path of the wiring information in FIG. 8B.

Returning to FIG.
From the library data table selected in step 04, the power values Eon, ΔEn, and output transition probability γo due to the load drive of the logic element are obtained (step 1112). Then, the number Nn of output transitions of the logic element is obtained by Nn = γo × f (step 1113), and (Eon + ΔEn × CL) ×
And P ₁ calculates the nn (step 1114).

Next, the power consumption Er due to the through current of the logic element is obtained from the library data table selected in step 1104 (step 1115).
_{d + Er + P 0 + P} 1 is calculated (initial value of Pd is 0), and updates the Pd (step 1116). Here, Er + P ₀ + P
₁ is the power consumption for the logic element.

Thereafter, it is determined whether there is a next logic element, and if so, the processing procedure of steps 1103 to 1116 is repeated. Step 11 is performed for all the logic elements described in the logic diagram information of the design data read in step 1101.
By repeating steps 03 to 1116, the power consumption Pd of the entire target electronic circuit can be calculated.

Next, as another embodiment of the present invention, a case where the logic element is a flip-flop will be described. FIG.
Shows an example of a flip-flop. 1301 is a data input signal, 1304 is a data output signal, 1302 is a clock signal, and 1303 is a clock enable. FIG. 13 schematically shows the configuration of a flip-flop separated into a data system and a clock system. As the circuit components, a clock system circuit shown by 1305 and a data system circuit shown by 1306 are used. is there. In the present invention, library data is prepared for each of the separated circuits 1305 and 1306, and each state transition and the power consumption generated at that time are separately calculated and added. As a result, even if the data signal is not switched, the power consumption caused by the switching of the clock signal can be calculated without omission.

Next, as another embodiment of the present invention, FIG.
An example of calculating the number of state transitions from the result of the logic simulation will be described with reference to FIGS. FIG. 14 illustrates a target logic element 1401, input signals 1402 to 1405, and an output signal 1406. Here, the logic element 140
1 is assumed to be the same as that of FIG. 3, the truth table is shown in FIG. 4, and the relationship between input / output signals and states is as shown in FIG.

FIG. 15 shows a result of the logic simulation. In FIG. 15, the horizontal axis indicates the passage of time, and changes in signal values of the respective signals are indicated by 1501 to 1505. Also,
The four possible states of the logic element are represented by 1506 to 1509.
Indicated by When the state transition in the logic simulation result is obtained from the signal values of 1501 to 1505 and FIG.
Nine state transitions 1510 to 1518 occur during a simulation time of 0 second to 2 seconds of the simulation result. For example, 1510 indicates that a transition has been made from state 1 to state 2. When the breakdown of the nine state transitions is counted by focusing on the state before the transition and the state after the transition, the number of state transitions is as shown by 1601 in FIG. Now, assuming that the simulation time is 2 seconds for simplicity, the number of transitions per second can be calculated by time averaging, and is as shown in a column 1602 in FIG.
Accordingly, the number of state transitions is as shown in the column 1602, and the number of logic element operations is 4.5.

As described above, the number of transitions and the number of operation of the logic element can be calculated from the result of the logic simulation. In this way, by counting the number of state transitions for each combination of the input result and the output result from the logic simulation result with respect to the simulation result when executing a certain benchmark program, each circuit can be executed when the actual benchmark program is executed. Can be calculated, and the power consumption can be calculated closer to the actual operation.

[0036]

As described above, according to the present invention, a CMOS LSI
In electronic circuits such as electronic circuits, state transitions are defined based on the combination of input and output signals, and the power consumption that occurs when only the input signal is switched without adding the output signal generated by the composite gate is added. Accordingly, it is possible to provide an estimated power consumption value or a calculated power consumption value closer to the measured power consumption value in the actual operation. As a result, more effective numerical values can be provided for the power supply design inside the LSI, the design of the LSI cooling system, the power supply design of the printed circuit board, and the like.

In the flip-flop, the state transition of the clock signal and the state transition of the data signal are treated separately, and the state transition of the clock signal and the state transition of the data signal are separately calculated and added, so that the data signal is not switched. Even if
Power consumption caused by switching of the clock signal can be added without omission.

[Brief description of the drawings]

FIG. 1 is a state transition diagram of a logic element.

FIG. 2 is a diagram illustrating definitions of power consumption and a state probability with respect to a state transition according to the present invention.

FIG. 3 is an example of a circuit diagram of a logic element.

FIG. 4 is an example of a truth table of a logic element.

FIG. 5 is a diagram illustrating an example of correspondence between states and input / output signals.

FIG. 6 is a diagram showing the relationship between input / output signals and states.

FIG. 7 is a schematic block diagram of a system configuration of the present invention.

FIG. 8 is a diagram showing a specific example of design data.

FIG. 9 is a diagram showing a specific example of a library data table.

FIG. 10 is a diagram illustrating a specific example of a capacitance table of a wiring layer;

FIG. 11 is a diagram showing an embodiment of a processing procedure of a power consumption calculating method according to the present invention.

FIG. 12 illustrates an example of a load capacitance of a logic element.

FIG. 13 illustrates an example of a flip-flop.

FIG. 14 is a diagram illustrating an example of a logic element for calculating the number of state transitions.

FIG. 15 is a diagram illustrating an example of a logic simulation result and a state transition.

FIG. 16 is a diagram illustrating an example of the number of state transitions.

[Explanation of symbols]

 710 Design database 720 Power consumption processing unit 721 Power consumption calculation unit 722 Load capacity calculation unit 730 Memory device

Claims (3)

[Claims] 1. A method for calculating power consumption of an electronic circuit composed of a plurality of logic elements, comprising the steps of: Among the state transitions determined by the combination of the power Er and the input / output signal of the logic element, the power consumption Enc at each state transition in which power consumption occurs, and the state transition of the output signal of the logic element regardless of the size of the load. The power consumption Eon generated and the power consumption ΔEn generated when a unit capacitance is assumed as a load for the output terminal of the logic element are defined, and the power consumption Pd of the electronic circuit is defined as A method for calculating power consumption of an electronic circuit, characterized by calculating 2. The method according to claim 1, wherein Er, Erc, Eon, ΔEn, Nc, Nn, and CL of the logic element of the flip-flop are used for the data signal system and the clock signal system. A power consumption calculation method for an electronic circuit, wherein the power consumption of a data signal system and the power consumption of a clock signal system are separately defined and calculated. 3. An apparatus for calculating power consumption of an electronic circuit composed of a plurality of logic elements, comprising: means for holding design data of the electronic circuit; Power consumption Er due to a through current that constantly flows through the logic element, power consumption Enc at each state transition in which power consumption occurs among state transitions determined by a combination of input / output signals of the logic element, output signal of the logic element Means for holding each value of power consumption Eon generated irrespective of the size of the load at the time of the state transition and power consumption ΔEn generated when a unit capacitance is assumed as a load for the output terminal of the logic element; Means for calculating the load capacitance CL of each logic element constituting the electronic circuit based on the design data of the electronic circuit; Means for calculating power consumption of an electronic circuit.