JPH0816634A - Method/device for calculating delay time - Google Patents

Abstract

PURPOSE:To provide a delay time calculation method which can shorten the computer processing time needed for the delay analysis where the wiring resistance is taken into consideration. CONSTITUTION:A 1st delay time Tc where the output resistance of a primitive element is taken into consideration is calculated by a delay calculation expression which applies the output resistance Ron of the primitive element, the wiring parasitic capacities C1-C3 and the input capacities Cin1 and Cin2 of the primitive element of the next stage. Then a 2nd delay time TL where the wiring resistance is taken into consideration is calculated by the analysis of a circuit network which is equalized by an RC delay circuit network including the wiring resistances R1-R3, the capacities C1-C3 and the capacities Cin1 and Cin2. Then both delay times Tc and TL are added together so that the delay time is known between the primitive elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for calculating a signal propagation delay time between logic elements required in a logic simulation of a semiconductor integrated circuit and an arithmetic unit therefor, for example, for a MOS type semiconductor integrated circuit. The technology is effective when applied to a logic simulator.

[0002]

2. Description of the Related Art For the signal propagation delay time Tpd between elements (hereinafter also simply referred to as primitive elements) in a logic simulation of a semiconductor integrated circuit, when the influence of the wiring resistance is not taken into consideration, for example, the following expression Tpd = Tcell + a × It can be calculated by Ron × Cload. Here, Tcell is a delay time of the primitive element itself (delay time until a change in the input of the primitive element appears in the output), a is a proportional constant, and Ron is an output resistance of the primitive element (for example, an output MOS included in the primitive element). Cload is the wiring capacitance (capacitance component parasitic on the wiring from the output terminal of the previous stage primitive element to the input terminal of the next stage primitive element) and the input capacitance of the next stage primitive element (input circuit). Is the sum of the gate capacitances of the input MOS transistors that form

However, due to the recent miniaturization of semiconductor elements, the wiring resistance has increased as compared with the output resistance of the primitive element, so that the wiring resistance cannot be ignored in calculating the delay time. Therefore, in order to accurately calculate the delay time between primitive elements, an RC approximation circuit that considers the wiring resistance together with the output resistance of the primitive element and the parasitic capacitance component in the wiring path between the primitive elements of interest should be analyzed. The accurate delay time can be calculated with. For example, assume an RC approximation circuit as shown in FIG. In FIG. 4, R1 is the wiring resistance of the path L1, C1 is the parasitic capacitance of the path L1, R2 is the wiring resistance of the path L2, C2 is the parasitic capacitance of the path L2, and R3.
Is the wiring resistance of the path L3, C3 is the parasitic capacitance of the path L3, C
In1 is representative of each component of the input capacitance of the primitive element coupled to the path L2, and Cin2 is representative of each component of the input capacitance of the primitive element coupled to the path L3. A π-type one-stage RC approximation circuit is adopted for approximation of the distributed constant path in the figure.

[0004]

However, the circuit analysis itself takes a lot of computer processing time, and the output resistance of the primitive element is output by the combination of the logical values of the input signals given to the input terminals of the primitive element. Since the resistance value is set to a plurality of values, if the circuit network analysis of the RC approximation circuit is performed for all the output resistance values of a plurality of types of primitive elements, an enormous amount of computer processing time is required. Revealed by For example, when the primitive element is the three-input type composite gate circuit shown in FIG. 5, the value of the output resistance Ron is such that the MOS transistors A and B are in the ON state according to the combination of the logical values of the input terminals I1 to I3. , MOS transistor C is on, MOS transistors A, B, C are on, M
The OS transistors D and F are turned on, the MOS transistors E and F are turned on, and the MOS transistors D, E, and F are turned on. These 6 types of output resistance R
Each of the on values must be used to perform a special operation for network analysis. The composite gate circuit shown in FIG. 5 has the composite logic of the 2-input OR gate and the 2-input NAND gate shown in (B) thereof, and can be constituted by the MOS circuit of (A), and the truth table is shown in (C). Part of is shown.

Japanese Patent Laid-Open No. 2-239373 is an example of a document describing a technique for reducing the computer processing time required for calculating the wiring delay.

An object of the present invention is to provide a delay time calculation method for delay time analysis which can shorten the computer processing time for delay analysis considering wiring resistance and can efficiently perform delay analysis. It is in.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the delay time calculation method of the present invention is
The delay calculation is performed by separating the delay time between the primitive elements into a first delay time considering the output resistance of the primitive element and a second delay time considering the wiring resistance. More specifically, the resistance component (output resistance) inside the element connected to the output terminal of the primitive element of interest and the capacitance component outside the element connected to the output terminal of the primitive element (of the wiring connecting between the primitive elements). The first delay time (Tc) is calculated from the parasitic capacitance and the input capacitance of the next-stage primitive element), and the resistance component (wiring resistance) and capacitance component (wiring resistance) outside the element connected to the output terminal of the primitive element of interest are calculated. The second delay time (TL) is calculated from the parasitic capacitance of the wiring connecting the primitive elements and the input capacitance of the next-stage primitive element. The delay time between the primitive elements is calculated by adding the two delay times (Tc, TL). Here, the primitive element is a logic element or a logic module whose output resistance is different depending on a difference in input state, such as a logic gate such as NAND or NOR, a composite gate of logic gates, a logic unit such as a flip-flop or a counter, and Macro module (macro cell) such as central processing unit and memory
Can be

The calculation of the second delay time (TL) can be performed by a network analysis equivalent to an RC delay network using the resistance component and the capacitance component. In addition, in the calculation of the first delay time and the calculation of the second delay time, weighting is applied to one or a plurality of items selected from mutually different temperature dependence, power supply voltage dependence, and manufacturing variation degree. You can do it.

[0011]

According to the above-mentioned means, since the wiring resistance is not considered in the calculation of the first delay time in consideration of the output resistance of the primitive element, the first delay time is different for each input signal of the primitive element. It is calculated by the delay calculation formula for each output resistance value. Since the wiring resistance is taken into consideration in the calculation of the second delay time, the second delay time is R
It is acquired by circuit network analysis using the C approximation circuit. At this time, it is not necessary to consider the output resistance of the primitive element. Therefore, it is not necessary to individually perform the entire network analysis many times using different output resistance values for each input signal of the primitive element. That is, even when the output resistance value of the primitive element is changed in many ways, the circuit network analysis for calculating the delay time in consideration of the wiring resistance needs to be performed only once. This significantly shortens the computer processing time for calculating the delay time when delay analysis is performed in consideration of wiring resistance.

[0012]

FIG. 2 shows an example of a logical model to which an embodiment of the delay time calculation method according to the present invention is applied. In FIG. 5, reference numeral 1 denotes a primitive element whose output resistance value differs depending on a combination of a plurality of input logical values, and for example, FIG.
The composite logic gate shown in FIG. Reference numerals 2 and 3 are appropriate primitive elements that receive the output of the primitive element 1 as an input. An RC distributed constant path can be represented between the primitive elements 1, 2, and 3. In the figure, R1 is the wiring resistance of the path L1, C1 is the parasitic capacitance of the path L1, and R2 is
Is the wiring resistance of the path L2, C2 is the parasitic capacitance of the path L2, R
3 is the wiring resistance of the path L3, C3 is the parasitic capacitance of the path L3,
Each of the components is typically shown. The resistance component and the capacitance component are obtained by the component per unit length and the wiring length obtained from the layout information. In the logic simulation for the circuit including the logic model as shown in FIG. 1, the change in the output of the primitive element 1 in response to the change in the input of the primitive element 1 changes the input of the primitive element 2 in the next stage. When the delay time Tpd before being given to the T.sub.d is required, the delay time is given by: Tpd = Tcell + Tnet. Tcell is primitive element 1
It is the delay time of itself (the delay time until a change in the input of the primitive element appears in the output), which can be uniquely determined from the circuit configuration. The calculation method targeted by the present invention is to reduce the computer processing time for obtaining the delay time Tnet considering the wiring resistance.

The operation method will be briefly described below.
The delay time generated by the output resistance of the primitive element 1, the wiring resistance and its parasitic capacitance, and the input capacitance of the next-stage primitive element 2 (3) is taken into consideration in the output resistance of the primitive element 1 (ignoring the wiring resistance). The delay time Tc and the second delay time TL in which the wiring resistance is taken into consideration (ignoring the output resistance of the primitive element) are separated and the respective delays are calculated.

FIG. 1 shows a delay time calculating method according to an embodiment of the present invention corresponding to FIG. In the figure, Tnet (a) is the delay time for the paths L1 and L2, and Tnet (b) is the delay time for the paths L1 and L3.

The first delay time Tc considering the output resistance of the primitive element 1 is calculated based on the following equation: Tc = a × Ron × Cload. Where a is a proportional constant, Ron
Is an output resistance formed by the on-resistance of the output MOS transistor constituting the primitive element 1, Cloa
d is the total capacitance value of the parasitic capacitance of the wiring coupled to the output terminal of the primitive element 1, the input terminal capacitances Cin1 and Cin2 of the next-stage primitive elements 2 and 3. In the above delay calculation formula, since the output resistance of the value of Ron changes according to the input state as shown in FIG. 5, for example, the first delay time Tc is set for all output resistances (or maximum and minimum output resistances). Also in the calculation, since the wiring resistance equivalent to the RC delay network is not taken into consideration, the computer processing time is remarkably short as compared with the network analysis.

Second delay time TL considering wiring resistance
Is calculated by performing an equivalent circuit analysis using an RC delay network using the parasitic capacitance of the target wiring and the input capacitances Cin1 and Cin2 of the next-stage primitive element. A publicly-known method can be appropriately adopted as such a circuit analysis method, and therefore a detailed analysis method will not be described. Such circuit analysis requires complicated operations such as matrix operation, and thus much more computer processing time is spent than the operation of the first delay time Tc.
However, since the output resistance of the primitive element is not taken into consideration, such a circuit network analysis which requires a long time for the arithmetic processing can be performed only once. The second delay time T obtained by this circuit network analysis
L is a unique value according to the wiring length of each wiring path. That is, according to FIG. 1, TL (a),
Obtained as TL (b).

By separately calculating the first delay time Tc considering the output resistance of the primitive element and the second delay time TL considering the wiring resistance, the temperatures of the primitive element and the wiring are different from each other. It becomes possible to consider the dependency, the power supply voltage dependency, and the manufacturing variation. For example, the temperature coefficient of resistance of the semiconductor in the MOS transistor forming the primitive element is different from the temperature coefficient of resistance of the metal forming the wiring, and the difference can be reflected individually.

For example, the first delay time Tc considering the output resistance of the primitive element and the second delay time TL considering the wiring resistance are given by the following equation: Tc = a × Ron × Cload × Ptemp × Pvcc
× Pprocess TL = TL * × Qtemp × Qvcc × Qproces
It can be calculated using s. Here, Ptemp is a temperature dependence coefficient of Tc, Pvcc is a power supply voltage dependence coefficient of Tc, Pprocess is a manufacturing variation of Tc, TL * is TL under a reference condition, Qtemp is a temperature dependence coefficient of TL,
Qvcc is the power supply voltage dependence coefficient of TL, Qprocess
Represents the manufacturing variation of TL. It goes without saying that the delay time Tcell of the primitive element itself can also be calculated in consideration of its own temperature dependence, power supply voltage dependence, and manufacturing variations.

By the above calculation method, the delay time Tpd (a) for the paths L1 and L3 and the delay time Tpd (b) for the paths L1 and L2 are calculated by the following equation: Tpd (a) = Tcell + Tnet (a) = Tcell + T
c + TL (a) Tpd (b) = Tcell + Tnet (b) = Tcell + T
It is obtained by c + TL (b). Here, Tnet represents a delay time between primitive elements, and is represented by the sum of the first delay time considering the output resistance of the primitive element and the second delay time considering the wiring resistance as described above.

FIG. 3 shows an example of the system configuration of a delay time calculation device for performing delay analysis using the above delay time calculation method. The delay time calculation device 10 includes a primitive element delay calculation unit 11, a wiring resistance delay calculation unit 12, and a total delay calculation unit 13, and the primitive element characteristic information 1
4, the function description information 15 and the layout information 16 are received and the required delay time is calculated. This delay time calculation device 1
0 is included in the logic simulator and is constituted by, for example, an engineering workstation including a predetermined operation program.

The function description information 15 includes information about a function description for specifying the function of the primitive element to be operated. For example, the input logic value and the output logic value of the composite gate circuit shown in FIG. Includes a truth table that describes relationships.

The primitive element characteristic information 14 is the delay time information Tce of the primitive element to be calculated.
11 and output resistance Ron. As the output resistance, for example, each output resistance Ron which is different depending on the combination of the logic values of the signals to be given to the input terminals I1 to I3 of FIG.

The layout information 16 includes a net list including wiring nets for defining the coupling relation between the target primitive elements, the length of each wiring constituting the wiring net, and the resistance component per unit length. And the value of the parasitic capacitance component and the input gate capacitance value of the next-stage primitive element. The method of defining the wiring resistance and the parasitic capacitance component is not limited to that, and the resistance and the capacitance component may be defined for each section that does not include the branch.

The primitive element delay calculation unit 11 calculates the delay time Tc in consideration of the output resistance of the primitive element to be calculated, based on the primitive element characteristic information 14 and the function description information 15, according to the above-described arithmetic expression.
The delay time Tc is calculated and acquired for each output resistance Ron that differs depending on the input state of the primitive element.
When the delay time Tcell of the primitive element itself is not acquired as the primitive characteristic information 14, the primitive element delay calculation unit 11 can calculate and acquire the delay time.

The wiring resistance delay calculation unit 16 calculates the delay time TL considering the wiring resistance based on the layout information 16 by the above-mentioned circuit network analysis. Since the delay time TL has nothing to do with the state of the input signal to the primitive element, in other words, the output resistance Ron of the primitive element is not used as a parameter for this calculation. Therefore, the network analysis is performed only once. It is sufficient to calculate the delay time TL due to the wiring resistance.

The total delay calculation unit 13 delays based on the delay time Tcell of the primitive element itself, the delay time Tc obtained by the primitive element delay calculation unit 11, and the delay time TL obtained by the wiring resistance delay calculation unit 16. Time Tp
Calculate d (a) and Tpd (b).

The delay time calculation method is applied to the simulation of the semiconductor integrated circuit shown in FIG. 6, for example. In FIG. 6, LSIa is a gate array type semiconductor integrated circuit, and LSIb is a standard cell base type semiconductor integrated circuit. Each semiconductor integrated circuit LSIa,
In the LSIb, 20 is a bonding pad area formed on the outer peripheral edge of the chip, and 21 is a buffer area for forming an input circuit, an output circuit, and an input / output circuit. In the case of the gate array type semiconductor integrated circuit LSIa, the entire central portion is a spread gate region 22 whose circuit configuration is determined according to user specifications. The spread gate region 22 is, for example, C including four P-channel type MOS transistors and four N-channel type MOS transistors.
A large number of MOS basic cells are arranged, and the connection to these transistors is determined according to user specifications to form a required circuit. A macro module such as a central processing unit (CPU) 23, a memory 24, and an analog circuit 25 is arranged in a central portion of a standard cell-based semiconductor integrated circuit LSIb according to user specifications, and a flip-flop or an arithmetic unit is partially provided. An area 26 is formed in which standard cells standardized at the level are arranged according to user specifications.

For example, the above-described delay time calculation method is applied to various wiring paths which are typically shown in a portion of the semiconductor integrated circuit LSIa where the spread gate region is enlarged. For example, it is applied to a path in which the non-inverter NIV1 is the primitive element of the previous stage and the NAND gate NAND is the primitive element of the next stage. Furthermore, NOR gate NOR1
It is also possible to apply the above-described delay time calculation method in units of the path from the output of the above to the one input of the NOR gate NOR2 via the flip-flop circuit DFF and the inverter IV1.

In the delay time calculation method described above, the wiring path 27 between the central processing unit 23 and the memory 24 (between macro cells) in the semiconductor integrated circuit LSIb and the central processing unit 2 are used.
It is also applicable to the wiring path 29 between the macro cell such as 3 and the standard cell such as the flip-flop 28 and the wiring path 31 between the standard cells such as the flip-flop 28 and the arithmetic unit 30. In particular, when a macro cell such as the central processing unit 23 is used as a primitive element, Ron is obtained from the circuit information of the macro cell library. As the delay time Tcell of the primitive element itself, the information used for the evaluation of the macro cell can be used.

According to the above embodiment, there are the following effects. (1) The delay between the primitive elements is calculated by separating the first delay time Tc considering the output resistance of the primitive element 1 and the second delay time TL considering the wiring resistance. Even when the output resistance Ron can take a plurality of ways according to the combination state of the input signals, the circuit analysis equivalent to the RC delay network is performed only once when the second delay time TL is obtained, and between the primitive elements is analyzed. The delay time can be obtained, and the computer processing time for obtaining the overall delay time Tnet between the elements in consideration of the wiring resistance can be significantly shortened. For example, in the case of the path coupled to the output of the primitive element 1 of FIG. 5, assuming that the output resistance Ron of the primitive element 1 is changed in six ways according to the combination of the input signals, the circuit for each of them is changed. Compared with the conventional method of network analysis, the method of this embodiment requires a computer processing time of about 1/6.

(2) It is possible to efficiently implement a logic simulation considering the delay time of each wiring path.

(3) By separating the delay time between the primitive elements into the first delay time considering the output resistance of the primitive element and the second delay time considering the wiring resistance,
It is possible to obtain the delay time by making the primitive element and the wiring have different temperature dependence, power supply voltage dependence, and manufacturing variation from each other. Also in this respect, the reliability of the logic simulation can be improved.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, the delay calculation formula of the primitive element delay calculation section 11 is not limited to the delay calculation formula described in the present specification, and the calculation does not consider the wiring resistance and also considers the output resistance of the primitive element. Any expression is acceptable.
Further, the method of calculating the delay time of the wiring resistance delay calculation unit 12 is not limited to the calculation by the circuit network analysis, and the delay time is calculated without considering the output resistance of the primitive element and the wiring resistance. I wish I had it. Further, the number of branches of the wiring route is not limited to the case shown in FIG. 2 and can be set appropriately.

In the above description, the case where the invention made by the present inventor is mainly applied to the calculation of the delay time in the MOS type semiconductor integrated circuit in the logic simulator which is the field of use as the background has been described.
It can be widely applied to delay time calculation in various semiconductor integrated circuits of I-CMOS type and bipolar type. Further, the LSI or IC arranged on the mounting board can be applied to the calculation of the delay time for the delay analysis of the mutual wiring route.

[0036]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) The output of the primitive element is calculated by separating the first delay time considering the output resistance of the primitive element and the second delay time considering the wiring resistance and calculating the delay between the primitive elements. Even when a plurality of resistances can be taken according to the combination state of the input signals, when the second delay time is to be obtained, the circuit analysis equivalent to the RC delay network only needs to be performed once, and the primitive considering the wiring resistance. The computer processing time for acquiring the delay time between elements can be shortened significantly.

(2) It is possible to efficiently realize a logic simulation in consideration of delay time for each wiring path.

(3) By separating the delay time between the primitive elements into a delay time considering the output resistance of the primitive element and a delay time considering the wiring resistance, the temperature dependences of the primitive element and the wiring are different from each other. sex,
The delay time can be obtained with the power supply voltage dependency and the manufacturing variation. Also in this respect, the reliability of the logic simulation can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a delay time calculation method according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a logical model to which an embodiment of the delay time calculation method according to the present invention is applied.

FIG. 3 is a system configuration diagram of an embodiment of a delay time calculation device for performing delay analysis using the delay time calculation method represented by FIG.

FIG. 4 is a circuit in which primitive elements formed of MOS circuits are equivalent to each other by an RC delay network.

FIG. 5 is an explanatory diagram of an example of a primitive element having different output resistances depending on a combination state of logical values of input signals.

FIG. 6 is an explanatory diagram showing an example of a wiring path of a semiconductor integrated circuit to which a delay time calculation method can be applied.

[Explanation of symbols]

Ron Primitive element output resistance R1, R2, R3 Wiring resistance C1, C2, C3 Parasitic capacitance Cin, Cin2 Input capacitance of next-stage primitive element Tnet Delay time between primitive elements Tc First delay considering output resistance of primitive element Time TL Second delay time considering wiring resistance Cload Capacitance that collectively refers to parasitic capacitance and input capacitance of next-stage primitive element 1 Primitive element in the previous stage 2, 3 Primitive element in the next stage 10 Delay time arithmetic unit 11 Primitive element Delay calculation unit 12 wiring resistance delay calculation unit 13 total delay calculation unit A, B, C, D, E, F MOS transistors I1, I2, I3 input terminal of primitive element OUT output terminal of primitive element

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Takashi Nakajima 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division (72) Inventor Shuji Katayama 5 Kamimizumoto-cho, Kodaira-shi, Tokyo Chome 20-1 Semiconductor Company, Hitachi Ltd. Semiconductor Division (72) Inventor Hitoshi Sugihara 5-201-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Company, Ltd.

Claims (5)

[Claims] 1. A method for calculating a delay time between elements to be simulated, comprising: a resistance component inside the element connected to the output terminal of the element of interest and the outside of the element connected to the output terminal of the element. Calculating a first delay time from the capacitance component of the element, and calculating a second delay time from the resistance component and the capacitance component outside the element connected to the output terminal of the element of interest, Calculating a delay time between elements from the first delay time and the second delay time; and a delay time calculating method. 2. The resistance component outside the element connected to the output terminal of the element of interest is the wiring resistance of the wiring connected to the output terminal, and the capacitance outside the element connected to the output terminal of the element of interest. The components are the parasitic capacitance of the wiring and the input capacitance of the element whose input terminal is connected to the wiring. The calculation of the second delay time is equivalent to the RC delay circuit network using the resistance component and the capacitance component. The delay time calculation method according to claim 1, wherein the delay time calculation method is performed by circuit network analysis. 3. The calculation of the first delay time and the calculation of the second delay time include one or more items selected from mutually different temperature dependence, power supply voltage dependence, and manufacturing variation degree. 3. The delay time calculation method according to claim 1, wherein the delay time calculation is performed by weighting. 4. The delay time calculation method according to claim 1, wherein the primitive element is a logic element or a logic module whose output resistance is different depending on a difference in input state. 5. A delay time calculation device method for calculating a delay time between elements to be simulated, comprising: connecting a resistance component inside the element connected to an output terminal of the element of interest and an output terminal of the element. A first delay calculation unit that calculates a first delay time from a capacitance component outside the device, and a second delay from a resistance component and a capacitance component outside the device connected to the output terminal of the device of interest. It includes a second delay calculating section for calculating time, and a third delay calculating section for calculating a delay time between elements from the first delay time and the second delay time. A delay time calculation device characterized by the above.