CN113992193A - Circuit adjusting method, circuit adjusting device, electronic equipment, storage medium and circuit - Google Patents

Circuit adjusting method, circuit adjusting device, electronic equipment, storage medium and circuit Download PDF

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Publication number
CN113992193A
CN113992193A CN202111275866.XA CN202111275866A CN113992193A CN 113992193 A CN113992193 A CN 113992193A CN 202111275866 A CN202111275866 A CN 202111275866A CN 113992193 A CN113992193 A CN 113992193A
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circuit
data path
delay
path circuit
target
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梁新理
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Shanghai Power Tensors Intelligent Technology Co Ltd
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Shanghai Power Tensors Intelligent Technology Co Ltd
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Priority to CN202111275866.XA priority Critical patent/CN113992193A/en
Publication of CN113992193A publication Critical patent/CN113992193A/en
Priority to PCT/CN2022/120966 priority patent/WO2023071651A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay

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  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The present disclosure provides a circuit adjustment method, apparatus, electronic device, storage medium and circuit, the method comprising: determining a first data path circuit in the integrated circuit; wherein a target path exists between different registers in the first data path circuit; inserting a selected buffer into the first data path circuit based on device delay of an electronic component included in a target path in the first data path circuit to obtain a second data path circuit, wherein delay of each item marking path in the second data path circuit is consistent; performing component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; the first clock cycle corresponding to the third data path circuit is smaller than the second clock cycle corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit is different by an integral multiple of the first clock cycle.

Description

Circuit adjusting method, circuit adjusting device, electronic equipment, storage medium and circuit
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a circuit adjustment method, an apparatus, an electronic device, a storage medium, and a circuit.
Background
With the advance of technology, integrated circuits are rapidly developing. An integrated circuit refers to a circuit having a specific function, which is formed by integrating a certain number of commonly used electronic components, such as resistors, capacitors, transistors, etc., and connecting lines between these components, through a semiconductor process. A chip is a general name of a semiconductor device product, and is a carrier of an Integrated Circuit (IC), and is formed by dividing a wafer.
Along with the higher integration level and stronger calculation, the low power consumption design of the chip is more and more emphasized. Therefore, it is important to provide a circuit adjusting method for reducing the power consumption of the chip.
Disclosure of Invention
In view of the above, the present disclosure at least provides a circuit adjusting method, an apparatus, an electronic device, a storage medium and a circuit.
In a first aspect, the present disclosure provides a circuit adjustment method, including:
determining a first data path circuit in the integrated circuit; wherein a target path exists between different registers in the first data path circuit;
inserting a selected buffer into the first data path circuit based on device delay of an electronic component included in a target path in the first data path circuit to obtain a second data path circuit, wherein delay of each item marking path in the second data path circuit is consistent;
performing component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; the first clock cycle corresponding to the third data path circuit is smaller than the second clock cycle corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit is different by an integral multiple of the first clock cycle.
In the method, the selected buffer is inserted into the first data path circuit to obtain the second data path circuit through device delay of the electronic component included in the target path based on the first data path circuit, so that delay of each item marking path in the second data path circuit is consistent, burrs are prevented from being generated in the second data path circuit, namely, generation of burr power consumption is avoided, and power consumption of the data path circuit is reduced.
Furthermore, the second data path circuit is subjected to component adjustment operation to obtain an adjusted third data path circuit, wherein the delay difference of different input signals in the third data path circuit to the same logic device is integral multiple of the first clock cycle, so that the generation of burr power consumption in the third data path circuit can be avoided, the static power consumption of the data path circuit is reduced, the clock cycle of the third data path circuit is reduced on the basis of ensuring the low power consumption requirement of the data path circuit, the clock frequency of the third data path circuit is improved, and the operation speed and the operation capacity of the integrated circuit are further ensured.
In one possible implementation, the inserting a selected buffer into the first data path circuit based on a device delay of an electronic device included in a target path in the first data path circuit to obtain a second data path circuit includes:
determining a path delay corresponding to a target path in the first data path circuit based on a device delay of an electronic component included in the target path in the first data path circuit;
taking the maximum delay time in the path delay time corresponding to each target path in the first data path circuit as a target delay time;
and inserting the selected buffer into the first data path circuit based on the target delay and the intermediate delay from the register to the logic device included in the target path in the first data path circuit to obtain a second data path circuit.
Here, the selected buffer may be inserted into the first data path circuit based on the target delay and an intermediate delay between a register included in the target path in the first data path circuit and the logic, so as to obtain the second data path circuit, so that delays of respective entry mark paths in the second data path circuit are consistent, and thereby avoiding glitch power consumption of the data path circuit.
In one possible implementation, in a case where there is a first buffer between the input port and the first register of the first datapath circuit, and a second buffer between the second register and the output port of the first datapath circuit, after obtaining a second datapath, the method further includes:
taking the maximum delay time of the path delay time corresponding to each target path in the first data path circuit as a target delay time;
selecting a first component to be replaced and a second component to be replaced, the device delay of which is matched with the target delay, replacing the first buffer in the second data path with the first component to be replaced and replacing the second buffer with the second component to be replaced to obtain an intermediate data path circuit;
the performing component adjustment operations on the second datapath circuit includes:
and carrying out component adjustment operation on the intermediate data path circuit.
Here, the intermediate data path circuit is obtained by replacing components of the first buffer and the second buffer, so that the intermediate data path circuit meets the circuit design requirements.
In a possible implementation manner, the performing a component adjustment operation on the second datapath circuit to obtain an adjusted third datapath circuit includes:
performing at least one of the following component adjustment operations on the second datapath circuit: and replacing components, deleting components and adding components to obtain the adjusted third data path circuit.
Here, the second datapath circuit may be subjected to at least one of the following component adjustment operations: and the type of the adjustment operation of the components is various, so that the adjusted third data path circuit can be flexibly obtained.
In one possible implementation, in a case where a third buffer exists between a third register and an output port of the third datapath circuit, after obtaining the third datapath circuit, the method further includes:
and selecting a third component to be replaced, the delay of which is matched with the second clock period, and replacing the third buffer with the third component to be replaced to obtain a fourth data path circuit.
In one possible implementation, prior to determining the first data path circuit in the integrated circuit, the method further comprises:
and performing integer processing on the initial device delay of each electronic component in the integrated circuit by using an integer linear programming method to obtain the device delay of an integral multiple target unit corresponding to each electronic component.
Before determining a first data path circuit in the integrated circuit, performing integer processing on initial device delay of each electronic component in the integrated circuit by using an integer linear programming method to obtain device delay of an integer multiple target unit corresponding to each electronic component, namely, the device delay corresponding to each electronic component is an integer, so that the subsequent device delay based on each electronic component can be more conveniently and rapidly determined, the path delay of a target path can be more conveniently and rapidly determined, the data path circuit can be more accurately adjusted based on the path delay, and the adjusted data path circuit can meet the requirement of low power consumption.
The following descriptions of the effects of the apparatus, the electronic device, and the like refer to the description of the above method, and are not repeated here.
In a second aspect, the present disclosure provides a circuit adjustment apparatus comprising:
a determination module to determine a first datapath circuit in an integrated circuit; wherein a target path exists between different registers in the first data path circuit;
the first adjusting module is used for inserting the selected buffer into the first data path circuit based on the device delay of the electronic component included in the target path in the first data path circuit to obtain a second data path circuit, wherein the delay of each entry marking path in the second data path circuit is consistent;
the second adjusting module is used for carrying out component adjusting operation on the second data path circuit to obtain an adjusted third data path circuit; the first clock cycle corresponding to the third data path circuit is smaller than the second clock cycle corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit is different by an integral multiple of the first clock cycle.
In a possible implementation manner, the first adjusting module, when inserting the selected buffer into the first datapath circuit based on the device delay of the electronic component included in the target path in the first datapath circuit to obtain the second datapath circuit, is configured to:
determining a path delay corresponding to a target path in the first data path circuit based on a device delay of an electronic component included in the target path in the first data path circuit;
taking the maximum delay time in the path delay time corresponding to each target path in the first data path circuit as a target delay time;
and inserting the selected buffer into the first data path circuit based on the target delay and the intermediate delay from the register to the logic device included in the target path in the first data path circuit to obtain a second data path circuit.
In one possible implementation, where there is a first buffer between the input port and the first register of the first datapath circuit, and a second buffer between the second register and the output port of the first datapath circuit, after obtaining a second datapath, the apparatus further includes: a first replacement module to:
taking the maximum delay time of the path delay time corresponding to each target path in the first data path circuit as a target delay time;
selecting a first component to be replaced and a second component to be replaced, the device delay of which is matched with the target delay, replacing the first buffer in the second data path with the first component to be replaced and replacing the second buffer with the second component to be replaced to obtain an intermediate data path circuit;
the second adjusting module, when performing a component adjustment operation on the second datapath circuit, is configured to:
and carrying out component adjustment operation on the intermediate data path circuit.
In a possible implementation manner, when performing a component adjustment operation on the second datapath circuit to obtain an adjusted third datapath circuit, the second adjusting module is configured to:
performing at least one of the following component adjustment operations on the second datapath circuit: and replacing components, deleting components and adding components to obtain the adjusted third data path circuit.
In one possible implementation, in a case where a third buffer exists between a third register and an output port of the third datapath circuit, after obtaining the third datapath circuit, the apparatus further includes: a second replacement module to:
and selecting a third component to be replaced, the delay of which is matched with the second clock period, and replacing the third buffer with the third component to be replaced to obtain a fourth data path circuit.
In one possible implementation, prior to determining the first data path circuit in the integrated circuit, the apparatus further comprises: a processing module to:
and performing integer processing on the initial device delay of each electronic component in the integrated circuit by using an integer linear programming method to obtain the device delay of an integral multiple target unit corresponding to each electronic component.
In a third aspect, the present disclosure provides a data path circuit comprising: at least one component of a logic device, a register and a buffer;
the data path circuit is generated based on the circuit adjustment method according to the first aspect or any one of the embodiments.
In a fourth aspect, the present disclosure provides an electronic device comprising: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating via the bus when the electronic device is running, the machine-readable instructions being executable by the processor to perform the steps of the circuit adjusting method according to the first aspect or any one of the embodiments or to include the data path circuit disclosed in the third aspect.
In a fifth aspect, the present disclosure provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the circuit adjustment method according to the first aspect or any one of the embodiments.
In order to make the aforementioned objects, features and advantages of the present disclosure more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly described below, and the drawings herein incorporated in and forming a part of the specification illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the technical solutions of the present disclosure. It is appreciated that the following drawings depict only certain embodiments of the disclosure and are therefore not to be considered limiting of its scope, for those skilled in the art will be able to derive additional related drawings therefrom without the benefit of the inventive faculty.
Fig. 1 is a schematic flow chart illustrating a circuit adjustment method according to an embodiment of the present disclosure;
FIG. 2a is a schematic diagram of a first data path circuit provided by an embodiment of the present disclosure;
FIG. 2b is a schematic diagram of a second datapath circuit provided by an embodiment of the present disclosure;
FIG. 2c shows a schematic diagram of an intermediate data path circuit provided by an embodiment of the present disclosure;
FIG. 2d is a schematic diagram of a third datapath circuit provided by embodiments of the present disclosure;
FIG. 2e is a schematic diagram of a fourth datapath circuit provided by an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating an architecture of a circuit adjustment apparatus according to an embodiment of the present disclosure;
fig. 4 shows a schematic structural diagram of an electronic device provided in an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure, presented in the figures, is not intended to limit the scope of the claimed disclosure, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the disclosure without making creative efforts, shall fall within the protection scope of the disclosure.
Along with the higher integration level and stronger calculation, the low power consumption design of the chip is more and more emphasized. The power consumption of the chip is mainly divided into static power consumption and dynamic power consumption. Static power consumption refers to leakage power consumption when a circuit of a chip is maintained in an inactive state, that is, power consumption under the condition of no load; dynamic power consumption is primarily the power consumption that occurs when a switch flips in response to input changes and/or glitches. Glitches are false flips experienced by a logic gate before it reaches the steady state value of the cycle, due to different delays in the input path of the logic gate, and not only are the glitches at risk of causing a functional error in the chip, but they also cause a loss in power consumption.
In order to reduce power consumption of a chip, embodiments of the present disclosure provide a circuit adjustment method, an apparatus, an electronic device, a storage medium, and a circuit.
The above-mentioned drawbacks are the results of the inventor after practical and careful study, and therefore, the discovery process of the above-mentioned problems and the solutions proposed by the present disclosure to the above-mentioned problems should be the contribution of the inventor in the process of the present disclosure.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
For the convenience of understanding the embodiments of the present disclosure, a circuit adjusting method disclosed in the embodiments of the present disclosure will be described in detail first. The execution main body of the circuit adjustment method provided by the embodiment of the disclosure may be a chip, a server, a terminal device, and the like, for example, the terminal device may be a computer, a tablet, and the like.
Referring to fig. 1, which is a schematic flow chart of a circuit adjustment method provided in the embodiment of the present disclosure, S101 to S103, wherein:
s101, determining a first data path circuit in an integrated circuit; wherein a target path exists between different registers in the first data path circuit;
s102, inserting a selected buffer into the first data path circuit based on device delay of an electronic component included in a target path in the first data path circuit to obtain a second data path circuit, wherein delay of each entry marking path in the second data path circuit is consistent;
s103, carrying out component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; the first clock cycle corresponding to the third data path circuit is smaller than the second clock cycle corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit is different by an integral multiple of the first clock cycle.
In the method, the selected buffer is inserted into the first data path circuit to obtain the second data path circuit through device delay of the electronic component included in the target path based on the first data path circuit, so that delay of each item marking path in the second data path circuit is consistent, burrs are prevented from being generated in the second data path circuit, namely, generation of burr power consumption is avoided, and power consumption of the data path circuit is reduced.
Furthermore, the second data path circuit is subjected to component adjustment operation to obtain an adjusted third data path circuit, wherein the delay difference of different input signals in the third data path circuit to the same logic device is integral multiple of the first clock cycle, so that the generation of burr power consumption in the third data path circuit can be avoided, the static power consumption of the data path circuit is reduced, the clock cycle of the third data path circuit is reduced on the basis of ensuring the low power consumption requirement of the data path circuit, the clock frequency of the third data path circuit is improved, and the operation speed and the operation capacity of the integrated circuit are further ensured.
S101 to S103 will be specifically described below.
For S101:
a first datapath circuit in the integrated circuit is determined, where the first datapath circuit may be the determined datapath circuit to be adjusted. For example, a data path circuit in which a glitch exists in the integrated circuit may be determined as a first data path circuit; and/or, a data path circuit with a greater delay in the integrated circuit may be identified as the first data path circuit, etc. A path through which data is transmitted between the functional units is called a data path, the functional units (components) may be, for example, registers, logic devices, and the like, and each functional unit on the transmission path constitutes a data path circuit; data path circuits in which glitches exist may be, for example, circuits that generate glitches for inconsistent delays of input signals arriving at the same logic from different paths.
Target paths exist among different registers in the first data path circuit, and the circuit structure of the first data path circuit can be selected according to actual conditions. Referring to FIG. 2a, a schematic diagram of a first data path circuit is shown, FIG. 2a includingComprises a buffer A, a buffer B, an AND gate logic C, an AND gate logic D, a buffer E and a register R1Register R2Register R3(ii) a In fig. 2a there are three target pathways, the first being: register R1>AND gate logic device C>AND gate logic device D>Register R3(ii) a The second target path is: register R2>Buffer B>AND gate logic device C>AND gate logic device D>Register R3(ii) a The third target pathway is: register R2>Buffer B>AND gate logic device D>Register R3. The corresponding number for each electronic component in fig. 2a represents the device delay for that electronic component.
In an alternative embodiment, prior to determining the first data path circuit in the integrated circuit, the method further comprises: and performing integer processing on the initial device delay of each electronic component in the integrated circuit by using an integer linear programming method to obtain the device delay of an integral multiple target unit corresponding to each electronic component.
In practice, the initial device delay of each electronic component is related to the performance, material and the like of the electronic component. The initial device delay of each electronic component can be predetermined, and then the integer linear programming method is utilized to perform integer processing on the initial device delay of each electronic component, so that the device delay of the integral multiple target unit corresponding to each electronic component is obtained. And performing integer processing on the initial device delay of each candidate electronic component included in the component database to obtain the device delay of an integral multiple target unit corresponding to the candidate electronic component.
For example, if the initial device delay of the electronic component 1 is 0.01s (second), the initial device delay of the electronic component 2 is 0.05s, and the initial device delay of the electronic component 3 is 0.07s, then after the integer processing, the device delay of the electronic component 1 is 1 (representing the device delay of 1 target unit), the device delay of the electronic component 2 is 5 (representing the device delay of 5 target units), the device delay of the electronic component 3 is 7 (representing the device delay of 7 target units), and each target unit is 0.01 s.
It can be seen that buffer a in fig. 2a corresponds to a device delay of 3 target units. Wherein the size of the target unit can be set according to actual conditions.
Before determining a first data path circuit in the integrated circuit, performing integer processing on initial device delay of each electronic component in the integrated circuit by using an integer linear programming method to obtain device delay of an integer multiple target unit corresponding to each electronic component, namely, the device delay corresponding to each electronic component is an integer, so that the subsequent device delay based on each electronic component can be more conveniently and rapidly determined, the path delay of a target path can be more conveniently and rapidly determined, the data path circuit can be more accurately adjusted based on the path delay, and the adjusted data path circuit can meet the requirement of low power consumption.
For S102:
when the time delay of different input signals reaching the same logic device is different, the logic device can generate burrs, so that the circuit has burr power consumption. Therefore, the buffer can be inserted into the circuit, and the generation of burrs is avoided, so that the power consumption of the burrs generated by the circuit is reduced.
In an alternative embodiment, in S102, the inserting a selected buffer into the first datapath circuit based on the device delay of the electronic device included in the target path in the first datapath circuit to obtain a second datapath circuit may include steps a 1-A3, where:
step A1, determining a path delay corresponding to a target path in the first data path circuit based on a device delay of an electronic component included in the target path in the first data path circuit;
step A2, using the maximum delay time of the path delay time corresponding to each target path in the first data path circuit as the target delay time;
step a3, inserting a selected buffer into the first datapath circuit based on the target delay and an intermediate delay between a register and a logic included in a target path in the first datapath circuit to obtain a second datapath circuit.
In implementation, for each target path in the first data path circuit, the path delay of the target path may be determined according to the device delay of each electronic component included in the target path, and the path delay corresponding to each target path included in the first data path circuit may be obtained. Further, the maximum delay among the path delays corresponding to the target paths in the first data path circuit may be determined, and the maximum delay may be used as the target delay.
When the first datapath circuit is the datapath circuit shown in fig. 2a, it can be seen that the first target path included in fig. 2a has a path delay of 6 target units, the second target path has a path delay of 7 target units, and the third target path has a path delay of 3 target units. The path delay of the second target path is used as the target delay, that is, the target delay is a delay of 7 target units.
An intermediate delay between a register to logic included in a target lane of the first data lane circuit is determined. For example, register R in FIG. 2a1The intermediate delay between the AND gate logic C is 0, register R2The intermediate delay to AND gate logic C is 1, register R1Intermediate delay to AND gate logic D is 6, register R2The first path between the and gate logic D has an intermediate delay of 7 and the second path has an intermediate delay of 3.
And further inserting the selected buffer into the first data path circuit based on the target delay and each intermediate delay to obtain a second data path circuit. The buffer to be inserted into the first data path circuit may be selected from the component database according to performance information, such as the size of each buffer, the device delay, and the like, stored in the component database.
For example, after the first datapath circuit in fig. 2a is adjusted, the second datapath circuit shown in fig. 2b is obtained, that is, a buffer a with a device delay of 1 target unit and a buffer b with a device delay of 4 target units are added to the first datapath circuit, so that the delays of the respective entry target paths in the second datapath circuit are consistent, that is, the delay of each target path is the target delay. Wherein the second clock cycle of the second datapath circuit shown in fig. 2b is 7 target units.
Here, the selected buffer may be inserted into the first data path circuit based on the target delay and an intermediate delay between a register included in the target path in the first data path circuit and the logic, so as to obtain the second data path circuit, so that delays of respective entry mark paths in the second data path circuit are consistent, and thereby avoiding glitch power consumption of the data path circuit.
For S103:
in an alternative embodiment, where there is a first buffer between the input port and the first register of the first datapath circuit, and a second buffer between the second register and the output port of the first datapath circuit, after obtaining a second datapath, the method further comprises:
step B1, regarding the maximum delay among the path delays corresponding to each of the target paths in the first data path circuit as a target delay;
and step B2, selecting a first component to be replaced and a second component to be replaced, the device delay of which is matched with the target delay, replacing the first buffer in the second data path with the first component to be replaced and replacing the second buffer with the second component to be replaced, and obtaining an intermediate data path circuit.
During implementation, a first to-be-replaced component with the component delay matched with the target delay can be selected from the component database, and the first buffer is replaced by the first to-be-replaced component. And selecting a second component to be replaced with the component delay matched with the target delay from the component database, and replacing the second buffer with the second component to be replaced. The size, the performance and the like of the first buffer and the first component to be replaced are matched, and the size, the performance and the like of the second buffer and the second component to be replaced are matched.
If the first buffer exists but the second buffer does not exist, selecting a first component to be replaced with the delay matched with the target delay from the component database, and replacing the first buffer with the first component to be replaced; and if the second buffer exists but the first buffer does not exist, selecting a second component to be replaced with the component delay matched with the target delay from the component database, and replacing the second buffer with the second component to be replaced.
Taking the second data path circuit shown in fig. 2b as an example for explanation, the second data path circuit in fig. 2b includes a first buffer a and a second buffer E, and the target delay time is a delay time of 7 target units, the first buffer a may be replaced by a first component to be replaced a1 whose device delay time is 7 target units, and the second buffer E may be replaced by a second component to be replaced E1 whose device delay time is 7 target units, so as to obtain the intermediate data path circuit shown in fig. 2 c.
The performing a component adjustment operation on the second datapath circuit may include: and carrying out component adjustment operation on the intermediate data path circuit.
And the intermediate data path circuit is obtained by replacing components of the first buffer and the second buffer, so that the intermediate data path circuit meets the circuit design requirement to ensure that the integrated circuit can normally work.
In an optional implementation manner, the performing a component adjustment operation on the second datapath circuit to obtain an adjusted third datapath circuit includes: performing at least one of the following component adjustment operations on the second datapath circuit: and replacing components, deleting components and adding components to obtain the adjusted third data path circuit.
Because the input of the data path circuit is a clock signal, a certain clock period exists, and the clock period comprises signals of a plurality of beats; in the data path circuit, if different signals input to the same logic device are signals of the same beat in the clock signal (i.e., the delay time of different signals reaching the same logic device is different by an integral multiple of the first clock cycle), the logic device in the data path circuit does not generate glitches. Based on the method, the second data path circuit can be subjected to at least one component adjustment operation of component replacement, component deletion and component addition by using a clock deviation planning method, so that an adjusted third data path circuit is obtained. The method for planning the clock deviation comprises the following steps: the method is used for planning the clock period and the components of the data path circuit by taking the integral multiple of the delay difference clock period when different input signals reach the same logic device as a target.
For example, when the clock cycle is 4 seconds, if the two signals input to the same logic device are the signal at the time of 1 second and the signal at the time of 5 seconds, the signals input to the same logic device are the signals of the same beat in the clock signal.
For example, a target clock cycle (i.e., a first clock cycle) may be determined, and a third datapath circuit may be obtained by performing at least one component adjustment operation of component replacement, component deletion, and component addition on the second datapath circuit or the intermediate datapath circuit, so that the clock cycle of the third datapath circuit is the target clock cycle.
The intermediate data path circuit shown in fig. 2c is subjected to at least one component adjustment operation to obtain a third data path circuit as shown in fig. 2d, for example, the buffer a1 (i.e. the first component a1 to be replaced) in the intermediate data path circuit in fig. 2c may be replaced by the buffer a2 with the device delay of 3 target units, and the buffer a may be deleted to obtain the third data path circuit. Wherein the first clock cycle of the third datapath circuit is 4 target units. The first clock cycle of the third data path circuit may be determined based on a delay of each component included in the third data path circuit.
As can be seen from fig. 2d, the delay of the input signal 1 reaching the and logic C is 0, the delay of the input signal 2 reaching the and logic C is 4, and the delay difference of the two input signals reaching the and logic C is 4, i.e. the delay difference of the different input signals reaching the and logic C is 1 time of the first clock cycle. Input signal 1 arrives atThe delay of the gate logic D is 4 and the input signal 2 passes through the first path (buffer a 2)>Register R2>Buffer B>And gate logic C) to and gate logic D with a delay of 8, input signal 2 passes through the second path (buffer a 2)>Register R2>Buffer B>The delay of the buffer b) to the and logic device D is 8, and the delay difference of the two input signals to the and logic device D is 4, i.e. the delay difference of the different input signals to the and logic device D is 1 time of the first clock cycle.
Here, the second datapath circuit may be subjected to at least one of the following component adjustment operations: and the type of the adjustment operation of the components is various, so that the adjusted third data path circuit can be flexibly obtained.
In an alternative embodiment, in the presence of a third buffer between a third register and an output port of the third datapath circuit, after obtaining the third datapath circuit, the method further comprises: and selecting a third component to be replaced, the delay of which is matched with the second clock period, and replacing the third buffer with the third component to be replaced to obtain a fourth data path circuit.
Taking the third data path circuit shown in fig. 2d as an example, when the third data path circuit includes the third buffer E1, the third component to be replaced E2 with a device delay matching the second clock cycle may be selected from the component database, and the third buffer is replaced with the third component to be replaced E2, so as to obtain the fourth data path circuit shown in fig. 2E, so as to ensure that other data path circuits connected to the third component to be replaced of the fourth data path circuit in the integrated circuit can operate normally.
It will be understood by those skilled in the art that in the method of the present invention, the order of writing the steps does not imply a strict order of execution and any limitations on the implementation, and the specific order of execution of the steps should be determined by their function and possible inherent logic.
Based on the same concept, an embodiment of the present disclosure further provides a circuit adjusting apparatus, as shown in fig. 3, which is an architecture schematic diagram of the circuit adjusting apparatus provided in the embodiment of the present disclosure, and includes a determining module 301, a first adjusting module 302, and a second adjusting module 303, specifically:
a determination module 301 for determining a first datapath circuit in an integrated circuit; wherein a target path exists between different registers in the first data path circuit;
a first adjusting module 302, configured to insert a selected buffer into the first data path circuit based on device delay of an electronic component included in a target path in the first data path circuit to obtain a second data path circuit, where delay of each entry mark path in the second data path circuit is consistent;
a second adjusting module 303, configured to perform a component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; the first clock cycle corresponding to the third data path circuit is smaller than the second clock cycle corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit is different by an integral multiple of the first clock cycle.
In a possible implementation manner, the first adjusting module 302, when inserting the selected buffer into the first datapath circuit based on the device delay of the electronic component included in the target path in the first datapath circuit to obtain the second datapath circuit, is configured to:
determining a path delay corresponding to a target path in the first data path circuit based on a device delay of an electronic component included in the target path in the first data path circuit;
taking the maximum delay time in the path delay time corresponding to each target path in the first data path circuit as a target delay time;
and inserting the selected buffer into the first data path circuit based on the target delay and the intermediate delay from the register to the logic device included in the target path in the first data path circuit to obtain a second data path circuit.
In one possible implementation, where there is a first buffer between the input port and the first register of the first datapath circuit, and a second buffer between the second register and the output port of the first datapath circuit, after obtaining a second datapath, the apparatus further includes: a first replacement module 304 to:
taking the maximum delay time of the path delay time corresponding to each target path in the first data path circuit as a target delay time;
selecting a first component to be replaced and a second component to be replaced, the device delay of which is matched with the target delay, replacing the first buffer in the second data path with the first component to be replaced and replacing the second buffer with the second component to be replaced to obtain an intermediate data path circuit;
the second adjusting module 303, when performing a component adjusting operation on the second datapath circuit, is configured to:
and carrying out component adjustment operation on the intermediate data path circuit.
In a possible implementation manner, the second adjusting module 303, when performing a component adjustment operation on the second datapath circuit to obtain an adjusted third datapath circuit, is configured to:
performing at least one of the following component adjustment operations on the second datapath circuit: and replacing components, deleting components and adding components to obtain the adjusted third data path circuit.
In one possible implementation, in a case where a third buffer exists between a third register and an output port of the third datapath circuit, after obtaining the third datapath circuit, the apparatus further includes: a second replacement module 305 for:
and selecting a third component to be replaced, the delay of which is matched with the second clock period, and replacing the third buffer with the third component to be replaced to obtain a fourth data path circuit.
In one possible implementation, prior to determining the first data path circuit in the integrated circuit, the apparatus further comprises: a processing module 306 configured to:
and performing integer processing on the initial device delay of each electronic component in the integrated circuit by using an integer linear programming method to obtain the device delay of an integral multiple target unit corresponding to each electronic component.
Based on the same concept, the embodiments of the present disclosure also provide a data path circuit, including: at least one component of a logic device, a register and a buffer; the data path circuit is generated based on the circuit adjustment method described in the above embodiment.
In some embodiments, the functions of the apparatus provided in the embodiments of the present disclosure or the included templates may be used to execute the method described in the above method embodiments, and specific implementation thereof may refer to the description of the above method embodiments, and for brevity, no further description is provided here.
Based on the same technical concept, the embodiment of the disclosure also provides an electronic device. Referring to fig. 4, a schematic structural diagram of an electronic device provided in the embodiment of the present disclosure includes a processor 401, a memory 402, and a bus 403. The memory 402 is used for storing execution instructions and includes a memory 4021 and an external memory 4022; the memory 4021 is also referred to as an internal memory, and is configured to temporarily store operation data in the processor 401 and data exchanged with the external memory 4022 such as a hard disk, the processor 401 exchanges data with the external memory 4022 through the memory 4021, and when the electronic device 400 operates, the processor 401 communicates with the memory 402 through the bus 403, so that the processor 401 executes the following instructions:
determining a first data path circuit in the integrated circuit; wherein a target path exists between different registers in the first data path circuit;
inserting a selected buffer into the first data path circuit based on device delay of an electronic component included in a target path in the first data path circuit to obtain a second data path circuit, wherein delay of each item marking path in the second data path circuit is consistent;
performing component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; the first clock cycle corresponding to the third data path circuit is smaller than the second clock cycle corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit is different by an integral multiple of the first clock cycle.
The specific processing flow of the processor 401 may refer to the description of the above method embodiment, and is not described herein again.
Furthermore, the embodiments of the present disclosure also provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program performs the steps of the circuit adjusting method described in the above method embodiments. The storage medium may be a volatile or non-volatile computer-readable storage medium.
The embodiments of the present disclosure also provide a computer program product, where the computer program product carries a program code, and instructions included in the program code may be used to execute the steps of the circuit adjusting method in the foregoing method embodiments, which may be referred to specifically in the foregoing method embodiments, and are not described herein again.
The computer program product may be implemented by hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied in a computer storage medium, and in another alternative embodiment, the computer program product is embodied in a Software product, such as a Software Development Kit (SDK), or the like.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the system and the apparatus described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, apparatus, and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above are only specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and shall be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A circuit adjustment method, comprising:
determining a first data path circuit in the integrated circuit; wherein a target path exists between different registers in the first data path circuit;
inserting a selected buffer into the first data path circuit based on device delay of an electronic component included in a target path in the first data path circuit to obtain a second data path circuit, wherein delay of each item marking path in the second data path circuit is consistent;
performing component adjustment operation on the second data path circuit to obtain an adjusted third data path circuit; the first clock cycle corresponding to the third data path circuit is smaller than the second clock cycle corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit is different by an integral multiple of the first clock cycle.
2. The method of claim 1, wherein inserting a selected buffer into the first datapath circuit based on a device delay of an electronic component included in a target path in the first datapath circuit to obtain a second datapath circuit comprises:
determining a path delay corresponding to a target path in the first data path circuit based on a device delay of an electronic component included in the target path in the first data path circuit;
taking the maximum delay time in the path delay time corresponding to each target path in the first data path circuit as a target delay time;
and inserting the selected buffer into the first data path circuit based on the target delay and the intermediate delay from the register to the logic device included in the target path in the first data path circuit to obtain a second data path circuit.
3. The method of claim 1 or 2, wherein, in the presence of a first buffer between the input port and the first register of the first datapath circuit, and in the presence of a second buffer between the second register and the output port of the first datapath circuit, after obtaining a second datapath, the method further comprises:
taking the maximum delay time of the path delay time corresponding to each target path in the first data path circuit as a target delay time;
selecting a first component to be replaced and a second component to be replaced, the device delay of which is matched with the target delay, replacing the first buffer in the second data path with the first component to be replaced and replacing the second buffer with the second component to be replaced to obtain an intermediate data path circuit;
the performing component adjustment operations on the second datapath circuit includes:
and carrying out component adjustment operation on the intermediate data path circuit.
4. The method according to any one of claims 1 to 3, wherein performing a component adjustment operation on the second datapath circuit to obtain an adjusted third datapath circuit comprises:
performing at least one of the following component adjustment operations on the second datapath circuit: and replacing components, deleting components and adding components to obtain the adjusted third data path circuit.
5. The method of any of claims 1 to 4, wherein in the presence of a third buffer between a third register of the third datapath circuit and an output port, after obtaining the third datapath circuit, the method further comprises:
and selecting a third component to be replaced, the delay of which is matched with the second clock period, and replacing the third buffer with the third component to be replaced to obtain a fourth data path circuit.
6. The method of any of claims 1-5, wherein prior to determining the first datapath circuit in the integrated circuit, the method further comprises:
and performing integer processing on the initial device delay of each electronic component in the integrated circuit by using an integer linear programming method to obtain the device delay of an integral multiple target unit corresponding to each electronic component.
7. A circuit adjustment device, comprising:
a determination module to determine a first datapath circuit in an integrated circuit; wherein a target path exists between different registers in the first data path circuit;
the first adjusting module is used for inserting the selected buffer into the first data path circuit based on the device delay of the electronic component included in the target path in the first data path circuit to obtain a second data path circuit, wherein the delay of each entry marking path in the second data path circuit is consistent;
the second adjusting module is used for carrying out component adjusting operation on the second data path circuit to obtain an adjusted third data path circuit; the first clock cycle corresponding to the third data path circuit is smaller than the second clock cycle corresponding to the second data path circuit, and the delay of different input signals reaching the same logic device in the third data path circuit is different by an integral multiple of the first clock cycle.
8. A data path circuit, comprising: at least one component of a logic device, a register and a buffer;
the datapath circuit is generated based on the circuit adjustment method of any one of claims 1 to 6.
9. An electronic device, comprising: processor, memory and bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating via the bus when the electronic device is operating, the machine-readable instructions when executed by the processor performing the steps of the circuit adjustment method according to any one of claims 1 to 6, or
Comprising the data path circuitry of claim 8.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the circuit adjustment method according to one of claims 1 to 6.
CN202111275866.XA 2021-10-29 2021-10-29 Circuit adjusting method, circuit adjusting device, electronic equipment, storage medium and circuit Pending CN113992193A (en)

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