JPH10178042A - Board for semiconductor integrated circuit connection, component constituting the same, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable improvement in workability, adhesiveness, insulating reliability and durability, by incorporating respectively at lest one type of resin having urethane coupling and/or urea coupling in the main chain and of thermoplastic resin as essential components of an adhesive composition forming an adhesive layer. SOLUTION: After aluminum hydroxide is mixed with methyl ethyl ketone, sand mill processing is carried out to prepare an aluminum hydroxide dispersion solution. To this dispersion solution, polyurethane resin, butadiene/acrylonitride/ acrylic acid copolymer, epoxy resin, and 4,4'-diamniodiphenylsulfone are added at a predetermined composition ratio, thus preparing an adhesive solution. The adhesive solution is applied to and dried on a polyethylene terephthalate film with a silicone releasant. Meanwhile, an adhesive layer is prepared by the same method except for using a polyethylene terephthalate film with a silicone separating agent of less peel strength. Adhesive surfaces of these sheets are put together, thus providing an adhesive sheet for semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit connecting substrate (interposer) used for mounting and packaging a semiconductor integrated circuit, components constituting the same, and a semiconductor device. For more information,
A wiring board layer composed of an insulator layer and a conductor pattern constituting a substrate for connecting a semiconductor integrated circuit used in a ball grid array (BGA), a land grid array (LGA), and a pin grid array (PGA) system, for example, a metal reinforcing plate (Stiffener) and other layers on which no conductor pattern is formed are bonded by an adhesive composition having a function of relaxing thermal stress generated between the layers due to a temperature difference, and are connected to a semiconductor integrated circuit having a laminated structure. The present invention relates to a substrate for use, components constituting the same, and a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor integrated circuit (IC) package, a dual in-line package (DIP),
Package forms such as a small outline package (SOP) and a quad flat package (QFP) have been used. However, with the increase in the number of pins of the IC and the miniaturization of the package, the limit of the QFP that can increase the number of pins is approaching its limit. This is due to the difficulty in maintaining the flatness of the leads and the difficulty in obtaining solder printing accuracy on the printed circuit board, particularly when mounting on a printed circuit board.
Therefore, in recent years, BGA method, LGA method, PGA method and the like have been put to practical use as means for increasing the number of pins and reducing the size.
Above all, the BGA method has attracted attention because of its high possibility of cost reduction, weight reduction and thickness reduction by using plastic materials.

FIG. 1 shows an example of the BGA system. The BGA method is characterized in that solder balls almost corresponding to the number of pins of an IC are provided on a grid (grid array) as external connection portions of a semiconductor integrated circuit connection substrate to which the IC is connected. The connection to the printed circuit board is performed by placing the solder ball surface on the conductor pattern of the printed circuit board on which the solder is already printed so as to match the conductor pattern, and melting the solder by reflow. The greatest feature is that since the surface of the substrate for connecting a semiconductor integrated circuit can be used, more terminals can be arranged in a smaller space as compared with a package such as QFP which can use only peripheral sides. A chip scale package (CSP) has further advanced this miniaturization function.
Due to their similarity, they may be referred to as micro BGA (μ-BGA). The present invention relates to a CS having these BGA structures.
Applicable to P.

On the other hand, the BGA method has the following problems. (A) maintaining the flatness of the solder ball surface; (b) improving the heat dissipation; (c) mitigating the thermal stress applied to the solder ball during temperature cycling and reflow; (d) higher due to the large number of reflows Requires reflow resistance. As a method of improving these, a method of laminating a material such as a metal plate for reinforcement, heat radiation, and electromagnetic shielding on a substrate for connecting a semiconductor integrated circuit is generally used. In particular, the insulating substrate layer for connecting the IC and the wiring board layer composed of the conductor pattern have a TA
This is important when a B tape or a flexible printed circuit board is used. For this reason, the substrate for connecting a semiconductor integrated circuit includes an insulator layer 1 for connecting an IC as illustrated in FIG.
A layer 15 on which no conductor pattern is formed, such as a wiring board layer composed of the conductor pattern 1 and the conductor pattern 13, a reinforcing plate (stiffener), a heat sink (heat spreader), and a shield plate;
And at least one adhesive layer 14 for laminating them. These semiconductor integrated circuit connection substrates are prepared as intermediate products by laminating or applying and drying an adhesive composition in a semi-cured state on either a wiring substrate layer or a layer on which no conductor pattern is formed. In general, it is generally formed by bonding, heating, curing and molding in a process before connecting the ICs.

[0005] From the above points, the following characteristics are required as the characteristics required of the adhesive layer 14. (A) high adhesive strength that does not peel off even under reflow conditions (230 ° C. or higher),
(B) To reduce thermal stress applied between dissimilar materials such as a wiring board layer and a reinforcing plate during a temperature cycle or reflow,
Moderate elastic modulus and linear expansion coefficient characteristics, (c) easy workability that enables low-temperature, short-time bonding and heating and curing, and (d) insulating properties when laminated on wiring.

[0006] From such a viewpoint, conventionally, a thermoplastic resin or a silicone elastomer (Japanese Patent Publication No.
-50448) and the like.

[0007]

However, it has been difficult to balance the thermal stress relaxation effect and the reflow resistance with respect to the adhesive force among the above-mentioned characteristics. That is, in the conventional adhesive composition, when the adhesive strength is improved, the elastic modulus at a high temperature is reduced, and the reflow property is also reduced.

[0008] In general, it is possible to increase the breaking energy by lowering the elastic modulus of the adhesive, thereby improving the adhesive force.
There is a problem that the adhesive softens under high humidity, and the reflow resistance and the adhesive strength at high temperature and high humidity decrease. On the other hand, in order to improve reflow resistance and adhesion at high temperature and high humidity,
Increasing the degree of crosslinking of the adhesive is not preferred because the adhesive is liable to brittle fracture and the internal stress is increased due to curing shrinkage, which lowers the adhesive strength. Furthermore, the effect of relaxing the thermal stress caused by the temperature difference is also lost.

Although a method of using a thermoplastic resin having a high softening point is also conceivable, a high bonding temperature is required when preparing a substrate for connecting a semiconductor integrated circuit, and the wiring substrate layer is damaged, and the dimensional accuracy is reduced. Cause trouble.

The present invention solves such problems and provides a novel substrate for connecting a semiconductor integrated circuit which is excellent in processability, adhesive strength, insulation reliability and durability, a component constituting the substrate, and a semiconductor device. The purpose is to:

[0011]

Means for Solving the Problems In order to achieve the above object, the present inventors have intensively studied the cured physical properties of an adhesive layer constituting a substrate for connecting a semiconductor integrated circuit, and as a result, have found that urethane is contained in the main chain. It has been found that, by skillfully combining a resin containing a bond and / or a urea bond with a thermosetting resin, a substrate for connecting a semiconductor integrated circuit having excellent adhesive force and thermal stress relaxation effect can be obtained, which has led to the present invention. Things.

That is, the present invention provides a semiconductor having at least one layer of (A) a wiring board layer composed of an insulator layer and a conductor pattern, (B) a layer having no conductor pattern formed thereon, and (C) an adhesive layer. An integrated circuit connecting substrate, wherein (C) an adhesive composition for forming an adhesive layer comprises, as essential components, at least one or more resins each containing a urethane bond and / or a urea bond in a main chain and a thermosetting resin. A semiconductor integrated circuit connecting substrate, components constituting the same, and a semiconductor device characterized by including the above.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The substrate for connecting a semiconductor integrated circuit according to the present invention is for connecting a semiconductor integrated circuit (bare chip) which has been separated after a device is formed on a semiconductor substrate such as silicon. (A) a wiring board layer comprising an insulator layer and a conductor pattern, (B) a layer having no conductor pattern formed thereon, and (C) an adhesive layer comprising the adhesive composition of the present invention, each having at least one or more layers. If so, the shape, material, and manufacturing method are not particularly limited. Therefore, the most basic structure is A / C / B, but this also includes a multilayer structure such as A / C / B / C / B.

(A) is a layer having a conductor pattern for connecting an electrode pad of a bare chip to the outside of a package (a printed circuit board or the like). The conductor pattern is formed on one or both sides of an insulator layer. is there. The insulator layer referred to here is made of a plastic such as polyimide, polyester, polyphenylene sulfide, polyether sulfone, polyether ether ketone, aramid, polycarbonate, polyarylate, or a composite material such as an epoxy resin impregnated glass cloth, and has a thickness of 10%. ~ 125μ
An insulating film having a flexibility of m, a ceramic substrate of alumina, zirconia, soda glass, quartz glass, or the like is suitable, and a plurality of layers selected from these may be laminated and used. If necessary, the insulator layer may be subjected to surface treatment such as hydrolysis, corona discharge, low-temperature plasma, physical surface roughening, and easy adhesion coating treatment. The formation of the conductor pattern is generally performed by either the subtractive method or the additive method, but any of them may be used in the present invention. In the subtractive method, a metal plate such as a copper foil is adhered to the insulator layer with an insulating adhesive (the adhesive composition of the present invention can also be used), or the metal plate is provided with the insulator layer. A pattern is formed by stacking precursors and etching a material prepared by a method of forming an insulator layer by heat treatment or the like by a chemical solution treatment. Specific examples of the material here include copper-clad materials for rigid or flexible printed circuit boards and TAB.
An example is a tape (FIG. 3). In particular, at least one layer or more of a polyimide film is used as an insulator layer, and a wiring board layer made by a subtractive method using a copper-clad material for flexible printed circuit boards or a TAB tape using a copper foil as a conductor pattern has a fine pattern. It is preferable because not only has a good track record in forming, but also it can be continuously produced in the form of a long film, so that it is economical.

On the other hand, in the additive method, a conductor pattern is directly formed on the insulator layer by electroless plating, electrolytic plating, sputtering or the like. In any case, the formed conductor may be plated with a metal having high corrosion resistance to prevent corrosion. Via holes may be formed in the wiring board layer (A) formed as described above, if necessary, and the conductor patterns formed on both sides by plating may be connected by plating. (B) is a uniform layer substantially independent of (A) or (C), which reinforces and dimensionally stabilizes a substrate for connecting a semiconductor integrated circuit (generally referred to as a reinforcing plate or stiffener); Electromagnetic shielding of ICs, heat dissipation of ICs (generally referred to as heat sinks, heat spreaders, heat sinks), imparting flame retardancy to substrates for connecting semiconductor integrated circuits, and discrimination by shape of substrates for connecting semiconductor integrated circuits It has functions such as imparting properties. Therefore, the shape may be not only a layer shape but also a three-dimensional shape having a fin structure for heat dissipation.
In addition, any insulator or conductor may be used as long as it has the above function, and the material is not particularly limited. Examples of metals include copper, iron, aluminum, gold, silver, nickel, and titanium. Examples of the material include alumina, zirconia, soda glass, quartz glass, carbon, and the like, and examples of the organic material include polyimide, polyamide, polyester, vinyl, phenol, and epoxy polymer materials. Further, a composite material obtained by combining these can also be used. For example, those having a shape in which thin metal plating is formed on a polyimide film, those having conductivity by kneading carbon into a polymer, and those having a metal plate coated with an organic insulating polymer can be exemplified. Further, it is not limited that various surface treatments are performed in the same manner as in the above (A).

(C) is an adhesive layer mainly used for bonding (A) and (B). However, the use of (A) or (B) for bonding to another member (for example, an IC or a printed board) is not limited at all. This adhesive layer is usually laminated in a semi-cured state on the semiconductor integrated circuit connection substrate, and before or after lamination, 30 to 20 times.
The degree of curing can be adjusted by performing a pre-curing reaction at a temperature of 0 ° C. for an appropriate time. The thickness of the adhesive layer can be appropriately selected depending on properties such as adhesive strength, thermal and thermal stress relaxation effect, and workability, but is preferably 2 to 500 μm, more preferably 20 to 200 μm.

The adhesive composition constituting the adhesive layer must contain at least one or more resins each containing a urethane bond and / or a urea bond in the main chain and at least one thermosetting resin. Is not particularly limited. Also,
Mixing other thermoplastic resins appropriately is not limited at all.

The resin containing a urethane bond and / or a urea bond in the main chain has adhesiveness, flexibility, relaxation of thermal stress,
It has the function of improving insulation due to low water absorption, and thermosetting resin is necessary to achieve the balance of physical properties such as heat resistance, insulation at high temperature, chemical resistance, strength of adhesive layer, etc. is there.

In the present invention, the main chain has a urethane bond and / or
Or, a resin containing a urea bond means that the main chain mainly comprises a urethane bond and / or a urea bond.
The structure of other parts is not particularly limited, but polyurethane,
Examples thereof include polyurea and a polyurethane-polyurea copolymer.

These resins may have a functional group capable of reacting with a thermosetting resin described below. Specific examples include an amino group, a carboxyl group, an epoxy group, a hydroxyl group, a methylol group, an isocyanate group, a vinyl group, and a silanol group. These functional groups are preferable because the bond with the thermosetting resin is strengthened and the heat resistance is improved.

Further, it is preferable that these resins are soluble in a solvent, since the adhesive composition can be formed into an adhesive layer having a uniform composition and a uniform thickness by coating. In this case, the solubility at 25 ° C. is preferably 5% by weight or more, more preferably 10% by weight or more. If it is less than 5% by weight, it is difficult to obtain an adhesive layer having a substantially appropriate thickness,
Not preferred. Although the solvent is not particularly limited, an organic solvent having a boiling point of 60 to 250 ° C is preferable in consideration of drying of the solvent in coating.

Among the resins exemplified above, polyurethane resins in which the main chains are all urethane bonds or polyurea resins in which the main chains are all urea bonds are flexible and adhesive.
It is particularly preferable because of its excellent heat resistance.

Examples of the thermosetting resin include known resins such as an epoxy resin, a phenol resin, a melamine resin, a xylene resin, a furan resin and a cyanate ester resin. Particularly, epoxy resin and phenol resin are preferable because of their excellent insulating properties.

The epoxy resin is not particularly limited as long as it has two or more epoxy groups in one molecule, but is not limited to bisphenol F, bisphenol A, bisphenol S,
Diglycidyl ethers such as resorcinol, dihydroxynaphthalene, dicyclopentadiene diphenol, epoxidized phenol novolak, epoxidized cresol novolak, epoxidized trisphenylolmethane, epoxidized tetraphenylolethane, epoxidized metaxylenediamine, cyclohexane epoxide, etc. Alicyclic epoxy, and the like. Further, it is effective to use a halogenated epoxy resin, particularly a brominated epoxy resin, for imparting flame retardancy. At this time, although the use of only the brominated epoxy resin can impart flame retardancy, the heat resistance of the adhesive is greatly reduced, so that it is more effective to use a mixed system with a non-brominated epoxy resin. Examples of the brominated epoxy resin include a copolymerized epoxy resin of tetrabromobisphenol A and bisphenol A, or "BR
EN "-S (manufactured by Nippon Kayaku Co., Ltd.) and the like. These brominated epoxy resins are used in combination of two or more kinds in consideration of bromine content and epoxy equivalent. May be.

As the phenol resin, any known phenol resin such as a novolak type phenol resin and a resol type phenol resin can be used. For example, alkyl-substituted phenols such as phenol, cresol, pt-butylphenol, nonylphenol, and p-phenylphenol; cyclic alkyl-modified phenols such as terpene and dicyclopentadiene; and heterocycles such as nitro, halogen, cyano, and amino groups. Those having a functional group containing atoms, naphthalene, those having a skeleton such as anthracene,
Examples of resins include polyfunctional phenols such as bisphenol F, bisphenol A, bisphenol S, resorcinol, and pyrogallol.

The addition amount of the thermosetting resin is 5 to 400 parts by weight, preferably 50 to 200 parts by weight, based on 100 parts by weight of the resin components other than the thermosetting resin. When the addition amount of the thermosetting resin is less than 5 parts by weight, the elastic modulus at a high temperature is remarkably reduced, and the semiconductor integrated circuit connection substrate is deformed during use of the device on which the semiconductor device is mounted, and is handled in a processing step. This is not preferable because of lack of workability. If the addition amount of the thermosetting resin exceeds 400 parts by weight, the modulus of elasticity is high, the coefficient of linear expansion is small, and the effect of relaxing thermal stress is small.

The addition of a curing agent and a curing accelerator for epoxy resin and phenolic resin to the adhesive composition constituting the adhesive layer is not limited at all. For example, 3,
3'5,5'-tetramethyl-4,4'-diaminodiphenylmethane, 3,3'5,5'-tetraethyl-4,
4'-diaminodiphenylmethane, 3,3'-dimethyl-5,5'-diethyl-4,4'-diaminodiphenylmethane, 3,3'-dichloro-4,4'-diaminodiphenylmethane, 2,2'3,3 '-Tetrachloro-4,
4'-diaminodiphenylmethane, 4,4'-diaminodiphenyl sulfide, 3,3'-diaminobenzophenone, 3,3'-diaminodiphenyl sulfone, 4,4
Aromatic polyamines such as' -diaminodiphenylsulfone, 3,4'-diaminodiphenylsulfone, 4,4'-diaminobenzophenone, and 3,4,4'-triaminodiphenylsulfone; and trifluorinated compounds such as boron trifluoride triethylamine complex. Amine complex of boron halide, 2-alkyl-4
Known compounds such as imidazole derivatives such as -methylimidazole and 2-phenyl-4-alkylimidazole, organic acids such as phthalic anhydride and trimellitic anhydride, dicyandiamide and triphenylphosphine can be used. These may be used alone or in combination of two or more. The addition amount is preferably 0.1 to 50 parts by weight based on 100 parts by weight of the adhesive composition constituting the adhesive layer.

In addition to the above components, addition of organic or inorganic components such as an antioxidant and an ion scavenger is not limited as long as the properties of the adhesive are not impaired. Examples of fine inorganic components include aluminum hydroxide, magnesium hydroxide, metal hydroxides such as calcium aluminate hydrate, silica, alumina, zirconium oxide, zinc oxide, antimony trioxide, antimony pentoxide, and magnesium oxide. Titanium oxide, iron oxide, cobalt oxide, chromium oxide, metal oxides such as talc, inorganic salts such as calcium carbonate, aluminum, gold, silver, nickel, iron, metal fine particles such as, or carbon black, glass, Examples of the organic component include crosslinked polymers such as styrene, NBR rubber, acrylic rubber, polyamide, polyimide, and silicone. These may be used alone or in combination of two or more. The average particle diameter of the fine particle component is preferably 0.2 to 5 μ in consideration of dispersion stability. The compounding amount is from 2 to 5 of the entire adhesive composition constituting the adhesive layer.
0 parts by weight is suitable.

The components (hereinafter, referred to as components) of the substrate for connecting a semiconductor integrated circuit of the present invention are materials in an intermediate processing stage used for producing the substrate for connecting a semiconductor integrated circuit and a semiconductor device. The component has (A) at least one wiring board layer composed of an insulator layer and a conductor pattern and (C ′) at least one adhesive layer having a protective layer, or (B) no conductor pattern is formed. And (C ′) an adhesive layer having at least one adhesive layer having a protective layer, and the adhesive composition constituting the (C ′) adhesive layer has a urethane bond and / or a main chain as an essential component. It is essential to include at least one kind of resin containing a urea bond and at least one kind of thermosetting resin, respectively, but other configurations and structures are not particularly limited. For example, (A) a flexible printed board or TAB is used as a wiring board layer composed of an insulator layer and a conductor pattern.
A wiring board with an adhesive and a conductor pattern (B) are formed by laminating an uncured or semi-cured adhesive layer having a (C ') silicone release-treated polyester protective film on one or both surfaces thereof using a tape. Metal plate made of copper, stainless steel, 42 alloy, or the like, and an uncured or semi-cured adhesive layer having a protective film similar to the above on one or both surfaces of the metal plate (adhesive) Stiffener) corresponds to the component of the present invention. Even when (A) a wiring board layer composed of an insulator layer and a conductor pattern and (B) one or more layers each having no conductor pattern formed thereon, uncured or semi-cured having a protective film on the outermost layer. The so-called adhesive-attached semiconductor integrated circuit connecting substrate in which the state adhesive layer is laminated is also included in the component of the present invention.

The protective film layer here is not particularly limited as long as it can be peeled off before the adhesive layer is adhered without impairing its function and form. Examples thereof include polyester, polyolefin, polyphenylene sulfide, polyvinyl chloride, and polytetrafluoroethylene. Plastic film of ethylene, polyvinylidene fluoride, polyvinyl fluoride, polyvinyl butyral, polyvinyl acetate, polyvinyl alcohol, polycarbonate, polyamide, polyimide, polymethyl methacrylate, etc., and coating treatment of these with release agent such as silicone or fluorine compound. Applied films, paper laminated with these films, paper impregnated or coated with a resin having releasability, and the like.

The peel strength of the protective film layer is preferably 1
２００200 N m ⁻¹ , more preferably 3 to 100 N m
It is ^-1 . When it is lower than 1 N m ^-1 , the protective film layer is apt to fall off, and when it exceeds 200 N m ^-1 , the protective film layer is hardly peeled off, and in both cases, the workability is undesirably reduced.

The semiconductor device according to the present invention is a device using the substrate for connecting a semiconductor integrated circuit according to the present invention.
The shape and structure are not particularly limited as long as they are A type, LGA type, and PGA type packages. The connection method between the semiconductor integrated circuit connection substrate and the IC includes gang bonding and single point bonding of TAB method, wire bonding used for a lead frame, resin sealing by flip chip mounting, anisotropic conductive film (adhesive). Any of connection and the like may be used. Further, a package called a CSP is also included in the semiconductor device of the present invention.

Next, a description will be given of an example of a semiconductor integrated circuit connecting substrate, components constituting the same and a method of manufacturing a semiconductor device according to the present invention.

(1) Preparation of a wiring board layer (A) composed of an insulator layer and a conductor pattern:
T with a three-layer structure in which an adhesive layer and a protective film layer are laminated
The AB tape is processed by the following steps (a) to (d). (A) perforation of sprocket and device holes,
(B) thermal lamination with copper foil, (c) pattern formation (resist coating, etching, resist removal), (d) tin or gold-plating treatment. FIG. 3 shows an example of the shape of the obtained TAB tape (pattern tape).

(2) Preparation of layer (B) on which no conductor pattern is formed: A copper plate or a stainless steel (SUS304) plate having a thickness of 0.05 to 0.5 mm is degreased with acetone.

(3) Preparation of adhesive layer (C): Prepared by the following steps (a) and (b). (A) A coating obtained by dissolving the adhesive composition in a solvent is applied on a polyester film having releasability and dried. The thickness of the adhesive layer is 10
It is preferable to apply so that the thickness is 100 μm. Drying conditions are 100 to 200 ° C. for 1 to 5 minutes. The solvent is not particularly limited, but aromatic solvents such as toluene, xylene and chlorobenzene, ketones such as methyl ethyl ketone and methyl isobutyl ketone, and aprotic polar solvents such as dimethylformamide, dimethylacetamide and N-methylpyrrolidone alone or a mixture thereof are preferred. It is. (B)
An adhesive sheet is obtained by laminating a polyester or polyolefin-based protective film having a releasability with a lower peel strength than the above film on the film of (a). When the thickness of the adhesive is further increased, the adhesive sheet may be laminated plural times. After lamination, for example, 40-70 ° C
For about 20 to 200 hours to adjust the degree of curing.

(4) Preparation of a component (wiring board with adhesive) of a substrate for connecting a semiconductor integrated circuit: A protective film on one side of the adhesive sheet prepared in (3) is applied to the wiring board layer of (1). Laminate after peeling. The laminate surface may be either a surface with or without a conductor pattern. Laminating temperature 20 ~ 200 ℃, pressure 0.1 ~ 3M
Pa is preferred. Finally, depending on the shape of the semiconductor device,
Punching and cutting are performed as appropriate. FIG. 4 shows an example of the component of the present invention.

(5) Preparation of a component (stiffener with adhesive) of a substrate for connecting a semiconductor integrated circuit: after peeling off the protective film on one side of the adhesive sheet prepared in (3) above on the metal plate (2). Laminate. A lamination temperature of 20 to 200 ° C. and a pressure of 0.1 to 3 MPa are preferred.
Alternatively, the coating of (3) may be directly applied to (B) and dried, and a protective film may be laminated. Finally, punching and cutting are performed as appropriate depending on the shape of the semiconductor device. FIG. 5 shows an example of the component of the present invention.

(6) Preparation of a substrate for connecting a semiconductor integrated circuit: (a) Method using a wiring board with an adhesive The protective film of the adhesive layer is peeled off from the component (wiring board with an adhesive) in (4), and an appropriate method is used. Glue to a metal plate punched into shape. As the metal plate, for example, a metal plate having a square shape and punched into a shape having a square hole in accordance with the device hole of the wiring board in the center can be exemplified. The bonding conditions are preferably a temperature of 20 to 200 ° C. and a pressure of 0.1 to 3 MPa. Finally, post-curing is performed in a hot-air oven at 80 to 200 ° C. for about 15 to 180 minutes for heat curing of the adhesive.

(B) Method using a stiffener with an adhesive The part (5) (stiffener with an adhesive) is punched out with a metal mold, and for example, a stiffener with an adhesive having a square shape and also having a square hole at the center. And The protective film is peeled off from the stiffener with the adhesive, and the center hole of the stiffener with the adhesive is made to coincide with the device hole of the wiring board on the conductor pattern surface of the wiring substrate layer or the polyimide film surface on the back surface of (1). to paste together. The bonding conditions are preferably a temperature of 20 to 200 ° C. and a pressure of 0.1 to 3 MPa. Finally, post-curing is performed in a hot-air oven at 80 to 200 ° C. for about 15 to 180 minutes for heat curing of the adhesive.

FIG. 2 shows an example of the substrate for connecting a semiconductor integrated circuit described above.

(7) Preparation of semiconductor device: The inner lead portion of the substrate for connecting a semiconductor integrated circuit of (6) is thermocompression-bonded (inner lead bonding) to a gold bump of the IC, and
With. Next, a semiconductor device is manufactured through a resin sealing step using a sealing resin. The obtained semiconductor device is connected to a printed circuit board or the like on which other components are mounted via solder balls, and mounted on an electronic device. Further, a so-called TCP type semiconductor device in which an IC is connected to the wiring board in the above (1) in advance and sealed with a resin can be used. FIG. 1 is a cross-sectional view of one embodiment of a semiconductor device of the present invention.

[0043]

EXAMPLES The present invention will be described below with reference to examples.
The present invention is not limited to these examples. Before starting the description of the embodiments, an evaluation method will be described.

Evaluation Method (1) Preparation of Evaluation Pattern Tape: An 18 μm electrolytic copper foil was laminated on a TAB adhesive tape (# 7100, manufactured by Toray Industries, Inc.) at 140 ° C. and 0.1 MPa. Then, in an air oven at 80 ° C for 3 hours, 100
The tape was heated and cured sequentially at 150 ° C. for 5 hours at 150 ° C. to prepare a TAB tape with a copper foil. A photoresist film was formed on the copper foil surface of the obtained TAB tape with copper foil, etching, and resist peeling were performed by a conventional method to prepare a pattern tape sample for evaluation.

(2) Embedding of conductor pattern and cure foaming: A pure copper plate having a thickness of 0.1 mm and having an adhesive layer made of an adhesive composition and having a thickness of 100 μm was used as a conductor of the pattern tape for evaluation of (1). 130 ° C, 0.1
After laminating under the condition of MPa, 1
Heat curing treatment was performed at 50 ° C. for 2 hours. This was immersed in an etching solution containing ferric chloride as a main component to dissolve the pure copper plate. Finally, the exposed adhesive layer was observed under a microscope to evaluate the foaming during curing and the embedding property of the conductor pattern.

(3) Peeling strength: A pure copper plate with an adhesive layer similar to that of (2) was applied to a polyimide film (“UPILEX” 75S manufactured by Ube Industries, Ltd.) at 130 ° C. and 0.1 MPa.
After laminating under the conditions of a, 150
Heat curing treatment was performed at 2 ° C. for 2 hours. The obtained polyimide film of the sample was cut so as to have a width of 2 mm, and peeled in a 90 ° direction at a speed of 50 mm / min, and the peeling force at that time was measured.

(4) Insulation reliability: Conductor width 100 μm, conductor-to-conductor distance 100 μm of the pattern tape for evaluation of (1)
On the conductor pattern surface of the sample for evaluating the comb shape,
A pure copper plate with an adhesive layer similar to that of (2) was heated at 130 ° C.
After laminating under the condition of 0.1 MPa, a heat curing treatment was performed in an air oven at 150 ° C. for 2 hours. Using the obtained sample, in a state where a voltage of 100 V was continuously applied in a constant temperature and humidity chamber of 85 ° C. and 85% RH, the resistance value was measured immediately after the measurement and after 200 hours.

(5) Solder heat resistance: A 30 mm square sample prepared by the above method (3) was conditioned for 48 hours in an atmosphere of 85 ° C. and 85% RH, and immediately placed on a solder bath for 60 seconds. The highest temperature without floating, swelling and peeling was measured.

(6) Reflow test of semiconductor device: thickness 1
The FR-4 glass epoxy copper-clad substrate having a thickness of 1 mm was etched according to a conventional method to form a solder ball connection pattern having a pitch of 1 mm. This was coated with cream solder, and a BGA type semiconductor device sample prepared in the following example was prepared.
After conditioning for 48 hours in an atmosphere of 5 ° C. and 85% RH, the film was immediately passed through a reflow furnace under a reflow condition of a maximum temperature of 230 ° C. for 10 seconds, and then the occurrence of swelling and peeling was evaluated.

(7) Heat cycle test: A 30 mm square sample prepared by the above method (3) was placed in a heat cycle tester (PL-3 type, manufactured by Tabai Espec Co., Ltd.) at -20.
600 cycles of treatment were carried out at a temperature of 1 to 100 ° C and a minimum and maximum temperature of 1 hour each, and the occurrence of peeling was evaluated.

(8) Thermal cycle test of a semiconductor device: A 1 mm thick FR-4 glass epoxy copper-clad substrate was etched according to a conventional method to form a solder ball connection pattern having a pitch of 1 mm. Apply cream solder to this,
A sample for a thermal cycle test was prepared by mounting a BGA type semiconductor device sample prepared in an example described later under a reflow condition of 230 ° C. This is converted to 60 under the same conditions as in (7).
After 0 cycles, the occurrence of cracks in the solder balls was evaluated.

Example 1 Aluminum hydroxide (H-42I, manufactured by Showa Denko KK)
Was mixed with methyl ethyl ketone, followed by sand milling to prepare an aluminum hydroxide dispersion. To this dispersion, a polyurethane resin (manufactured by Nippon Polyurethane, Coronate L), a butadiene / acrylonitrile / acrylic acid copolymer (manufactured by Nippon Synthetic Rubber Co., Ltd., PNR-1H), and an epoxy resin (manufactured by Yuka Shell Epoxy Co., Ltd.) , "Epicoat" 828, epoxy equivalent 186), 4,4'-diaminodiphenylsulfone were added so as to have the composition ratios shown in Table 1, and stirred and mixed at 40 ° C to prepare an adhesive solution. This adhesive solution was applied by a bar coater to a 25 μm thick polyethylene terephthalate film (peel force F ₁ ) with a silicone release agent to a dry thickness of about 20 μm, and dried at 170 ° C. for 5 minutes. On the other hand, except that a 25 μm thick polyethylene terephthalate film (peeling force F ₂ ) with a silicone release agent having a low release force was used, an adhesive layer was formed to a dry thickness of about 50 μ by the same method as described above. did. Next, these were laminated together with the adhesive surfaces together to prepare an adhesive sheet for a semiconductor device of the present invention having an adhesive thickness of 40 μm. FIG. 6 shows the configuration. This adhesive sheet is placed on a pure copper plate having a thickness of 0.1 mm at 100 ° C. for 0.1
Lamination was performed under the conditions of MPa to obtain a pure copper plate with an adhesive layer. Table 2 shows the characteristics.

The pure copper plate with the adhesive layer obtained by the above procedure was punched into a shape having a 30 mm square outer shape and a 20 mm square hole at the center, and was used as a component of a semiconductor integrated circuit connecting substrate (stiffener with an adhesive). It was created.

On the other hand, a pattern tape (wiring board layer) shown in FIG. 3 was prepared in the same manner as in the above evaluation method (1). However, a photosensitive solder resist (“Probimer” 71, manufactured by Ciba Geigy) is applied to the conductive pattern surface, dried, exposed with a photomask, developed, and heat-cured to form a pad for solder ball connection (solder ball pitch 1.0 m).
m) The resist was removed above. Then, the stiffener with the adhesive was aligned at 130 ° C. and 0.1 MPa so that the holes corresponded to the device holes of the pattern tape.
After thermocompression bonding to the surface opposite to the conductor pattern under the conditions of the above, heat curing treatment is performed in an air oven at 150 ° C for 2 hours,
A substrate for connecting a semiconductor integrated circuit was prepared.

Further, inner lead bonding was performed on the inner lead portion of the substrate for connecting a semiconductor integrated circuit at 450 ° C. for 1 minute to connect the semiconductor integrated circuit. Next, resin sealing was performed with an epoxy-based liquid sealing agent (“Chipcoat” 1320-617, manufactured by Hokuriku Paint Co., Ltd.). After solder cream printing on the pad for solder ball connection, solder ball of 0.3mm diameter (Tanaka Electronics Industries
(Manufactured by Co., Ltd.) and heated in a reflow furnace at 260 ° C. to obtain a semiconductor device. FIG. 1 shows a cross section of the obtained semiconductor device. Table 2 shows the characteristics.

Example 2 Spherical silica ("Excelica", manufactured by Tokuyama Corporation) was mixed with methyl ethyl ketone, followed by sand milling to prepare a silica dispersion. To this, a polyurethane resin (“PANDEX” T-520, manufactured by Dainippon Ink and Chemicals, Inc.)
1), butadiene / acrylonitrile / acrylic acid copolymer ("Nipol" 1072, manufactured by Zeon Corporation)
J), epoxy resin (manufactured by Yuka Shell Epoxy Co., Ltd.)
"Epicoat" 828, epoxy equivalent 186), 4,
4 ′ diaminodiphenyl sulfone was added so as to have a composition ratio shown in Table 1, respectively, and stirred and mixed at 40 ° C. to prepare an adhesive solution. Using this adhesive solution, components of a substrate for connecting a semiconductor integrated circuit (a stiffener with an adhesive) and a substrate for connecting a semiconductor integrated circuit were obtained in the same manner as in Example 1.
Table 2 shows the characteristics.

Example 3 Aluminum hydroxide (H-42I, manufactured by Showa Denko KK)
Was mixed with toluene, followed by sand milling to prepare an aluminum hydroxide dispersion. On the other hand, 4,4′-diphenylmethane diisocyanate and isophoronediamine were added to toluene so that the molar ratio of isocyanate groups / amino groups was 1/1, and reacted at 30 ° C. for 8 hours to prepare a polyurea solution. A polyurea solution, a butadiene / acrylonitrile / acrylic acid copolymer (PNR-1H, manufactured by Nippon Synthetic Rubber Co., Ltd.), a brominated epoxy resin (manufactured by Yuka Shell Co., Ltd., Epicoat, "5050, bromine content 49%, epoxy equivalent 395), epoxy resin (" Epicoat "82, manufactured by Yuka Shell Epoxy Co., Ltd.)
8, epoxy equivalent 186), resole type phenol resin (PL2607, manufactured by Gun Ei Chemical Co., Ltd.), and 4,4′-diaminodiphenyl sulfone in a mixture of methyl ethyl ketone / toluene = 1/1 so as to have a composition ratio shown in Table 1. In addition to the solvent, the mixture was stirred and mixed at 40 ° C. to prepare an adhesive solution. Next, an adhesive sheet was prepared from this adhesive solution in the same manner as in Example 1. This adhesive sheet was applied to a pattern tape (wiring board layer) prepared in the same manner as in Example 1 at 80 ° C. and 0.1 MPa in the same procedure as in Example 1.
Under the condition of a, thermocompression bonding was performed on the surface opposite to the conductor pattern. Further, the adhesive layer sheet with the protective film was punched out in accordance with the device holes or the like of the wiring substrate layer to obtain a component (wiring substrate with adhesive) of a substrate for connecting a semiconductor integrated circuit.

On the other hand, a pure copper plate having a thickness of 0.1 mm
A 20 mm square hole was punched out in the center of a square mm to form a stiffener. This was aligned with the adhesive-attached wiring board so that the holes of the stiffener corresponded to the device holes of the pattern tape.
Thermocompression bonding was performed on the surface opposite to the conductor pattern under the condition of 0.1 MPa. Finally, a heat curing treatment was performed at 150 ° C. for 2 hours in an air oven to prepare a semiconductor integrated circuit connection substrate. Table 2 shows the characteristics.

Comparative Example 1 Aluminum hydroxide (H-42I, manufactured by Showa Denko KK)
Was mixed with toluene, followed by sand milling to prepare an aluminum hydroxide dispersion. NBR-
C (manufactured by Nippon Synthetic Rubber Co., Ltd., PNR-1H) and a dispersion were added to each of the same proportions of methyl ethyl ketone so as to have the composition ratio shown in Table 1, followed by stirring and mixing at 30 ° C. to prepare an adhesive solution. Using this adhesive solution, components of a substrate for connecting a semiconductor integrated circuit (a stiffener with an adhesive) and a substrate for connecting a semiconductor integrated circuit were obtained in the same manner as in Example 1.
Table 2 shows the characteristics.

Comparative Example 2 Aluminum hydroxide (H-42I, manufactured by Showa Denko KK)
Was mixed with toluene, followed by sand milling to prepare an aluminum hydroxide dispersion. A phenol novolak resin (manufactured by Gunei Chemical Industry Co., Ltd., PSM42) was added to this dispersion.
61), hexamethylenetetramine and methyl ethyl ketone of the same weight as the dispersion were added so as to have the composition ratios shown in Table 1, respectively, and stirred and mixed at 30 ° C. to prepare an adhesive solution. Using this adhesive solution, components of a substrate for connecting a semiconductor integrated circuit (a stiffener with an adhesive) and a substrate for connecting a semiconductor integrated circuit were obtained in the same manner as in Example 1. Table 2 shows the characteristics.

[0061]

[Table 1]

[0062]

[Table 2]

From the examples and comparative examples in Tables 1 and 2, it can be seen that the substrate for connecting a semiconductor integrated circuit obtained by the present invention is excellent in adhesive strength, insulation reliability and durability.

[0064]

The present invention is to provide a novel substrate for connecting a semiconductor integrated circuit which is excellent in processability, adhesive strength, insulation reliability and durability, components constituting the same, and a semiconductor device, which are industrially provided. The substrate for connecting a semiconductor integrated circuit according to the present invention can improve the economic efficiency based on the reliability and the ease of processing of a semiconductor device for high-density mounting.

[Brief description of the drawings]

FIG. 1 shows B using a semiconductor integrated circuit connection substrate of the present invention.
FIG. 4 is a cross-sectional view of one embodiment of a GA semiconductor device.

FIG. 2 is a cross-sectional view of one embodiment of a substrate for connecting a semiconductor integrated circuit of the present invention.

FIG. 3 is a perspective view of one embodiment of a pattern tape (TAB tape) constituting a substrate for connecting a semiconductor integrated circuit according to the present invention.

FIG. 4 is a cross-sectional view of one embodiment of a component (wiring substrate with an adhesive) of the substrate for connecting a semiconductor integrated circuit according to the present invention.

FIG. 5 is a cross-sectional view of one embodiment of a component (a stiffener with an adhesive) of a substrate for connecting a semiconductor integrated circuit according to the present invention.

FIG. 6 is a cross-sectional view of one embodiment of the adhesive sheet for a semiconductor device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Gold bump 3,11,17 Flexible insulating film 4,12,18 Adhesive layer which comprises a wiring board layer 5,13,21 Conductor for connecting a semiconductor integrated circuit 6,14, 23 Adhesive layer composed of the adhesive composition of the present invention 7, 15 Layer on which no conductor pattern is formed 8, 16 Solder resist 9 Solder ball 10 Sealing resin 19 Sprocket hole 20 Device hole 22 Solder ball connection Conductor

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁶ Identification code FI C09J 161/06 C09J 161/06 163/00 163/00 175/04 175/04 201/00 201/00 H01L 23/12 H01L 23 / 12 Z

Claims (16)

[Claims] 1. A semiconductor integrated circuit connection comprising (A) a wiring board layer comprising an insulator layer and a conductor pattern, (B) at least one layer having no conductor pattern and (C) an adhesive layer. A substrate, wherein (C) the adhesive composition constituting the adhesive layer contains, as essential components, at least one or more resins each containing a urethane bond and / or a urea bond in the main chain and a thermosetting resin. Substrate for connecting a semiconductor integrated circuit. 2. The substrate for connecting a semiconductor integrated circuit according to claim 1, wherein the resin having a urethane bond and / or a urea bond in the main chain is polyurethane. 3. The substrate for connecting a semiconductor integrated circuit according to claim 1, wherein the resin containing a urethane bond and / or a urea bond in the main chain is polyurea. 4. The semiconductor according to claim 1, wherein the resin containing a urethane bond and / or a urea bond in the main chain is soluble in a solvent and has a solubility at 25 ° C. of 5% by weight or more. Substrate for connecting integrated circuits. 5. The substrate according to claim 1, wherein the thermosetting resin is an epoxy resin and / or a phenol resin. 6. The method according to claim 1, wherein the insulating layer constituting the wiring board layer comprising the insulating layer and the conductor pattern comprises at least one or more polyimide films, and the conductor pattern contains copper. The substrate for connecting a semiconductor integrated circuit according to claim 1. 7. A semiconductor device using the substrate for connecting a semiconductor integrated circuit according to claim 1. 8. A component of a substrate for connecting a semiconductor integrated circuit having at least one each of (A) a wiring board layer comprising an insulator layer and a conductor pattern and (C ′) an adhesive layer having a protective film layer. And (C ′) a semiconductor characterized in that the adhesive composition constituting the adhesive layer contains, as essential components, at least one or more resins each having a urethane bond and / or a urea bond in the main chain and a thermosetting resin. Parts of integrated circuit connection board. 9. A component of a substrate for connecting a semiconductor integrated circuit, comprising: (B) at least one layer having no conductive pattern and (C ′) at least one adhesive layer having a protective layer, wherein (C ′) The adhesive composition constituting the adhesive layer comprises at least one resin having a urethane bond and / or a urea bond in the main chain and a thermosetting resin as essential components.
A component of a substrate for connecting a semiconductor integrated circuit, wherein the component includes at least one kind. 10. A resin containing a urethane bond and / or a urea bond in the main chain of the adhesive composition constituting the adhesive layer,
10. Polyurethane is a polyurethane.
Parts of the substrate for connecting a semiconductor integrated circuit according to the above. 11. A resin having a urethane bond and / or a urea bond in the main chain of the adhesive composition constituting the adhesive layer,
The component of the substrate for connecting a semiconductor integrated circuit according to claim 8, wherein the component is polyurea. 12. A resin having a urethane bond and / or a urea bond in the main chain of the adhesive composition constituting the adhesive layer is soluble in a solvent and has a solubility at 25 ° C. of 5 or less.
10. The component of the substrate for connecting a semiconductor integrated circuit according to claim 8, wherein the component is not less than% by weight. 13. The component for a substrate for connecting a semiconductor integrated circuit according to claim 8, wherein the adhesive composition constituting the adhesive layer contains an epoxy resin and / or a phenol resin. (A) The insulating layer constituting the wiring board layer comprising the insulating layer and the conductor pattern is made of at least one or more polyimide films, and the conductor pattern contains copper. The component of the substrate for connecting a semiconductor integrated circuit according to claim 8. 15. The component of the substrate for connecting a semiconductor integrated circuit according to claim 9, wherein (B) the layer on which the conductor pattern is not formed is a metal plate. (C ') The protective film layer of the adhesive layer is
10. The component of the substrate for connecting a semiconductor integrated circuit according to claim 8, wherein the component is an organic film subjected to a release treatment.