JPH10151883A - Ic card - Google Patents

Ic card

Info

Publication number
JPH10151883A
JPH10151883A JP8312194A JP31219496A JPH10151883A JP H10151883 A JPH10151883 A JP H10151883A JP 8312194 A JP8312194 A JP 8312194A JP 31219496 A JP31219496 A JP 31219496A JP H10151883 A JPH10151883 A JP H10151883A
Authority
JP
Japan
Prior art keywords
chip
card
circuit pattern
substrate
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8312194A
Other languages
Japanese (ja)
Inventor
Ryuzo Fukao
隆三 深尾
Toshiaki Ochiai
利明 落合
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxell Holdings Ltd
Original Assignee
Hitachi Maxell Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Maxell Ltd filed Critical Hitachi Maxell Ltd
Priority to JP8312194A priority Critical patent/JPH10151883A/en
Publication of JPH10151883A publication Critical patent/JPH10151883A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an IC card having excellent durability and reliability in a reduced thickness. SOLUTION: A bump 21 of an IC chip 4 is connected by wire bonding to a terminal 3a of a circuit pattern 3 mounted on a board 1. Wire bonding is conducted from a first bond to the terminal 3a of the pattern 3 and from a second bond to a bump 21 of the chip 4. Thus, a riser 6a rising substantially in a normal direction X-X of a circuit pattern forming surface of the board from the terminal of the pattern, a bent part 6b at about 90 degrees of a bending angle θ, and a parallel part 6c extended substantially parallel to the pattern forming surface are formed. After wire bonding, the wire and its periphery are fixed with molding resin 7, the chip mounting surface of the board is covered with hot-melt package resin 8, and further a PET film is laminated as a cover sheet 9 on the surface.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、基板上に搭載され
たベアＩＣチップの端子部と基板表面に形成された回路
パターンの端子部とをボンディングワイヤを介して接続
するＩＣカードに係り、特に、前記ボンディングワイヤ
の配線構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card for connecting terminals of a bare IC chip mounted on a substrate and terminals of a circuit pattern formed on the surface of the substrate through bonding wires, and more particularly to an IC card. And a wiring structure of the bonding wire.

【０００２】[0002]

【従来の技術】従来より、基板上にベアＩＣチップを搭
載して成り、情報の記憶やリーダ・ライタとの間の情報
のやり取りとを行うＩＣカードが種々提案されている。
この種のＩＣカードは、例えば預金情報、保険情報、医
療情報、定期券情報、運転免許証情報、身分証明情報等
の個人情報の記憶や、工場における製品管理情報や商品
流通業界における商品管理情報等の産業情報の記憶等に
使用されるか、あるいは使用が検討されている。2. Description of the Related Art Hitherto, various IC cards have been proposed in which a bare IC chip is mounted on a substrate to store information and exchange information with a reader / writer.
This type of IC card stores personal information such as deposit information, insurance information, medical information, commuter pass information, driver's license information, identification information, etc., product management information in factories, and product management information in the product distribution industry. It is used for storage of industrial information such as, or the use is being studied.

【０００３】従来、この種のＩＣカードにおけるＩＣチ
ップの端子部と基板上に形成された回路パターンの端子
部との接続方式としては、フェースアップ方式でＩＣチ
ップを基板上に取り付けるタイプのＩＣカードについて
はワイヤボンディング接続、フェースダウン方式でＩＣ
チップを基板上に取り付けるタイプのＩＣカードについ
ては導電ペーストや異方導電性フィルム等を用いた直接
接続が一般に採用されている。Conventionally, as a method of connecting the terminal portion of the IC chip in this type of IC card to the terminal portion of the circuit pattern formed on the substrate, an IC card of a type in which the IC chip is mounted on the substrate in a face-up system. About wire bonding connection, face down IC
For an IC card in which a chip is mounted on a substrate, direct connection using a conductive paste or an anisotropic conductive film is generally employed.

【０００４】図２は、ワイヤボンディング接続によりＩ
Ｃチップの端子部と回路パターンの端子部とが接続され
た従来のＩＣカードの一例を示す要部拡大断面図であっ
て、１はＩＣカード、２は基板、３は基板２の表面に形
成された回路パターン、４はＩＣチップ、５はＩＣチッ
プ４を基板２上に固定するダイボンディング、６はボン
ディングワイヤ、７はボンディングワイヤ６及びその周
辺部を固定するモールド樹脂、８は基板２のＩＣチップ
搭載面（回路パターン形成面）を覆うパッケージ樹脂、
９はパッケージ樹脂８の表面に被着されたカバーシート
を示している。この図から明らかなように、ボンディン
グワイヤ６の側面形状（基板の断面方向からボンディン
グワイヤ６の延長方向に沿って見たときの形状）は、ル
ープ状に湾曲した形状になるが、必ずしも曲率半径が一
定の円弧状には成らず、その一部に他の部分とは明らか
に曲率半径が異なる屈曲部１０が生じる。そして、従来
のこの種のＩＣカードにおいては、図２に示すように、
屈曲部１０がＩＣチップ４の端子部４ａ側に偏った位置
に形成され、しかもその屈曲角度θが鋭角になってい
る。[0004] FIG.
FIG. 2 is an enlarged cross-sectional view of an essential part showing an example of a conventional IC card in which a terminal portion of a C chip and a terminal portion of a circuit pattern are connected, wherein 1 is an IC card, 2 is a substrate, and 3 is formed on the surface of the substrate 2. 4 is an IC chip, 5 is die bonding for fixing the IC chip 4 on the substrate 2, 6 is a bonding wire, 7 is a molding resin for fixing the bonding wire 6 and its peripheral portion, and 8 is a A package resin covering an IC chip mounting surface (circuit pattern forming surface);
Reference numeral 9 denotes a cover sheet adhered to the surface of the package resin 8. As is clear from this figure, the side surface shape of the bonding wire 6 (the shape when viewed from the cross-sectional direction of the substrate along the extending direction of the bonding wire 6) is a shape curved in a loop, but not necessarily a radius of curvature. Are not formed in a constant arc shape, and a bent portion 10 having a clearly different radius of curvature from other portions occurs in a part thereof. And in this type of conventional IC card, as shown in FIG.
The bent portion 10 is formed at a position deviated toward the terminal portion 4a of the IC chip 4, and the bending angle θ is an acute angle.

【０００５】図３は、導電ペーストを用いた直接接続に
よりＩＣチップの端子部と回路パターンの端子部とが接
続された従来のＩＣカードの他の例を示す断面図であっ
て、ＩＣチップ４の端子部４ａに形成された二段バンプ
１１が、導電ペースト１２を介して基板２上に形成され
た回路パターン３と電気的に接続されており、ＩＣチッ
プ４の下面と基板２とが接着剤１３により接着されてい
る。その他、前出の図２と共通する部分については、対
応する部分に同一の符号を表示して、説明を省略する。FIG. 3 is a cross-sectional view showing another example of a conventional IC card in which terminals of an IC chip and terminals of a circuit pattern are connected by direct connection using a conductive paste. Is electrically connected to the circuit pattern 3 formed on the substrate 2 via the conductive paste 12 so that the lower surface of the IC chip 4 and the substrate 2 are bonded to each other. It is adhered by the agent 13. In addition, the same parts as those in FIG. 2 described above are denoted by the same reference numerals, and description thereof is omitted.

【０００６】[0006]

【発明が解決しようとする課題】ワイヤボンディングは
確立された技術であり、精度及び接合強度が高い点で信
頼性に優れるが、前記したように、ＩＣチップ４の端子
部４ａと回路パターン３の端子部３ａとをワイヤボンデ
ィングするためには、ボンディングワイヤ６を基板面か
ら見て上向きに湾曲させなくてはならないので、屈曲部
１０がＩＣチップ４の端子部４ａ側に偏った位置に形成
されされると必然的にＩＣチップの上面からのボンディ
ングワイヤ６の突出高さが大きくなる。このため、従来
方式のワイヤボンディングは、薄形のＩＣカードに適用
することが難しい。また、前記したように、従来技術に
よると屈曲部１０が鋭角状に曲折されていることから、
該部に応力集中を生じやすく、該部が破断しやすいた
め、曲げに強いフレキシブルなＩＣカードを作製する上
で不利であった。The wire bonding is an established technology, and is excellent in reliability because of its high accuracy and high bonding strength. However, as described above, the wire bonding between the terminal portion 4a of the IC chip 4 and the circuit pattern 3 is performed. In order to perform wire bonding with the terminal portion 3a, the bonding wire 6 must be curved upward when viewed from the substrate surface. Therefore, the bent portion 10 is formed at a position biased toward the terminal portion 4a of the IC chip 4. As a result, the protruding height of the bonding wires 6 from the upper surface of the IC chip necessarily increases. For this reason, it is difficult to apply the conventional wire bonding to a thin IC card. Further, as described above, according to the related art, since the bent portion 10 is bent at an acute angle,
Since stress concentration easily occurs in the portion and the portion is easily broken, this is disadvantageous in producing a flexible IC card that is resistant to bending.

【０００７】一方、導電ペースト等を用いた直接接続
は、カードの薄形化に適した工法であるが、その反面、
接続の安定性及び接続部の強度の点でワイヤボンディン
グに劣っており、長期信頼性を必要とするＩＣカードに
は必ずしも適していないという問題がある。On the other hand, direct connection using a conductive paste or the like is a method suitable for reducing the thickness of a card.
There is a problem that wire bonding is inferior in terms of connection stability and connection portion strength, and is not necessarily suitable for IC cards requiring long-term reliability.

【０００８】本発明は、かかる課題を解決するためにな
されたものであって、その目的は、薄形にして耐久性及
び信頼性に優れたＩＣカードを提供することにある。The present invention has been made to solve such a problem, and an object of the present invention is to provide an IC card which is thin and has excellent durability and reliability.

【０００９】[0009]

【課題を解決するための手段】本発明は、前記課題を解
決するため、基板と当該基板上に搭載されるＩＣチップ
とを有し、前記基板に形成された回路パターンの端子部
と前記ＩＣチップの端子部とをボンディングワイヤを介
して接続してなるＩＣカードにおいて、前記ボンディン
グワイヤの側面形状（基板の断面方向からボンディング
ワイヤの延長方向に沿って見たときの形状）を、その一
部に他の部分とは明らかに曲率半径が異なる屈曲部を有
する形状とし、その屈曲部を、前記回路パターンの端子
部側に偏った位置に形成するという構成にした。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention has a substrate and an IC chip mounted on the substrate, and includes a terminal portion of a circuit pattern formed on the substrate and the IC. In an IC card in which a terminal portion of a chip is connected via a bonding wire, a part of a side shape of the bonding wire (a shape when viewed from a cross-sectional direction of the substrate along an extending direction of the bonding wire) is partially included. In this configuration, a bent portion having a clearly different radius of curvature from the other portions is formed, and the bent portion is formed at a position biased toward the terminal portion of the circuit pattern.

【００１０】例えば、本手段におけるボンディングワイ
ヤ６は、図１に示すように、回路パターン３の端子部３
ａから基板２の回路パターン形成面の法線方向Ｘ−Ｘ又
は当該法線方向Ｘ−Ｘに対して鋭角に立ち上がる起立部
６ａと、屈曲角度θが約９０度の屈曲部６ｂと、当該屈
曲部６ｂよりＩＣチップ４の端子部４ａに向けて前記回
路パターン形成面と平行又は当該回路パターン形成面に
対して鋭角を成す方向に伸びる平行部６ｃとを有する形
状にすることができる。For example, as shown in FIG. 1, the bonding wire 6 in this means is connected to the terminal 3 of the circuit pattern 3.
a, an upright portion 6a that rises at an acute angle to the normal direction XX or the normal direction XX of the circuit pattern formation surface of the substrate 2, a bent portion 6b having a bending angle θ of about 90 degrees, and the bending A parallel portion 6c extending from the portion 6b toward the terminal portion 4a of the IC chip 4 in a direction parallel to the circuit pattern forming surface or at an acute angle with respect to the circuit pattern forming surface can be formed.

【００１１】このように、ボンディングワイヤ６の屈曲
部６ｂを回路パターン３の端子部３ａ側に偏った位置に
形成すると、屈曲部１０をＩＣチップ４の端子部４ａ側
に偏った位置に形成する場合に比べて、少なくともＩＣ
チップ４の厚さ及び当該ＩＣチップ４を基板２上に固定
するためのダイボンディング部５の厚さ分だけボンディ
ングワイヤ６の突出高さを低くすることができるので、
基板厚さを薄形化できる。また、ボンディングワイヤの
突出高さを低くできることから、屈曲部６ｂの曲げ角度
を小さくすることができ、屈曲部６ｂに作用する応力集
中を緩和することができるので、薄形にして可撓性の高
いＩＣカード１についても耐久性及び信頼性を高めるこ
とができる。As described above, when the bent portion 6b of the bonding wire 6 is formed at a position biased toward the terminal portion 3a of the circuit pattern 3, the bent portion 10 is formed at a position biased toward the terminal portion 4a of the IC chip 4. At least IC compared to the case
The protrusion height of the bonding wire 6 can be reduced by the thickness of the chip 4 and the thickness of the die bonding portion 5 for fixing the IC chip 4 on the substrate 2.
Substrate thickness can be reduced. Further, since the projecting height of the bonding wire can be reduced, the bending angle of the bent portion 6b can be reduced, and the concentration of stress acting on the bent portion 6b can be reduced. The durability and reliability of the high IC card 1 can be improved.

【００１２】ワイヤボンディング方式としては、公知に
属する任意の形式を適用することができるが、ワイヤと
端子部との接合強度が高いことから、所謂ネイルヘッド
方式のワイヤボンディングを採用することが特に好まし
い。この場合、ワイヤの先端部に加熱形成されたボール
をキャピラリにより熱圧着する第１ボンド（ボールボン
ド）を回路パターンの端子部に対して行い、ワイヤの他
端側を他方の端子部に位置付けるキャピラリの動作経路
やワイヤの線径や材質それに送給速度等を適正化するこ
とによって、ワイヤの側面形状を前記のように調整でき
る。ＩＣチップの端子部においては、ボンディングワイ
ヤの他端側がキャピラリによって第２ボンドされ、接合
端が切断される。As the wire bonding method, any type known in the art can be applied. However, it is particularly preferable to use a so-called nail head type wire bonding because the bonding strength between the wire and the terminal portion is high. . In this case, a first bond (ball bond) for thermocompression bonding a ball formed at the tip of the wire by a capillary is performed on the terminal portion of the circuit pattern, and the other end of the wire is positioned on the other terminal portion. By optimizing the operation path, wire diameter, material, feed speed, and the like, the side shape of the wire can be adjusted as described above. In the terminal portion of the IC chip, the other end of the bonding wire is second-bonded by a capillary, and the bonded end is cut.

【００１３】また、基板上に搭載されるＩＣチップ４と
しては、公知に属する任意のベアＩＣチップを用いるこ
とができるが、ボンディングワイヤ６の接合を容易かつ
確実に行い、かつ所謂エッジショートを防止するため、
端子部４ａがＩＣチップ４の上面より低い位置に設定さ
れたものより、端子部４ａがＩＣチップ４の上面と同じ
か、それよりも突出する位置に設定されたものを用いる
ことが好ましい。ＩＣチップ４として端子部４ａがＩＣ
チップ４の上面より低い位置に設定されたものを用いる
場合には、端子部４ａに導電性のバンプ２１を形成し、
当該バンプ２１の表面をＩＣチップ４の上面と同じか、
それよりも突出させることが好ましい。この場合、ボン
ディングワイヤ６との接合性を良好なものにするため、
バンプ２１はボンディングワイヤ６と同一材料をもって
形成することが特に好ましい。As the IC chip 4 mounted on the substrate, any known bare IC chip can be used, but the bonding of the bonding wires 6 can be performed easily and reliably, and the so-called edge short circuit can be prevented. To do
It is preferable to use a terminal whose terminal portion 4a is set at a position that is the same as or protrudes from the upper surface of the IC chip 4 rather than a terminal whose terminal portion 4a is set at a position lower than the upper surface of the IC chip 4. The terminal portion 4a is an IC chip 4
In the case of using a chip set at a position lower than the upper surface of the chip 4, a conductive bump 21 is formed on the terminal portion 4a,
Whether the surface of the bump 21 is the same as the upper surface of the IC chip 4
It is preferable to project more than that. In this case, in order to improve the bondability with the bonding wire 6,
It is particularly preferable that the bump 21 is formed of the same material as the bonding wire 6.

【００１４】さらに、基板材料としては、任意の絶縁性
材料又は表面に絶縁性が付与された導電性材料を用いる
ことができるが、量産性に優れ安価に製造できることか
ら、絶縁性のプラスチックシートを用いることが好まし
い。この種のプラスチックシートとしては、ポリエチレ
ンテレフタレート（ＰＥＴ）、ポリエーテルスルフォン
（ＰＥＳ）、ポリエチレンナフタレート（ＰＥＮ）、ポ
リイミド等を用いることができる。当該基板２上に形成
される回路パターン３は、基板２上に例えばアルミニウ
ム、銅、銀、スズ、鉛、インジウム、クロム、ニッケル
等の良導電性金属材料又はこれらの金属材料を少なくと
も１種類以上含む合金の薄膜を真空蒸着法、スパッタリ
ング法、イオンプレーティング法などによって形成した
後、当該薄膜に精密エッチングやレーザビームカッティ
ング等を施すことによって形成することができる。Further, as the substrate material, any insulating material or a conductive material having an insulating property on the surface can be used. However, since it is excellent in mass productivity and can be manufactured at low cost, an insulating plastic sheet is used. Preferably, it is used. As this kind of plastic sheet, polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polyimide or the like can be used. The circuit pattern 3 formed on the substrate 2 includes at least one kind of a good conductive metal material such as aluminum, copper, silver, tin, lead, indium, chromium, nickel or the like, or at least one of these metal materials. After forming a thin film of an alloy containing the same by a vacuum evaporation method, a sputtering method, an ion plating method, or the like, the thin film can be formed by subjecting the thin film to precision etching or laser beam cutting.

【００１５】なお、ＩＣカード１は、ＩＣチップ４が搭
載された基板２の表裏両面にカバーシートをケーシング
することによって作製することもできるし、前記基板２
をケーシングの一部として兼用することもできる。後者
の構成によれば、ＩＣカード１のより一層の薄形化及び
低コスト化を図ることができる。The IC card 1 can be manufactured by casing cover sheets on both sides of the substrate 2 on which the IC chip 4 is mounted.
Can also be used as a part of the casing. According to the latter configuration, the thickness and cost of the IC card 1 can be further reduced.

【００１６】[0016]

【発明の実施の形態】以下、本発明の実施形態を比較例
と共に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described together with comparative examples.

【００１７】〈実施形態例〉下記の手順で、図１に示す
ＩＣカードを作製した。まず、厚さ１００μｍのＰＥＴ
フィルム上に真空蒸着法によって膜厚が０．１μｍのス
ズ膜を形成し、このスズ膜にエッチングを施して非接触
伝送用のコイルを含む回路パターン３を形成し、基板２
を得た。<Embodiment> An IC card shown in FIG. 1 was manufactured by the following procedure. First, a 100 μm thick PET
A tin film having a thickness of 0.1 μm is formed on the film by a vacuum deposition method, and the tin film is etched to form a circuit pattern 3 including a coil for non-contact transmission.
I got

【００１８】この基板２の回路パターン形成面に薄形研
摩加工された厚さ１００μｍのベアＩＣチップ４をダイ
ボンディング５でフェースアップ方式により固定した。
ダイボンディング部５の厚さは、約２０μｍであった。
ＩＣチップ４の端子部４ａには、バンプ２１を形成し、
バンプ２１の表面をＩＣチップ４の上面より約２０μｍ
突出させた。バンプ２１の形成は、金のスタッドバンプ
で行い、レベリングにより上面を平坦化した。A bare IC chip 4 having a thickness of 100 μm, which was thinly polished on the circuit pattern forming surface of the substrate 2, was fixed by die bonding 5 in a face-up manner.
The thickness of the die bonding part 5 was about 20 μm.
A bump 21 is formed on the terminal 4a of the IC chip 4,
The surface of the bump 21 is about 20 μm from the upper surface of the IC chip 4
Protruded. The bumps 21 were formed using gold stud bumps, and the upper surface was flattened by leveling.

【００１９】次に、ＩＣチップ４の端子部４ａに設けら
れたバンプ２１と回路パターン３の端子部３ａとをワイ
ヤボンディングによって接続した。ワイヤボンディング
は、所謂ネイルヘッド方式により行い、ワイヤの先端部
に加熱形成されたボールをキャピラリにより熱圧着する
第１ボンドを回路パターン３の端子部３ａに対して行
い、第２ボンドをバンプ２１に対して行った。これによ
り、ボンディングワイヤ６に、回路パターン３の端子部
３ａからほぼ基板２の回路パターン形成面の法線方向Ｘ
−Ｘに立ち上がる起立部６ａと、屈曲角度θが約９０度
の屈曲部６ｂと、前記回路パターン形成面とほぼ平行に
伸びる平行部６ｃとが形状された。ボンディングワイヤ
６の基板面からの突出高さは、約１５０μｍであった。Next, the bumps 21 provided on the terminal portions 4a of the IC chip 4 were connected to the terminal portions 3a of the circuit pattern 3 by wire bonding. The wire bonding is performed by a so-called nail head method, a first bond for thermocompression bonding a ball formed at the tip of the wire by a capillary is performed on the terminal portion 3a of the circuit pattern 3, and a second bond is formed on the bump 21. I went for it. As a result, the bonding wire 6 is moved from the terminal portion 3a of the circuit pattern 3 substantially in the normal direction X of the circuit pattern forming surface of the substrate 2.
An upright portion 6a rising to −X, a bent portion 6b having a bending angle θ of about 90 degrees, and a parallel portion 6c extending substantially parallel to the circuit pattern formation surface were formed. The projecting height of the bonding wire 6 from the substrate surface was about 150 μm.

【００２０】ワイヤボンディング後、ボンディングワイ
ヤ６及びその周辺部をモールド樹脂７にて固定すると共
に、基板２のＩＣチップ搭載面をホットメルト型のパッ
ケージ樹脂８にて覆い、さらにこのパッケージ樹脂８の
表面にカバーシート９としてＰＥＴフィルムをラミネー
トした。なお、このパッケージ樹脂８の充填とカバーシ
ート９のラミネートとは、同一の工程で行った。After the wire bonding, the bonding wires 6 and the periphery thereof are fixed with a mold resin 7, and the IC chip mounting surface of the substrate 2 is covered with a hot-melt type package resin 8. Was laminated with a PET film as a cover sheet 9. The filling of the package resin 8 and the lamination of the cover sheet 9 were performed in the same process.

【００２１】最後に、金型による打ち抜きを行って、図
１に示した非接触式のＩＣカード１を得た。カードの総
厚は、０．５ｍｍであった。Finally, punching was performed with a die to obtain a non-contact type IC card 1 shown in FIG. The total thickness of the card was 0.5 mm.

【００２２】〈第１比較例〉下記の方法で、図２に示す
ＩＣカードを作製した。バンプを有しないＩＣチップ４
を基板２上にダイボンディングした後、ＩＣチップ４の
端子部４ａと回路パターン３の端子部３ａとをワイヤボ
ンディングによって接続した。ワイヤボンディングは、
所謂ネイルヘッド方式により行い、ワイヤの先端部に加
熱形成されたボールをキャピラリにより熱圧着する第１
ボンドをＩＣチップ４の端子部４ａに対して行い、第２
ボンドを回路パターン３の端子部３ａに対して行った。
その他の部分の材質、製法、構成については、実施形態
例に係るＩＣカードと同じであるので、重複を避けるた
めに説明を省略する。<First Comparative Example> An IC card shown in FIG. 2 was manufactured by the following method. IC chip 4 without bumps
Was die-bonded onto the substrate 2, and the terminal portions 4a of the IC chip 4 and the terminal portions 3a of the circuit pattern 3 were connected by wire bonding. Wire bonding is
The first method uses a so-called nail head method in which a ball formed by heating at the tip of a wire is thermocompressed by a capillary.
Bonding is performed to the terminal portion 4a of the IC chip 4, and the second
Bonding was performed on the terminal portion 3a of the circuit pattern 3.
The material, manufacturing method, and configuration of the other parts are the same as those of the IC card according to the embodiment, and thus description thereof will be omitted to avoid duplication.

【００２３】前記のワイヤボンディングにより、ボンデ
ィングワイヤ６には、ＩＣチップ４の端子部４ａからほ
ぼ基板２の回路パターン形成面の法線方向Ｘ−Ｘに立ち
上がる起立部６ａと、屈曲角度θが鋭角状の屈曲部１０
と、前記回路パターン形成面に対して鋭角状に傾斜する
傾斜部６ｄとが形状された。ボンディングワイヤ６の基
板面からの突出高さは、約２７０μｍであった。また、
得られたＩＣカードの総厚は０．７ｍｍであり、これよ
りも薄形のＩＣカードを作製することは困難であった。Due to the wire bonding described above, the bonding wire 6 has an upright portion 6a which rises from the terminal portion 4a of the IC chip 4 substantially in the normal direction XX of the circuit pattern forming surface of the substrate 2, and the bending angle θ is an acute angle. Bent part 10
And an inclined portion 6d inclined at an acute angle to the circuit pattern formation surface. The projecting height of the bonding wire 6 from the substrate surface was about 270 μm. Also,
The total thickness of the obtained IC card was 0.7 mm, and it was difficult to produce a thinner IC card.

【００２４】〈第２比較例〉下記の方法で、図３に示す
ＩＣカードを作製した。ＩＣチップ４の端子部４ａに二
段形状のスタッドバンプ１１を設け、導電ペースト１２
を介して当該バンプ１１と回路パターン３の端子部３ａ
とをフェースダウン方式で接続した。接続部の間隙に接
着剤１３を充填して固定した後、ＩＣチップ４上から直
接パッケージ樹脂８を加えてラミネート封止を行った。
その他の部分の材質、製法、構成については、実施形態
例に係るＩＣカードと同じであるので、重複を避けるた
めに説明を省略する。得られたＩＣカードの総厚は０．
５ｍｍであった。<Second Comparative Example> An IC card shown in FIG. 3 was manufactured by the following method. A two-stage stud bump 11 is provided on the terminal portion 4 a of the IC chip 4, and a conductive paste 12 is provided.
Via the bump 11 and the terminal 3a of the circuit pattern 3
And were connected in a face-down manner. After filling and fixing the adhesive 13 in the gap between the connection portions, the package resin 8 was directly added from above the IC chip 4 to perform lamination sealing.
The material, manufacturing method, and configuration of the other parts are the same as those of the IC card according to the embodiment, and thus description thereof will be omitted to avoid duplication. The total thickness of the obtained IC card is 0.
5 mm.

【００２５】これらの結果より、実施形態例に係るＩＣ
カードは、第１比較例に係るＩＣカードに比べて約３０
％も薄くできること、及び第２比較例に係るＩＣカード
とほぼ同一の厚さに形成できることが判った。From these results, the IC according to the embodiment is
The card is about 30 times smaller than the IC card according to the first comparative example.
% Can be reduced, and it can be formed to have almost the same thickness as the IC card according to the second comparative example.

【００２６】また、実施形態例に係るＩＣカードと第１
及び第２比較例に係るＩＣカードとを夫々１００枚ずつ
作製し、各ＩＣカードに１０００回の繰り返し曲げ応力
を負荷して、曲げ応力に対する耐久性を試験した。その
結果、実施形態例に係るＩＣカードにおいて動作不良を
起したものは皆無であったのに対して、第１比較例に係
るＩＣカードは１００枚中２枚が動作不良を起し、第２
比較例に係るＩＣカードは１００枚中６枚が動作不良を
起した。この試験結果より、実施形態例に係るＩＣカー
ドは外力の作用に対する耐性が高いことが確認された。The IC card according to the embodiment and the first
Then, 100 IC cards according to the second comparative example and 100 IC cards according to the second comparative example were manufactured, and each IC card was repeatedly subjected to a bending stress of 1000 times to test the durability against the bending stress. As a result, none of the IC cards according to the embodiment caused malfunctions, whereas two of the IC cards according to the first comparative example malfunctioned, and
In the IC card according to the comparative example, six out of the 100 cards malfunctioned. From this test result, it was confirmed that the IC card according to the embodiment had high resistance to the action of external force.

【００２７】さらに、パッケージ樹脂８を施す前のモジ
ュール段階で、各ＩＣカードについて３００点ずつ接続
部の導通チェックを行った結果、実施形態例に係るＩＣ
カードと第１比較例に係るＩＣカードとはいずれも導通
不良が皆無であったのに対して、第２比較例に係るＩＣ
カードでは導通不良が１１個の接続部で発生しており、
ワイヤボンディングは導電ペーストを用いた直接接続に
比べて信頼性が高いことが実証された。Further, at the module stage before the application of the package resin 8, a continuity check of 300 connection points was performed for each IC card, and as a result, the IC according to the embodiment was
Both the card and the IC card according to the first comparative example had no conduction failure, whereas the IC card according to the second comparative example did not.
In the card, continuity failure occurs at 11 connection parts,
It has been demonstrated that wire bonding has higher reliability than direct connection using a conductive paste.

【００２８】[0028]

【発明の効果】以上説明したように、本発明によると、
ボンディングワイヤの屈曲部を回路パターンの端子部側
に偏った位置に形成したので、当該屈曲部をＩＣチップ
の端子部側に偏った位置に形成する場合に比べて、少な
くともＩＣチップの厚さ及び当該ＩＣチップを基板上に
固定するためのダイボンディング部の厚さ分だけボンデ
ィングワイヤの突出高さを低くすることができ、基板厚
さを薄形化できる。また、ボンディングワイヤの突出高
さを低くできることから、屈曲部の曲げ角度を小さくす
ることができ、屈曲部に作用する応力集中を緩和するこ
とができるので、薄形にして可撓性の高いＩＣカードに
ついても耐久性及び信頼性を高めることができる。As described above, according to the present invention,
Since the bent portion of the bonding wire is formed at a position biased toward the terminal portion of the circuit pattern, at least the thickness and the thickness of the IC chip are reduced as compared with the case where the bent portion is formed at a position biased toward the terminal portion of the IC chip. The projecting height of the bonding wires can be reduced by the thickness of the die bonding portion for fixing the IC chip on the substrate, and the substrate thickness can be reduced. Further, since the projecting height of the bonding wire can be reduced, the bending angle of the bent portion can be reduced, and the concentration of stress acting on the bent portion can be reduced. The durability and reliability of the card can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】実施形態例に係るＩＣカードの要部拡大断面図
である。FIG. 1 is an enlarged sectional view of a main part of an IC card according to an embodiment.

【図２】第１比較例に係るＩＣカードの要部拡大断面図
である。FIG. 2 is an enlarged sectional view of a main part of an IC card according to a first comparative example.

【図３】第２比較例に係るＩＣカードの要部拡大断面図
である。FIG. 3 is an enlarged sectional view of a main part of an IC card according to a second comparative example.

【符号の説明】[Explanation of symbols]

１ ＩＣカード ２ 基板 ３ 回路パターン ３ａ 回路パターンの端子部 ４ ＩＣチップ ４ａ ＩＣチップの端子部 ５ ダイボンディング ６ ボンディングワイヤ ６ａ 起立部 ６ｂ 屈曲部 ６ｃ 平行部 ７ モールド樹脂 ８ パッケージ樹脂 ９ カバーシート DESCRIPTION OF SYMBOLS 1 IC card 2 Substrate 3 Circuit pattern 3a Terminal part of circuit pattern 4 IC chip 4a Terminal part of IC chip 5 Die bonding 6 Bonding wire 6a Standing part 6b Bend part 6c Parallel part 7 Mold resin 8 Package resin 9 Cover sheet

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 基板と当該基板上に搭載されるＩＣチッ
プとを有し、前記基板に形成された回路パターンの端子
部と前記ＩＣチップの端子部とをボンディングワイヤを
介して接続してなるＩＣカードにおいて、前記ボンディ
ングワイヤの側面形状を、その一部に他の部分とは明ら
かに曲率半径が異なる屈曲部を有する形状とし、その屈
曲部を、前記回路パターンの端子部側に偏った位置に形
成したことを特徴とするＩＣカード。1. A semiconductor device comprising a substrate and an IC chip mounted on the substrate, wherein a terminal of a circuit pattern formed on the substrate and a terminal of the IC chip are connected via a bonding wire. In the IC card, the side surface shape of the bonding wire is formed in a shape having a bent portion having a curvature radius clearly different from that of another portion in a part thereof, and the bent portion is biased toward a terminal portion side of the circuit pattern. An IC card formed on a substrate. 【請求項２】 請求項１に記載のＩＣカードにおいて、
前記ボンディングワイヤが、前記回路パターンの端子部
から前記基板の回路パターン形成面の法線方向又は当該
法線方向に対して鋭角に立ち上がる起立部と、前記屈曲
部と、当該屈曲部より前記ＩＣチップの端子部に向けて
前記回路パターン形成面と平行又は当該回路パターン形
成面に対して鋭角を成す方向に伸びる平行部とを有して
いることを特徴とするＩＣカード。2. The IC card according to claim 1, wherein
The bonding wire, a rising portion rising from a terminal portion of the circuit pattern in a normal direction of the circuit pattern forming surface of the substrate or an acute angle with respect to the normal direction, the bent portion, and the IC chip from the bent portion. A parallel portion extending in a direction parallel to the circuit pattern forming surface or at an acute angle with respect to the circuit pattern forming surface toward the terminal portion. 【請求項３】 請求項１に記載のＩＣカードにおいて、
前記回路パターンの端子部に前記ボンディングワイヤの
一端がボールボンドされ、前記ＩＣチップの端子部にお
ける前記ボンディングワイヤの接合端が切断されている
ことを特徴とするＩＣカード。3. The IC card according to claim 1, wherein
An IC card, wherein one end of the bonding wire is ball-bonded to a terminal portion of the circuit pattern, and a bonding end of the bonding wire at a terminal portion of the IC chip is cut. 【請求項４】 請求項１に記載のＩＣカードにおいて、
前記ＩＣチップの端子部に導電性のバンプを形成し、当
該バンプの表面を前記ＩＣチップの上面よりも突出させ
たことを特徴とするＩＣカード。4. The IC card according to claim 1, wherein
An IC card, wherein conductive bumps are formed on terminal portions of the IC chip, and the surfaces of the bumps protrude from the upper surface of the IC chip. 【請求項５】 請求項１に記載のＩＣカードにおいて、
前記基板がプラスチックシートより形成され、前記回路
パターンがアルミニウム、銅、銀、スズ、鉛、インジウ
ム、クロム、ニッケルより選択される少なくとも１種類
の金属材料を含む薄膜をもって形成されていることを特
徴とするＩＣカード。5. The IC card according to claim 1, wherein
The substrate is formed of a plastic sheet, and the circuit pattern is formed of a thin film containing at least one metal material selected from aluminum, copper, silver, tin, lead, indium, chromium, and nickel. IC card to do.
JP8312194A 1996-11-22 1996-11-22 Ic card Withdrawn JPH10151883A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8312194A JPH10151883A (en) 1996-11-22 1996-11-22 Ic card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8312194A JPH10151883A (en) 1996-11-22 1996-11-22 Ic card

Publications (1)

Publication Number Publication Date
JPH10151883A true JPH10151883A (en) 1998-06-09

Family

ID=18026350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8312194A Withdrawn JPH10151883A (en) 1996-11-22 1996-11-22 Ic card

Country Status (1)

Country Link
JP (1) JPH10151883A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002236900A (en) * 2001-02-08 2002-08-23 Dainippon Printing Co Ltd Contact-noncontact common use type ic module and method of manufacturing
US6502917B1 (en) 1998-05-18 2003-01-07 Seiko Epson Corporation Ink-jet printing apparatus and ink cartridge therefor
US6634738B1 (en) 1999-10-12 2003-10-21 Seiko Epson Corporation Ink cartridge for ink-jet printing apparatus
JP2008541208A (en) * 2005-04-27 2008-11-20 プリバシーズ，インコーポレイテッド Electronic card and manufacturing method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6502917B1 (en) 1998-05-18 2003-01-07 Seiko Epson Corporation Ink-jet printing apparatus and ink cartridge therefor
US6550902B2 (en) 1998-05-18 2003-04-22 Seiko Epson Corporation Ink-jet printing apparatus and ink cartridge therefor
US6634738B1 (en) 1999-10-12 2003-10-21 Seiko Epson Corporation Ink cartridge for ink-jet printing apparatus
US6908184B2 (en) 1999-10-12 2005-06-21 Seiko Epson Corporation Ink cartridge for ink-jet printing apparatus
JP2002236900A (en) * 2001-02-08 2002-08-23 Dainippon Printing Co Ltd Contact-noncontact common use type ic module and method of manufacturing
JP4724923B2 (en) * 2001-02-08 2011-07-13 大日本印刷株式会社 Contact / non-contact IC module and manufacturing method thereof
JP2008541208A (en) * 2005-04-27 2008-11-20 プリバシーズ，インコーポレイテッド Electronic card and manufacturing method thereof

Similar Documents

Publication Publication Date Title
EP0992366B1 (en) Card mounted with circuit chip and circuit chip module
JP4195804B2 (en) Dual die package
KR100514023B1 (en) Semiconductor device
JPH11328352A (en) Connection structure between antenna and ic chip, and ic card
JP3421548B2 (en) Semiconductor bare chip, semiconductor bare chip manufacturing method, and semiconductor bare chip mounting structure
JP3893624B2 (en) Semiconductor device substrate, lead frame, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
US20060261456A1 (en) Micromodule, particularly for chip card
US5533664A (en) Method of manufacturing a semiconductor device
JPH10151883A (en) Ic card
US5455452A (en) Semiconductor package having an LOC structure
JPH05218127A (en) Semiconductor device and manufacture thereof
JPH08282167A (en) Ic card
JP2000299411A (en) Chip-mounting body and its manufacture
JP2981194B2 (en) Semiconductor chip package
JPH10335368A (en) Wire-bonding structure and semiconductor device
US5532189A (en) Method of making semiconductor package
JPH06112402A (en) Semiconductor device
JP4842201B2 (en) Chip module, chip card
JPS6394894A (en) Semiconductor device
US6992898B2 (en) Smart-card module with an anisotropically conductive substrate film
JPS63152160A (en) Laed frame for semiconductor device
JP2002304606A (en) Non-contact communication medium and its manufacturing method
JP2021140671A (en) RFID inlay
JPH0930170A (en) Ic card
JP2003031615A (en) Mounting structure of semiconductor device and method of mounting the same

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20040203