JP2003031615A - Mounting structure of semiconductor device and method of mounting the same - Google Patents

Mounting structure of semiconductor device and method of mounting the same

Info

Publication number
JP2003031615A
JP2003031615A JP2001214773A JP2001214773A JP2003031615A JP 2003031615 A JP2003031615 A JP 2003031615A JP 2001214773 A JP2001214773 A JP 2001214773A JP 2001214773 A JP2001214773 A JP 2001214773A JP 2003031615 A JP2003031615 A JP 2003031615A
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring
bump
semiconductor device
substrate wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001214773A
Other languages
Japanese (ja)
Inventor
Yoshio Ozeki
良雄 大関
Toru Yoshida
亨 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2001214773A priority Critical patent/JP2003031615A/en
Publication of JP2003031615A publication Critical patent/JP2003031615A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

PROBLEM TO BE SOLVED: To provide a mounting structure of semiconductor device and a method of mounting the same semiconductor device in which a bump electrode of a semiconductor element is connected to substrate wiring on a circuit substrate, and the substrate wiring coupled to the bump electrode is largely deformed to assure electrical connection at the connecting part, while a gap between the semiconductor element and substrate wiring is formed thinner to improve reliability of connection at the terminal of the semiconductor element. SOLUTION: The mounting structure of semiconductor device comprises insulating sealing resin 3, a circuit substrate 7 where thermosetting bonding agent 5 is provided between a basic material and substrate wiring 4, a semiconductor element 1 where a plurality of bump electrodes 2 are formed, and connecting part for electrically connecting on the face-down basis the semiconductor element 1 to the substrate wiring via the sealing resin 3. The substrate wiring 4 to be in contact with the bump electrode 2 of semiconductor element is largely deformed at the connecting part by removing the thermosetting bonding agent 5, while the gap between semiconductor element and substrate wiring is formed thinner up to 0.2 times or less the height of bump at the terminal of the semiconductor element.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の実装
構造体及び半導体装置を回路基板に実装する実装方法に
係り、特に、フリップチップ方式による半導体装置の実
装構造体及び半導体装置を回路基板に実装する実装方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure for a semiconductor device and a mounting method for mounting the semiconductor device on a circuit board, and more particularly to a mounting structure for a semiconductor device and a semiconductor device by a flip chip method on a circuit board. Regarding the implementation method to be implemented.

【0002】[0002]

【従来の技術】近年、ノートパソコン、PDA、携帯電
話等の情報機器の小型化、軽量化、また、無線ICタ
グ、非接触ICカード等の無線ICモジュールの薄型化
に伴い、半導体素子を回路基板に実装するための高密度
実装技術及び低コスト化のニーズが益々高くなってい
る。これに対応した実装方法としてフリップチップ方式
が提案されている。
2. Description of the Related Art In recent years, with the miniaturization and weight reduction of information devices such as notebook personal computers, PDAs, and mobile phones, and the thinning of wireless IC modules such as wireless IC tags and contactless IC cards, semiconductor elements have been incorporated into circuits. There is an increasing need for high-density mounting technology and cost reduction for mounting on a substrate. A flip chip method has been proposed as a mounting method corresponding to this.

【0003】フリップチップ方式は、複数のバンプ電極
が形成された半導体素子を、その電極形成面をフェース
ダウンさせて回路基板に接続するものであり、日本国特
許第2502794号に開示されている。
The flip chip method is a method for connecting a semiconductor element having a plurality of bump electrodes formed on it to a circuit board with its electrode forming surface face down, and is disclosed in Japanese Patent No. 2502794.

【0004】図8の断面図を参照して、従来のフリップ
チップ実装構造体について説明する。図8の回路基板7
は、基材6と基板配線4との間に紫外線硬化型もしくは
熱硬化型の高弾性率絶縁性樹脂51を形成した構成とな
っている。この回路基板7上には、半導体素子1をフェ
ースダウンで実装するための封止樹脂3が塗布されてい
る。一方、半導体素子1の電極パッド上には複数のバン
プ電極2が形成されている。
A conventional flip-chip mounting structure will be described with reference to the sectional view of FIG. Circuit board 7 of FIG.
Has a structure in which an ultraviolet curable or thermosetting high-elasticity insulating resin 51 is formed between the base material 6 and the substrate wiring 4. On the circuit board 7, a sealing resin 3 for mounting the semiconductor element 1 face down is applied. On the other hand, a plurality of bump electrodes 2 are formed on the electrode pads of the semiconductor element 1.

【0005】まず、半導体素子1に設けられている複数
のバンプ電極2と基板配線4との位置合わせを行い、次
いで、半導体素子1を回路基板7に搭載し加圧した状態
で封止樹脂3を硬化させる。この際、半導体素子1のバ
ンプ電極2と基板配線4との間に塗布していた封止樹脂
3が加圧により押し出されるため、バンプ電極2と基板
配線4とが電気的に接続される。
First, the plurality of bump electrodes 2 provided on the semiconductor element 1 are aligned with the board wiring 4, and then the semiconductor element 1 is mounted on the circuit board 7 and is pressed to form the sealing resin 3. Cure. At this time, since the sealing resin 3 applied between the bump electrode 2 of the semiconductor element 1 and the substrate wiring 4 is pushed out by pressure, the bump electrode 2 and the substrate wiring 4 are electrically connected.

【0006】この従来のフリップチップ実装構造体で
は、バンプ電極2と接触した基板配線4及び高弾性率絶
縁性樹脂層51を凹なるように弾性変形させるため、高
弾性率絶縁性樹脂層51の弾性回復力と封止樹脂3の収
縮力によって、バンプ電極2と基板配線4との電気的接
続が安定に保持される。
In this conventional flip-chip mounting structure, since the substrate wiring 4 and the high elastic modulus insulating resin layer 51 which are in contact with the bump electrodes 2 are elastically deformed to be concave, the high elastic modulus insulating resin layer 51 is formed. Due to the elastic recovery force and the contracting force of the sealing resin 3, the electrical connection between the bump electrode 2 and the substrate wiring 4 is stably maintained.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、この従
来のフリップチップ実装構造は、圧力を加え基板配線4
及び高弾性率絶縁性樹脂5を弾性変形させた状態を保持
することで電気的接続を確保する構造となっている。
However, in this conventional flip-chip mounting structure, pressure is applied to the substrate wiring 4
Also, the high elastic modulus insulating resin 5 is held in an elastically deformed state to ensure electrical connection.

【0008】このため、加圧によってバンプ2と接触し
た基板配線部分以外もほとんど変形しない構造となり、
接続部近傍の半導体素子と基板配線間ギャップと、半導
体素子端部における半導体素子と基板配線間のギャップ
が同程度となるため、半導体素子の端の部分では封止樹
脂と半導体素子の接着界面、封止樹脂と基板配線の接着
界面、封止樹脂と基材の接着界面に大きな引張応力とせ
ん断応力が集中して生じ、接続信頼性が低下するという
問題がある。
For this reason, the structure is such that the portion other than the wiring portion of the substrate which is in contact with the bump 2 by the pressure is hardly deformed,
Since the gap between the semiconductor element and the substrate wiring in the vicinity of the connection portion and the gap between the semiconductor element and the substrate wiring at the end of the semiconductor element are almost the same, at the edge portion of the semiconductor element, the bonding interface between the sealing resin and the semiconductor element, There is a problem that large tensile stress and shear stress are concentrated on the bonding interface between the sealing resin and the substrate wiring and the bonding interface between the sealing resin and the base material, and the connection reliability is reduced.

【0009】したがって、本発明の目的は、上記問題を
解決すべく、接続部ではバンプ電極と接触する基板配線
を大きく変形させて電気的接続を安定に確保し、半導体
素子の端部では半導体素子と基板配線間ギャップを極力
薄くして接続信頼性を向上させた半導体装置の実装構造
体及び実装方法を提供することにある。
Therefore, in order to solve the above problems, the object of the present invention is to greatly deform the substrate wiring contacting the bump electrode at the connection portion to stably secure the electrical connection, and to secure the electrical connection at the end portion of the semiconductor element. Another object of the present invention is to provide a mounting structure and a mounting method for a semiconductor device in which the gap between the wirings of the substrates is made as thin as possible to improve the connection reliability.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するため
の本発明に係る半導体装置の実装構造体の特徴点は、エ
ポキシ樹脂を主成分とする絶縁性封止樹脂と、基材と基
板配線の間に熱可塑性接着剤を設けた回路基板と、複数
のバンプ電極を形成した半導体素子と、半導体素子を封
止樹脂を介してフェースダウンで前記基板配線に電気的
に接続された接続部とを有する半導体装置の実装構造体
であって、前記接続部では半導体素子のバンプ電極と接
触する基板配線を熱可塑性接着剤を排除しながら大きく
変形させ、半導体素子の端では半導体素子と基板配線間
ギャップをバンプ高さの0.2倍以下まで薄くしたこと
にある。
In order to achieve the above object, the semiconductor device mounting structure according to the present invention is characterized by an insulating sealing resin containing an epoxy resin as a main component, a base material and a substrate wiring. A circuit board provided with a thermoplastic adhesive between them, a semiconductor element having a plurality of bump electrodes formed thereon, and a connecting portion electrically connected to the board wiring face down with the semiconductor element through a sealing resin. A mounting structure of a semiconductor device having: a substrate wiring contacting a bump electrode of a semiconductor element at the connection portion is largely deformed while a thermoplastic adhesive is removed; This is to make the gap thinner than 0.2 times the bump height.

【0011】また、上記目的を達成するための本発明に
係る半導体装置の実装構造体の特徴点は、エポキシ樹脂
を主成分とする絶縁性接着フィルムと、基材と基板配線
の間に熱可塑性接着剤を設けた回路基板と、複数のバン
プ電極を形成した半導体素子と、半導体素子を接着フィ
ルムを介してフェースダウンで前記基板配線に電気的に
接続された接続部とを有する半導体装置の実装構造体で
あって、前記接続部では半導体素子のバンプ電極と接触
する基板配線を熱可塑性接着剤を排除しながら大きく変
形させ、半導体素子の端では半導体素子と基板配線間ギ
ャップをバンプ高さの0.2倍以下まで薄くしたことに
ある。
The semiconductor device mounting structure according to the present invention for achieving the above object is characterized in that an insulating adhesive film containing an epoxy resin as a main component and a thermoplastic resin between the base material and the substrate wiring. Mounting of a semiconductor device having a circuit board provided with an adhesive, a semiconductor element having a plurality of bump electrodes formed thereon, and a connecting portion electrically connecting the semiconductor element face down with an adhesive film to the board wiring In the structure, the substrate wiring contacting the bump electrodes of the semiconductor element is largely deformed while eliminating the thermoplastic adhesive at the connecting portion, and the gap between the semiconductor element and the substrate wiring is set at the bump height at the end of the semiconductor element. The purpose is to reduce the thickness to 0.2 times or less.

【0012】上記絶縁性接着フィルムは、エポキシ樹脂
を主成分とするが、導電粒子を含まないエポキシ樹脂を
主成分とする接着フィルムである。
The above-mentioned insulating adhesive film is an adhesive film containing an epoxy resin as a main component but an epoxy resin containing no conductive particles as a main component.

【0013】これにより、半導体素子と基板配線間ギャ
ップをバンプ高さの0.2倍以下まで薄くした半導体素
子の端部では、封止樹脂もしくは接着フィルムと半導体
素子の接着界面、封止樹脂もしくは接着フィルムと回路
基板の接着界面に生じる応力を低減できる構造となるた
め、接続信頼性の向上が可能となった。
As a result, at the end of the semiconductor element in which the gap between the semiconductor element and the substrate wiring is thinned to 0.2 times or less of the bump height, the sealing resin or the bonding interface between the adhesive film and the semiconductor element, the sealing resin or Since the structure can reduce the stress generated at the adhesive interface between the adhesive film and the circuit board, the connection reliability can be improved.

【0014】また、高コストな異方導電性フィルムを用
いた場合に比べて低コスト化が可能であり、導電粒子を
含まないエポキシ樹脂を主成分とする接着フィルムを用
いて電気的接続を安定に確保することが可能となった。
Further, the cost can be reduced as compared with the case of using a high-cost anisotropic conductive film, and the electrical connection is stabilized by using an adhesive film containing epoxy resin as a main component containing no conductive particles. It has become possible to secure.

【0015】また、上記目的を達成するための本発明に
係る半導体装置の実装方法の特徴点は、エポキシ樹脂を
主成分とする絶縁性封止樹脂と、基材と基板配線の間に
熱可塑性接着剤を設けた回路基板と、複数のバンプ電極
を形成した半導体素子と、前記半導体素子を前記絶縁性
封止樹脂を介してフェースダウンで前記基板配線に電気
的に接続された接続部とを有してなり、前記接続部では
半導体素子のバンプ電極と接触する基板配線を熱可塑性
接着剤を排除しながら大きく変形させ、半導体素子の端
では半導体素子と基板配線間ギャップをバンプ高さの
0.2倍以下まで薄くする半導体装置の実装方法であっ
て、前記バンプ電極と前記基板配線を接続させる前に半
導体素子が実装される領域上に前記封止樹脂を前記回路
基板に予め供給し、バンプ電極と接触する基板配線を前
記熱可塑性接着剤を排除しながら大きく変形させた後、
封止樹脂を硬化させることにある。
A feature of the method for mounting a semiconductor device according to the present invention to achieve the above object is that an insulating sealing resin containing an epoxy resin as a main component and a thermoplastic resin between the base material and the substrate wiring. A circuit board provided with an adhesive, a semiconductor element having a plurality of bump electrodes formed thereon, and a connecting portion electrically connected to the board wiring face down with the semiconductor element via the insulating sealing resin. In the connection portion, the substrate wiring contacting the bump electrode of the semiconductor element is largely deformed while the thermoplastic adhesive is removed, and the gap between the semiconductor element and the substrate wiring is set to 0 at the bump height at the end of the semiconductor element. 1. A method for mounting a semiconductor device, which is reduced to a thickness of 2 times or less, wherein the sealing resin is preliminarily supplied to the circuit board on a region where a semiconductor element is mounted before connecting the bump electrode and the board wiring, After the board wiring in contact with pump electrode was greatly deformed while excluding the thermoplastic adhesive,
To cure the sealing resin.

【0016】また、上記目的を達成するための本発明に
係る半導体装置の実装方法の特徴点は、エポキシ樹脂を
主成分とする絶縁性接着フィルムと、基材と基板配線の
間に熱可塑性接着剤を設けた回路基板と、複数のバンプ
電極を形成した半導体素子と、前記半導体素子を前記絶
縁性接着フィルムを介してフェースダウンで前記基板配
線に電気的に接続された接続部とを有してなり、前記接
続部では半導体素子のバンプ電極と接触する基板配線を
熱可塑性接着剤を排除しながら大きく変形させ、半導体
素子の端では半導体素子と基板配線間ギャップをバンプ
高さの0.2倍以下まで薄くする半導体装置の実装方法
であって、前記バンプ電極と前記基板配線を接続させる
前に半導体素子が実装される領域上に、前記絶縁性接着
フィルムを回路基板に仮圧着し、バンプ電極と接触する
基板配線を熱可塑性接着剤を排除しながら大きく変形さ
せた後、接着フィルムを硬化させることにある。
A feature of the method for mounting a semiconductor device according to the present invention to achieve the above object is that an insulating adhesive film containing an epoxy resin as a main component and a thermoplastic adhesive between the base material and the board wiring. A circuit board provided with an agent, a semiconductor element having a plurality of bump electrodes formed thereon, and a connecting portion electrically connecting the semiconductor element face down through the insulating adhesive film to the board wiring. In the connection portion, the substrate wiring contacting the bump electrode of the semiconductor element is largely deformed while the thermoplastic adhesive is removed, and the gap between the semiconductor element and the substrate wiring is set to 0.2 mm of the bump height at the end of the semiconductor element. A method for mounting a semiconductor device, which reduces the thickness to less than or equal to twice, wherein the insulating adhesive film is provided on a region where a semiconductor element is mounted before connecting the bump electrodes and the substrate wiring. Temporarily crimped, after the board wiring in contact with the bump electrode is greatly deformed while eliminating thermoplastic adhesive is to cure the adhesive film.

【0017】以上説明したように、前記構成によれば、
半導体素子をフェースダウンで回路基板に実装するフリ
ップチップ方式の半導体装置の実装構造体において、接
続部では半導体素子のバンプ電極と接触する基板配線を
熱可塑性接着剤を排除しながら大きく変形させ、半導体
素子の端部では半導体素子と基板配線間ギャップをバン
プ高さの0.2倍まで薄くした実装構造体であるため、
引張応力やせん断応力が最大となるポイントを分散で
き、接続信頼性を向上させることが可能となる。
As described above, according to the above configuration,
In a mounting structure of a flip-chip type semiconductor device in which a semiconductor element is mounted face down on a circuit board, the substrate wiring contacting the bump electrode of the semiconductor element at the connection portion is largely deformed while removing the thermoplastic adhesive, At the edge of the device, the gap between the semiconductor device and the board wiring is as thin as 0.2 times the bump height.
The points at which the tensile stress and the shear stress are maximum can be dispersed, and the connection reliability can be improved.

【0018】また、本発明は、回路基板の基材を下側カ
バーシートとし、回路基板の基板配線を無線通信のため
のアンテナとする半導体装置の実装構造体である。
Further, the present invention is a mounting structure of a semiconductor device, wherein a base material of a circuit board is a lower cover sheet and board wiring of the circuit board is an antenna for wireless communication.

【0019】また、本発明は、前記記載の半導体の実装構
造体と、上側カバーシートとをホットメルト剤を用いて
接着したことを特徴とする無線ICモジュールである。
Further, the present invention is a wireless IC module characterized in that the semiconductor mounting structure described above and the upper cover sheet are bonded together by using a hot melt agent.

【0020】特に、ノートパソコン、PDA、携帯電話
等の情報機器、また、無線ICタグ、非接触ICカード
等の無線ICモジュールにおいても、接続不良を発生す
ることなく低抵抗で確実に接続することが可能となる。
Especially, in information equipment such as a notebook computer, PDA, and mobile phone, and also in a wireless IC module such as a wireless IC tag and a non-contact IC card, reliable connection can be achieved with low resistance without causing connection failure. Is possible.

【0021】[0021]

【発明の実施の形態】以下、本発明の実施の形態を、図
面を用いた実施例の具体的な説明により詳述する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings and specific description of the embodiments.

【0022】[0022]

【実施例】<実施例1>図1は、本発明の一実施例とな
る半導体装置の実装構造体101の断面図である。この
実装構造体101の構成は、エポキシ樹脂を主成分とす
る封止樹脂3と、基材6と基板配線4の間に熱可塑性接
着剤5を設けた回路基板7と、複数のバンプ電極2を形
成した半導体素子1を用いて、半導体素子1をフェース
ダウンで封止樹脂3(もしくは後述する図5の接着フィ
ルム9でも可)を介して実装する際に、接続部では半導
体素子1のバンプ電極2と接触する基板配線4を熱可塑
性接着剤5を排除しながら大きく変形させで安定して電
気的な接続を確保し、半導体素子1の端では半導体素子
1と基板配線4の間のギャップをバンプ高さの0.2倍
以下まで薄くすることで接続信頼性を向上させた構成と
したものである。
EXAMPLE 1 FIG. 1 is a sectional view of a mounting structure 101 of a semiconductor device according to an example of the present invention. The structure of this mounting structure 101 includes a sealing resin 3 containing an epoxy resin as a main component, a circuit board 7 provided with a thermoplastic adhesive 5 between a base material 6 and board wiring 4, and a plurality of bump electrodes 2. When mounting the semiconductor element 1 face down with the sealing resin 3 (or the adhesive film 9 of FIG. 5 described later also possible) using the semiconductor element 1 having the above-described structure, the bumps of the semiconductor element 1 are connected at the connecting portions. The substrate wiring 4 in contact with the electrode 2 is largely deformed while eliminating the thermoplastic adhesive 5 to secure a stable electrical connection, and the gap between the semiconductor element 1 and the substrate wiring 4 is secured at the end of the semiconductor element 1. Is thinner than 0.2 times the bump height to improve the connection reliability.

【0023】同図中のバンプ電極2は、半導体素子1の
電極パッド上にメッキ技術やワイヤバンピング工法によ
りAu等の電気的導通材料を用いて形成したものであ
る。
The bump electrode 2 in the figure is formed on the electrode pad of the semiconductor element 1 by an electrically conductive material such as Au by a plating technique or a wire bumping method.

【0024】回路基板7は、ガラス・エポキシ、ポリプ
ロピレン、ポリアリレート、ポリエチレンテレフタレー
ト(PETと記)、ポリイミド、ポリアミド等の絶縁性
樹脂の基材6上に、Au、Al、Cuの金属もしくはこ
れらの元素を用いた合金の箔を熱可塑性接着剤5を用い
て貼り付け、所定のマスクパターンを用いてエッチング
により基板配線4を形成したもの、もしくは金属箔の代
わりに金属もしくは合金層を基材上にメッキ技術により
成長させて基板配線4を形成したものである。
The circuit board 7 is made of a metal such as Au, Al, or Cu on a base material 6 of an insulating resin such as glass epoxy, polypropylene, polyarylate, polyethylene terephthalate (referred to as PET), polyimide or polyamide. An alloy foil containing an element is attached using a thermoplastic adhesive 5 and the substrate wiring 4 is formed by etching using a predetermined mask pattern, or a metal or alloy layer is used on the base material instead of the metal foil. The substrate wiring 4 is formed by growing it by a plating technique.

【0025】熱可塑性接着剤5は、例えばポリエステ
ル、ナイロン、ウレタン、ポリエチレン、ポリプロピレ
ンのいずれかのバインダ樹脂である。
The thermoplastic adhesive 5 is, for example, a binder resin selected from polyester, nylon, urethane, polyethylene and polypropylene.

【0026】図2は、図1の半導体素子1のバンプ電極
2が基板配線4に電気的に接続された状態を部分的に示
した金属顕微鏡写真である。この図から明らかなよう
に、接続部では半導体素子1のバンプ電極2と接触する
基板配線4が熱可塑性接着剤5を排除しながら変形させ
て電気的接続を安定に確保し、半導体素子1の端(同図
の右端)では半導体素子1と基板配線4の間のギャップ
をバンプ高さの0.2倍以下まで薄くして、半導体素子
1と封止樹脂3(もしくは後述する図5の接着フィルム
9)の接着界面、回路基板7と封止樹脂3(もしくは接
着フィルム9)の接着界面に生じる応力を低減できる構
造としている。
FIG. 2 is a metallographic micrograph partially showing a state in which the bump electrode 2 of the semiconductor element 1 of FIG. 1 is electrically connected to the substrate wiring 4. As is clear from this figure, the substrate wiring 4 in contact with the bump electrode 2 of the semiconductor element 1 is deformed while removing the thermoplastic adhesive 5 at the connection portion to ensure stable electrical connection, and At the end (the right end in the figure), the gap between the semiconductor element 1 and the substrate wiring 4 is thinned to 0.2 times or less the bump height, and the semiconductor element 1 and the sealing resin 3 (or the bonding of FIG. The structure is such that the stress generated at the adhesive interface of the film 9) and the adhesive interface of the circuit board 7 and the sealing resin 3 (or the adhesive film 9) can be reduced.

【0027】例えば、電気的導通材料としてAuを用い
て形成した形状a×b×最大バンプ高さtのバンプ電極
2を半導体素子1の端から長さLの位置にバンプ電極2
の端が配置するようにバンプ電極2を形成した半導体素
子1と、基板配線4の材料構成として弾性率E、厚さh
のCu箔を形成した回路基板7を用いて加圧・加熱する
と、基板配線4が熱可塑性接着剤5を排除しながら容易
に弾性変形するため、接続部では高さばらつきを吸収す
るとともに、バンプ電極2の一部が塑性変形して基板配
線4の形状にならうため、電気的接続を安定に確保する
ことができる。
For example, a bump electrode 2 having a shape a × b × maximum bump height t formed by using Au as an electrically conductive material is provided at a position having a length L from the end of the semiconductor element 1.
Of the semiconductor element 1 in which the bump electrodes 2 are formed so that the ends of the wirings are arranged, and the material composition of the substrate wiring 4 is the elastic modulus E and the thickness h.
When the circuit board 7 on which the Cu foil is formed is pressed and heated, the board wiring 4 is easily elastically deformed while the thermoplastic adhesive 5 is removed. Since a part of the electrode 2 is plastically deformed to follow the shape of the board wiring 4, stable electrical connection can be ensured.

【0028】また、図3に示すように、半導体素子1端
部における半導体素子1と基板配線4間ギャップをバン
プ高さtの0.2倍以下まで薄くすることで、半導体素
子1と封止樹脂3(もしくは接着フィルム9)の接着界
面、回路基板7と封止樹脂3もしくは接着フィルム4の
接着界面に生じる応力を低減させ、接続信頼性を向上さ
せることができる。 <実施例2>次に半導体装置の実装構造体101の実装
方法について、図4の工程図を用いて説明する。
Further, as shown in FIG. 3, the gap between the semiconductor element 1 and the substrate wiring 4 at the end of the semiconductor element 1 is reduced to 0.2 times or less the bump height t so that the semiconductor element 1 and the sealing are sealed. It is possible to reduce the stress generated at the adhesive interface between the resin 3 (or the adhesive film 9) and the adhesive interface between the circuit board 7 and the sealing resin 3 or the adhesive film 4, and improve the connection reliability. <Embodiment 2> Next, a method of mounting the mounting structure 101 of the semiconductor device will be described with reference to the process chart of FIG.

【0029】工程1として、回路基板7を以下の方法で
形成する。基板配線4としてAu、Al、Cuの金属も
しくはこれらの元素を用いた合金を用いる場合、基板配
線4は金属箔もしくは合金箔を、例えばポリエステル接
着剤のような熱可塑性接着剤5を用いて基材6に貼り付
け、この金属箔もしくは合金箔を周知のリソグラフ技術
によるレジストマスク形成とエッチングにより回路基板
7を形成する。
In step 1, the circuit board 7 is formed by the following method. When a metal such as Au, Al, or Cu or an alloy using these elements is used as the substrate wiring 4, the substrate wiring 4 is formed of a metal foil or an alloy foil by using a thermoplastic adhesive 5 such as a polyester adhesive. The circuit board 7 is formed by adhering the metal foil or alloy foil on the material 6 and forming a resist mask by a well-known lithographic technique and etching.

【0030】なお、回路基板7の形成方法としては、そ
の他、例えば、金属箔もしくは合金箔を熱可塑性接着剤
5を用いて基材6に貼り付けメッキ技術により金属もし
くは合金層を成長させて基板配線5を形成する方法、さ
らには、金属もしくは合金層を基材6の熱可塑性接着剤
5上にメッキ技術により成長させて基板配線5を形成す
る方法もあり、いずれの形成方法を用いてもよい。
As a method of forming the circuit board 7, for example, a metal foil or an alloy foil is attached to the base material 6 by using the thermoplastic adhesive 5 to grow a metal or alloy layer by a plating technique and then the substrate is formed. There is also a method of forming the wiring 5, and further, a method of forming a substrate wiring 5 by growing a metal or alloy layer on the thermoplastic adhesive 5 of the base material 6 by a plating technique, and any forming method can be used. Good.

【0031】工程2として、この回路基板7上に封止樹
脂3を塗布する。なお、この工程は、図4(a)に示して
いる。
In step 2, the sealing resin 3 is applied on the circuit board 7. Note that this step is shown in FIG.

【0032】工程3として、予めバンプ電極2を形成し
た半導体素子1を、位置合わせ搭載装置8を用いて基板
配線5上の所定の位置に搭載する。バンプ電極2は、前
述の通り、半導体素子1の電極パッド上にメッキ技術や
ワイヤバンピング工法によりAu等の電気的導通材料を
用いて形成する。なお、この工程は、図4(b)に示して
いる。
In step 3, the semiconductor element 1 on which the bump electrode 2 is formed in advance is mounted on the substrate wiring 5 at a predetermined position by using the positioning mounting device 8. As described above, the bump electrode 2 is formed on the electrode pad of the semiconductor element 1 using an electrically conductive material such as Au by a plating technique or a wire bumping method. This step is shown in FIG. 4 (b).

【0033】最後に工程4として、バンプ電極2と基板
配線4との間に高い接触応力が常に保持されるように、
半導体素子1に加圧力(200MPa)を加えた状態で封止樹
脂3を熱硬化(180℃で20s)して電気的接続を安定に確
保する。以上の工程で本発明の目的とする半導体装置の
実装構造体101を得た。なお、この工程は、図4(c)
に示している。
Finally, in step 4, a high contact stress is always maintained between the bump electrode 2 and the substrate wiring 4,
The sealing resin 3 is thermoset (20 s at 180 ° C.) while the semiconductor element 1 is applied with a pressure (200 MPa), and a stable electrical connection is secured. Through the above steps, the semiconductor device mounting structure 101, which is the object of the present invention, is obtained. This process is shown in Fig. 4 (c).
Is shown in.

【0034】このように、本発明の半導体装置の実装構
造体101を用いれば、電気的接続を安定に確保するこ
とができ、また、従来のエポキシ樹脂等の高弾性率絶縁
性樹脂層を設けた場合の比較例に比べ、低コスト化及び
接続信頼性の向上を実現することができる。 <実施例3>図5は、実施例2の封止樹脂の代わりに、
同様の機能を有する接着フィルムを用いた実装方法の工
程を説明する断面図である。
As described above, by using the semiconductor device mounting structure 101 of the present invention, stable electrical connection can be ensured, and a conventional high elastic modulus insulating resin layer such as epoxy resin is provided. It is possible to realize cost reduction and improvement in connection reliability as compared with the comparative example in the case of the above. <Embodiment 3> FIG.
It is sectional drawing explaining the process of the mounting method using the adhesive film which has the same function.

【0035】図5(c)の断面図に示す半導体装置の実
装構造体102は、基本的には実施例2の図4と同じ工
程で実装されるが、前述の回路基板7上に封止樹脂3を
塗布する工程の代わりに、エポキシ樹脂もしくは導電粒
子を含まないエポキシ樹脂を主成分とする接着フィルム
9を仮圧着する工程を用いる点が異なる。すなわち、図
5(a)に示すように、回路基板7上に封止樹脂3の代わ
りに接着フィルム9を敷く。
The mounting structure 102 of the semiconductor device shown in the sectional view of FIG. 5C is basically mounted in the same process as that of FIG. 4 of the second embodiment, but is sealed on the circuit board 7 described above. The difference is that instead of the step of applying the resin 3, a step of temporarily press-bonding an adhesive film 9 whose main component is an epoxy resin or an epoxy resin containing no conductive particles is used. That is, as shown in FIG. 5A, an adhesive film 9 is laid on the circuit board 7 instead of the sealing resin 3.

【0036】次いで図5(b)に示すように、予めバンプ
電極2を形成した半導体素子1を、位置合わせ搭載装置
8を用いて基板配線5上の所定の位置に搭載する。バン
プ電極2は、前述の通り、半導体素子1の電極パッド上
にメッキ技術やワイヤバンピング工法によりAu等の電
気的導通材料を用いて形成する。
Next, as shown in FIG. 5B, the semiconductor element 1 on which the bump electrodes 2 are formed in advance is mounted on the substrate wiring 5 at a predetermined position by using the positioning mounting device 8. As described above, the bump electrode 2 is formed on the electrode pad of the semiconductor element 1 using an electrically conductive material such as Au by a plating technique or a wire bumping method.

【0037】最後に図5(c)に示すように、バンプ電極
2と基板配線4との間に高い接触応力が常に保持される
ように、半導体素子1に加圧力(200MPa)を加えた状態
で封止樹脂3を熱硬化(180℃で20s)して電気的接続を
安定に確保する。以上の工程で本発明の目的とする半導
体装置の実装構造体102を得た。
Finally, as shown in FIG. 5C, a pressure (200 MPa) is applied to the semiconductor element 1 so that a high contact stress is always maintained between the bump electrode 2 and the substrate wiring 4. The thermosetting of the sealing resin 3 (at 180 ° C for 20s) secures the electrical connection. Through the above steps, the semiconductor device mounting structure 102, which is the object of the present invention, is obtained.

【0038】以上、図5(c)の断面図に示した通り、
本実施例の半導体装置の実装構造体102は、エポキシ
樹脂もしくは導電粒子を含まないエポキシ樹脂を主成分
とする接着フィルム9と、基材6と基板配線4の間に熱
可塑性接着剤5を設けた回路基板7と、複数のバンプ電
極2を形成した半導体素子1を用いて、半導体素子1を
フェースダウンで接着フィルム9を介して実装し、接続
部では半導体素子1のバンプ電極2と接触する基板配線
4を熱可塑性接着剤5を排除しながら容易に変形させて
電気的な接続を確保し、半導体素子1の端では半導体素
子1と基板配線4の間のギャップをバンプ高さの0.2
倍まで薄くすることで接続信頼性を向上させた構成とし
たものである。 <実施例4>図6及び図7は、非接触ICカード103
及び無線ICタグ104、105の無線ICモジュール
に、本発明の半導体装置の実装構造体101もしくは1
02を適用した例を示している。
As described above, as shown in the sectional view of FIG.
The mounting structure 102 of the semiconductor device according to the present embodiment is provided with an adhesive film 9 containing an epoxy resin or an epoxy resin containing no conductive particles as a main component, and a thermoplastic adhesive 5 between the base material 6 and the board wiring 4. Using the circuit board 7 and the semiconductor element 1 having the plurality of bump electrodes 2 formed thereon, the semiconductor element 1 is mounted face down via the adhesive film 9 and is in contact with the bump electrode 2 of the semiconductor element 1 at the connection portion. The substrate wiring 4 is easily deformed while the thermoplastic adhesive 5 is removed to ensure electrical connection. At the end of the semiconductor element 1, the gap between the semiconductor element 1 and the substrate wiring 4 is set to 0. Two
The connection reliability is improved by making it twice as thin. <Fourth Embodiment> FIGS. 6 and 7 show a non-contact IC card 103.
And the mounting structure 101 or 1 of the semiconductor device of the present invention in the wireless IC modules of the wireless IC tags 104 and 105.
An example in which 02 is applied is shown.

【0039】すなわち、図6(a)は非接触ICカード1
03の平面図、図6(b)は図6(a)のA−A′断面図を示
している。図7(a)は無線ICタグ104、図7(b)
は無線ICタグ105の無線ICモジュールの平面図を
それぞれ示している。図7(c)は図7(a)のB−B′
断面図、図7(d)は図7(b)のB−B′断面図をそれ
ぞれ示している。
That is, FIG. 6A shows the non-contact IC card 1
03 is a plan view, and FIG. 6 (b) is a sectional view taken along the line AA 'in FIG. 6 (a). FIG. 7A shows the wireless IC tag 104, and FIG. 7B.
Shows plan views of the wireless IC modules of the wireless IC tag 105, respectively. FIG. 7C shows BB ′ of FIG. 7A.
The cross-sectional view and FIG. 7D are cross-sectional views taken along the line BB ′ of FIG. 7B.

【0040】図示のように、回路基板7の基板配線4を
アンテナコイル、基材6をフィルム状のフレキシブルな
下側カバーシートとして回路基板7を構成した本発明の
半導体装置の実装構造体101、もしくは102と、下
側カバーシートと同様な材料でフィルム状のフレキシブ
ルな上側カバーシート11とをホットメルト剤10を用
いて接着した構成となっている。このように無線ICモ
ジュールは、本発明の半導体装置の実装構造体を用いた
構成であるため、電気的接続を安定に確保することがで
き、また、低コスト化とともに接続信頼性の向上を実現
することができる。 <実施例5>上記実施例3〜4において、エポキシ樹脂
を主成分とする30μm厚の導電粒子を含まない接着フ
ィルム9を回路基板7に仮圧着を行う。回路基板7は基
材6を50μm厚のPETフィルム、基板配線4を弾性
率115GPa、9μm厚のCu配線、また、基板配線
4と基材6を接着するための接着剤としてポリエステル
系の熱可塑性接着剤5を用いる構成とした。
As shown in the figure, the mounting structure 101 of the semiconductor device of the present invention, in which the circuit board 7 is formed by using the board wiring 4 of the circuit board 7 as an antenna coil and the substrate 6 as a film-like flexible lower cover sheet, Alternatively, 102 and a film-shaped flexible upper cover sheet 11 made of the same material as the lower cover sheet are bonded by using a hot melt agent 10. As described above, since the wireless IC module has the configuration using the mounting structure of the semiconductor device of the present invention, stable electrical connection can be ensured, and cost reduction and improvement of connection reliability are realized. can do. <Example 5> In Examples 3 to 4, the adhesive film 9 containing epoxy resin as a main component and having a thickness of 30 [mu] m and containing no conductive particles is temporarily pressure-bonded to the circuit board 7. For the circuit board 7, the base material 6 is a PET film with a thickness of 50 μm, the board wiring 4 has an elastic modulus of 115 GPa, a Cu wiring with a thickness of 9 μm, and a polyester-based thermoplastic as an adhesive for bonding the board wiring 4 and the base material 6. The adhesive 5 is used.

【0041】次いで、半導体素子1の電極パッド上に電
気メッキ技術により形成した50μm×50μm×高さ1
5μm厚のAuのバンプ電極2と回路基板7上のCu配
線4の電気的な接続を確保するために180℃20sの
硬化条件で接続した。
Next, 50 μm × 50 μm × height 1 formed on the electrode pad of the semiconductor element 1 by the electroplating technique.
In order to secure the electrical connection between the 5 μm thick Au bump electrode 2 and the Cu wiring 4 on the circuit board 7, they were connected under a curing condition of 180 ° C. for 20 s.

【0042】ここで、加圧力として、バンプ先端面積の
単位面積当たりの力200MPaとすることで、接続部
では半導体素子1のバンプ電極2と接触する基板配線4
を熱可塑性接着剤5を排除しながら容易に変形し、半導
体素子1の端では半導体素子1と基板配線4の間のギャ
ップを2〜3μm程度とバンプ高さの0.2倍以下まで
薄くした。
Here, by applying a pressure of 200 MPa per unit area of the tip area of the bump as the pressing force, the substrate wiring 4 which contacts the bump electrode 2 of the semiconductor element 1 at the connection portion.
Was easily deformed while removing the thermoplastic adhesive 5, and the gap between the semiconductor element 1 and the substrate wiring 4 was thinned to about 2 to 3 μm at the end of the semiconductor element 1 to 0.2 times or less the bump height. .

【0043】接続抵抗値の測定は、10mAの定電流を
印加して4端子法によりバンプ電極と接触接続の合計の
測定電圧値から接続抵抗値を算出した。この結果、85
℃85%RHの高温高湿試験100時間後においても接
続抵抗値は、100mΩ未満で安定した接続抵抗値であ
ることを確認した。
The connection resistance value was measured by applying a constant current of 10 mA and calculating the connection resistance value from the total measured voltage value of the bump electrode and the contact connection by the 4-terminal method. As a result, 85
It was confirmed that the connection resistance value was stable at less than 100 mΩ even after 100 hours of the high temperature and high humidity test at 85 ° C. and 85% RH.

【0044】[0044]

【発明の効果】以上のように、本発明によれば、電気的
接続を安定に確保することができ、回路基板に高弾性率
絶縁樹脂層を設ける場合や導電粒子を介して接触接続を
確保する場合に比べ、低コスト化とともに接続信頼性の
向上を実現することができる。
As described above, according to the present invention, stable electrical connection can be secured, and contact connection is secured when a high elastic modulus insulating resin layer is provided on a circuit board or through conductive particles. As compared with the case where the cost is reduced, the cost can be reduced and the connection reliability can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例となる実装構造体の断面図。FIG. 1 is a sectional view of a mounting structure according to an embodiment of the present invention.

【図2】本発明の実施例となる実装構造体のバンプ周辺
の金属顕微鏡写真による断面拡大図。
FIG. 2 is an enlarged cross-sectional view of a bump structure of a mounting structure according to an embodiment of the present invention, taken along a metallurgical micrograph.

【図3】本発明の実施例の詳細を説明するための特性曲
線図で、バンプ高さを考慮した半導体素子端部における
基板配線間のギャップと接続不良率との関係を示した
図。
FIG. 3 is a characteristic curve diagram for explaining details of the embodiment of the present invention, and is a diagram showing a relationship between a gap between substrate wirings and a connection failure rate at an end portion of a semiconductor element in consideration of bump height.

【図4】本発明の実施例となる実装工程を示した断面
図。
FIG. 4 is a cross-sectional view showing a mounting process according to an embodiment of the present invention.

【図5】本発明の他の実施例となる実装工程を示した断
面図。
FIG. 5 is a sectional view showing a mounting process according to another embodiment of the present invention.

【図6】本発明の実施例となる実装構造体を非接触IC
カードに適用した説明図。
FIG. 6 illustrates a mounting structure according to an embodiment of the present invention in which a contactless IC
Explanatory drawing applied to a card.

【図7】本発明の実施例となる実装構造体を無線ICタ
グに適用した説明図。
FIG. 7 is an explanatory diagram in which a mounting structure according to an embodiment of the present invention is applied to a wireless IC tag.

【図8】従来例となる実装構造体の断面図。FIG. 8 is a cross-sectional view of a conventional mounting structure.

【符号の説明】[Explanation of symbols]

1…半導体素子、 2…バンプ電極、 3…封止樹脂、 4…熱可塑性接着剤、 5…基板配線、 6…基材、 7…回路基板、 8…位置合わせ搭載装置、 9…接着フィルム、 10…ホットメルト剤、 11…上側カバーシート、 12…絶縁フィルム、 101、102…半導体装置の実装構造体、 103…非接触ICカード、 104、105…無線ICタグ。 1 ... Semiconductor element, 2 ... bump electrodes, 3 ... Sealing resin, 4 ... Thermoplastic adhesive, 5 ... Board wiring, 6 ... Base material 7 ... circuit board, 8 ... Positioning device 9 ... Adhesive film, 10 ... Hot melt agent, 11 ... Upper cover sheet, 12 ... Insulating film, 101, 102 ... Semiconductor device mounting structure, 103 ... Non-contact IC card, 104, 105 ... Wireless IC tags.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】エポキシ樹脂を主成分とする絶縁性封止樹
脂と、基材と基板配線の間に熱可塑性接着剤を設けた回
路基板と、複数のバンプ電極を形成した半導体素子と、
前記半導体素子を前記絶縁性封止樹脂を介してフェース
ダウンで前記基板配線に電気的に接続された接続部とを
有する半導体装置の実装構造体であって、前記接続部で
は半導体素子のバンプ電極と接触する基板配線を熱可塑
性接着剤を排除しながら大きく変形させ、半導体素子の
端では半導体素子と基板配線間ギャップをバンプ高さの
0.2倍以下まで薄くしたことを特徴とする半導体装置
の実装構造体。
1. An insulative sealing resin containing an epoxy resin as a main component, a circuit board provided with a thermoplastic adhesive between a base material and board wiring, and a semiconductor element having a plurality of bump electrodes formed thereon.
A mounting structure of a semiconductor device, comprising a connecting portion electrically connected to the substrate wiring face down with the semiconductor element via the insulating sealing resin, wherein the connecting portion has bump electrodes of the semiconductor element. A semiconductor device characterized in that the substrate wiring contacting the substrate is largely deformed while eliminating the thermoplastic adhesive, and the gap between the semiconductor element and the substrate wiring is thinned to 0.2 times or less of the bump height at the end of the semiconductor element. Implementation structure of.
【請求項2】エポキシ樹脂を主成分とする絶縁性接着フ
ィルムと、基材と基板配線の間に熱可塑性接着剤を設け
た回路基板と、複数のバンプ電極を形成した半導体素子
と、前記半導体素子を前記絶縁性接着フィルムを介して
フェースダウンで前記基板配線に電気的に接続された接
続部とを有する半導体装置の実装構造体であって、前記
接続部では半導体素子のバンプ電極と接触する基板配線
を熱可塑性接着剤を排除しながら大きく変形させ、半導
体素子の端では半導体素子と基板配線間ギャップをバン
プ高さの0.2倍以下まで薄くしたことを特徴とする半
導体装置の実装構造体。
2. An insulating adhesive film containing an epoxy resin as a main component, a circuit board provided with a thermoplastic adhesive between a base material and substrate wiring, a semiconductor element having a plurality of bump electrodes formed thereon, and the semiconductor. A mounting structure of a semiconductor device having a connection part electrically connected to the substrate wiring face down through the insulating adhesive film, wherein the connection part is in contact with a bump electrode of the semiconductor element. Mounting structure of a semiconductor device characterized in that the board wiring is largely deformed while removing the thermoplastic adhesive, and the gap between the semiconductor element and the board wiring is thinned to 0.2 times or less of the bump height at the end of the semiconductor element. body.
【請求項3】エポキシ樹脂を主成分とする絶縁性封止樹
脂と、基材と基板配線の間に熱可塑性接着剤を設けた回
路基板と、複数のバンプ電極を形成した半導体素子と、
前記半導体素子を前記絶縁性封止樹脂を介してフェース
ダウンで前記基板配線に電気的に接続された接続部とを
有してなり、前記接続部では半導体素子のバンプ電極と
接触する基板配線を熱可塑性接着剤を排除しながら大き
く変形させ、半導体素子の端では半導体素子と基板配線
間ギャップをバンプ高さの0.2倍以下まで薄くする半
導体装置の実装方法であって、前記バンプ電極と前記基
板配線を接続させる前に半導体素子が実装される領域上
に前記封止樹脂を前記回路基板に予め供給し、バンプ電
極と接触する基板配線を前記熱可塑性接着剤を排除しな
がら大きく変形させた後、封止樹脂を硬化させることを
特徴とする半導体装置の実装方法。
3. An insulating encapsulating resin containing an epoxy resin as a main component, a circuit board provided with a thermoplastic adhesive between a base material and board wiring, and a semiconductor element having a plurality of bump electrodes formed thereon.
The semiconductor element has a connecting portion electrically connected to the substrate wiring face down with the insulating sealing resin interposed therebetween, and the connecting portion includes a substrate wiring contacting a bump electrode of the semiconductor element. A method of mounting a semiconductor device, wherein a large deformation is performed while eliminating a thermoplastic adhesive, and a gap between a semiconductor element and a substrate wiring is thinned to 0.2 times or less of a bump height at an end of the semiconductor element, the bump electrode and Before connecting the board wiring, the sealing resin is pre-supplied to the circuit board on the area where the semiconductor element is mounted, and the board wiring contacting the bump electrodes is largely deformed while removing the thermoplastic adhesive. After that, the semiconductor device mounting method is characterized in that the sealing resin is cured.
【請求項4】エポキシ樹脂を主成分とする絶縁性接着フ
ィルムと、基材と基板配線の間に熱可塑性接着剤を設け
た回路基板と、複数のバンプ電極を形成した半導体素子
と、前記半導体素子を前記絶縁性接着フィルムを介して
フェースダウンで前記基板配線に電気的に接続された接
続部とを有してなり、前記接続部では半導体素子のバン
プ電極と接触する基板配線を熱可塑性接着剤を排除しな
がら大きく変形させ、半導体素子の端では半導体素子と
基板配線間ギャップをバンプ高さの0.2倍以下まで薄
くする半導体装置の実装方法であって、前記バンプ電極
と前記基板配線を接続させる前に半導体素子が実装され
る領域上に、前記絶縁性接着フィルムを回路基板に仮圧
着し、バンプ電極と接触する基板配線を熱可塑性接着剤
を排除しながら大きく変形させた後、接着フィルムを硬
化させることを特徴とする半導体装置の実装方法。
4. An insulating adhesive film containing an epoxy resin as a main component, a circuit board provided with a thermoplastic adhesive between a base material and board wiring, a semiconductor element having a plurality of bump electrodes formed thereon, and the semiconductor. The device has a connecting portion electrically connected to the substrate wiring facedown through the insulating adhesive film, and the substrate wiring contacting the bump electrode of the semiconductor element is thermoplastically bonded at the connecting portion. A method for mounting a semiconductor device, wherein a bump between a semiconductor element and a board wiring is thinned to 0.2 times or less of a bump height at an end of the semiconductor element while largely deforming while removing an agent. Before the connection of the semiconductor element, the insulating adhesive film is temporarily pressure-bonded to the circuit board on the area where the semiconductor element is mounted, and the board wiring that contacts the bump electrode is large while eliminating the thermoplastic adhesive. After Ku deformed, mounting method of a semiconductor device, characterized in that curing the adhesive film.
【請求項5】請求項1もしくは2記載の半導体装置の実
装構造体における回路基板の基材を下側カバーシートと
し、回路基板の基板配線を無線通信のためのアンテナと
することを特徴とする無線ICモジュール。
5. The base material of the circuit board in the semiconductor device mounting structure according to claim 1 or 2 serves as a lower cover sheet, and the board wiring of the circuit board serves as an antenna for wireless communication. Wireless IC module.
【請求項6】請求項1もしくは2記載の半導体装置の実
装構造体と、上側カバーシートとをホットメルト剤を用
いて接着したことを特徴とする請求項6に記載の無線I
Cモジュール。
6. The wireless I according to claim 6, wherein the semiconductor device mounting structure according to claim 1 and the upper cover sheet are bonded to each other by using a hot melt agent.
C module.
JP2001214773A 2001-07-16 2001-07-16 Mounting structure of semiconductor device and method of mounting the same Pending JP2003031615A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001214773A JP2003031615A (en) 2001-07-16 2001-07-16 Mounting structure of semiconductor device and method of mounting the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001214773A JP2003031615A (en) 2001-07-16 2001-07-16 Mounting structure of semiconductor device and method of mounting the same

Publications (1)

Publication Number Publication Date
JP2003031615A true JP2003031615A (en) 2003-01-31

Family

ID=19049534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001214773A Pending JP2003031615A (en) 2001-07-16 2001-07-16 Mounting structure of semiconductor device and method of mounting the same

Country Status (1)

Country Link
JP (1) JP2003031615A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007027305A (en) * 2005-07-14 2007-02-01 Shindo Denshi Kogyo Kk Semiconductor device and its manufacturing method
JP2007057392A (en) * 2005-08-24 2007-03-08 Fis Inc Semiconductor gas sensor and semiconductor gas sensor for gas chromatograph
US9450197B2 (en) 2014-08-08 2016-09-20 Samsung Display Co., Ltd. Flexible display apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007027305A (en) * 2005-07-14 2007-02-01 Shindo Denshi Kogyo Kk Semiconductor device and its manufacturing method
JP4657840B2 (en) * 2005-07-14 2011-03-23 新藤電子工業株式会社 Semiconductor device and manufacturing method thereof
JP2007057392A (en) * 2005-08-24 2007-03-08 Fis Inc Semiconductor gas sensor and semiconductor gas sensor for gas chromatograph
US9450197B2 (en) 2014-08-08 2016-09-20 Samsung Display Co., Ltd. Flexible display apparatus

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