JPH10144923A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high reliable, high-performance MOS TFT device with a crystalline silicone film used as an active region by after having the outermost portion of the silicon film thin-film-etched, the active region with an insulating film in the upper layer is covered, thus forming it without exposing to air. SOLUTION: When a crystalline silicon film 105 is subjected to reactive etching, the entire surface of the silicon film 105 is turned into a thin film. The etching makes rapid progress especially in the grain boundary 107 where ridges 108 are present, and the ridges are selectively etched and shaved. Here, the exposed surface of the crystalline silicon film 109 is rid of the contaminated region in its surface layer. As a result, the unevenness of the surface is reduced, and the surface is brought into a very clean state. For this reason, a verey clean crystalline silicon film 109-oxide film 110 boundary 111 is obtained, by covering the crystalline silicon film 109 with the oxide film 110 without exposing it to the air.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention is effective for a semiconductor device using a thin film transistor (hereinafter, referred to as a TFT) having a MOS type or other structure provided on a substrate having an insulating surface. It can be used for sensors and three-dimensional ICs.

[0002]

2. Description of the Related Art In recent years, large and high resolution liquid crystal display devices have been developed.
High-speed, high-resolution contact image sensor, 3D IC
In order to realize such a technique, attempts have been made to form a high-performance semiconductor element on an insulating substrate such as glass or an insulating film. In general, a silicon semiconductor thin film is used for a semiconductor element used in these devices. Silicon semiconductor thin films are roughly classified into two types: those made of an amorphous silicon semiconductor (a-Si) and those made of a crystalline silicon semiconductor.

[0003] Amorphous silicon semiconductors are most commonly used because they have a low production temperature, can be produced relatively easily by a gas phase method, and have high mass productivity. Since it is inferior to a crystalline silicon semiconductor, a method for manufacturing a semiconductor device made of a crystalline silicon semiconductor has been strongly demanded in order to obtain higher-speed characteristics in the future. In addition, as a silicon semiconductor having crystallinity,
Polycrystalline silicon, microcrystalline silicon and the like are known.

As a method for obtaining a silicon semiconductor in the form of a thin film having such crystallinity, there is the following method.

(1) A film having crystallinity is directly formed at the time of film formation.

(2) An amorphous semiconductor film is formed,
Crystallinity is imparted by applying heat energy.

(3) An amorphous semiconductor film is formed in advance,
Crystallinity is imparted by the energy of strong light such as laser light.

However, in the above method (1), crystallization proceeds simultaneously with the film formation step, so that it is difficult to obtain crystalline silicon having a large grain size, and it is essential to increase the thickness of the silicon film. . Moreover, even though the film thickness is increased, only a crystal grain size substantially equal to the film thickness is basically obtained, and it is in principle impossible to produce a silicon film having good crystallinity by this method. It is possible.

The method (2) is used for crystallization of 600
Since heat treatment for several tens of hours is required at a high temperature of not less than ℃, productivity is very poor. Also, in order to utilize the solid-phase crystallization phenomenon, the crystal grains spread in parallel to the substrate surface and are several μm
However, since the grown crystal grains collide with each other to form a grain boundary, the grain boundary acts as a trap level for carriers, which is a major cause of lowering the mobility of the TFT. ing. Further, each crystal grain has a twin structure, and a large number of crystal defects called so-called twin defects exist in one crystal grain.

For this reason, the method (3) is mainly used at present. In the above method (3), the crystallization is carried out by utilizing the melt-solidification process, so that the crystallinity in each crystal grain is very good. Further, by selecting the wavelength of the irradiation light, it is possible to efficiently heat only the silicon film to be annealed, to prevent thermal damage to the underlying glass substrate, and to reduce the length as described in the above (2). No processing over time is required. A high-output excimer laser annealing apparatus and the like have also been developed in terms of equipment, and are now being able to cope with large-area substrates. A method of forming a crystalline silicon thin film using this method is disclosed in Japanese Patent Application Laid-Open No. Hei 7-135173.
In this publication, after injecting silicon ions into an amorphous silicon film, a pulse laser such as an excimer laser is irradiated to crystallize the amorphous silicon film. In Japanese Patent Application Laid-Open No. 163588/1994, the surface of a crystalline silicon film, which is considered to be crystallized by the above method (3), is polished with an abrasive to obtain the unevenness of the surface of the crystalline silicon film. Has been reduced.

[0011]

SUMMARY OF THE INVENTION In the current technology,
In order to realize a high-performance semiconductor device, it is best to use at least the above method (3) in producing a silicon semiconductor thin film constituting the active region. However, in the crystalline silicon film obtained by the method (3),
The size of the surface roughness is a major problem. That is, in the above method (3), the amorphous silicon film is instantaneously heated to its melting point of 1414 ° C. or more by the energy of strong light, and is heated to several tens of nsec. It is cooled to around room temperature in about a cooling time and solidified. At this time, since the solidification rate is too high, the silicon film is in a supercooled state, and is solidified instantaneously.
As extremely small as about nm, the point where the crystal grains collide, that is, the crystal grain boundary rises in a mountain shape. This phenomenon is particularly remarkable at the three poles where three crystal grains collide. The ridge-shaped portion caused by the crystal growth is hereinafter referred to as a “ridge”.

The above phenomenon occurs not only in the case where the starting film for intense light irradiation is an amorphous silicon film but also in the case where a crystalline silicon film is used. In the case of a crystalline silicon film, even if it is melted by intense light irradiation, some microcrystalline components are retained, the components become nuclei, and recrystallization is performed with some information on the original crystal remaining. Is done. Therefore, as compared with the case of crystallization from the above-mentioned amorphous silicon film, the crystal grain size increases, the size of each ridge also increases, and the generation density of ridges decreases.

FIG. 6 shows an atomic force microscope (AF) showing the surface state of a crystalline silicon film actually crystallized by intense light irradiation.
M) Shows a sketched image below. In FIG. 6, X
The full scale in the Y direction is 1 μm, and the full scale in the Z direction is 100 nm. When an active region of a semiconductor device such as a MOS thin film transistor is formed by using such a crystalline silicon film, an electric field is concentrated on a ridge on the surface of the crystalline silicon film. That is, the breakdown voltage of the insulating film formed on the crystalline silicon film is reduced, which causes a leak current. Therefore, the reliability of the semiconductor device is greatly reduced, and it is extremely difficult to obtain a semiconductor device that can be used practically.

Further, the ridge of the silicon film is formed by MOS
In a thin-film transistor, it is present at the interface between the channel surface (the crystalline silicon film and the gate oxide film), causing fixed charges in the gate oxide film and at the interface, and deteriorating the interface characteristics. . In addition, they serve as a scattering center for carriers and reduce the field-effect mobility of the transistor.

In an active matrix substrate such as a liquid crystal display device, an auxiliary capacitance is generally provided in parallel with a liquid crystal capacitance. When the above crystalline silicon film is used as an electrode of the auxiliary capacitance component together with the channel portion of the pixel TFT, the capacitance deviates from the design value due to the change in the surface area ratio due to the ridge, and display such as display unevenness and flicker is caused. It causes a defect.

The above-mentioned Japanese Patent Application Laid-Open Nos. Hei 6-163588 and Hei 7-135173 have been proposed as one solution to the above-mentioned problem. It does not solve the above problem.
Japanese Patent Application Laid-Open No. Hei 6-163588 discloses a method for chemically and mechanically polishing the surface irregularities of a crystalline silicon film with an abrasive, but the crystalline silicon film is a portion which becomes an active region of a semiconductor device. In a MOS thin film transistor, the surface constitutes a channel surface, and it is not preferable to damage this surface. In the above polishing step, the surface of the crystalline silicon film suffers considerable polishing damage, and even if a semiconductor device is manufactured using such a silicon film as an active region, a high-reliability and high-performance semiconductor which is an object of the present invention. No equipment is available.
Japanese Patent Application Laid-Open No. Hei 7-135173 discloses a technique in which silicon is injected into a silicon thin film and crystallization is performed by laser irradiation. This is only an effect to the extent that it is reduced, and is not a drastic solution.
Therefore, even if a semiconductor device is manufactured by forming a semiconductor thin film using the method disclosed in Japanese Patent Application Laid-Open No. 7-135173, it is not possible to obtain a high-performance device having high reliability as the object of the present invention.

In order to improve the performance and reliability of a MOS thin film transistor, in addition to improving the crystallinity and surface state of the crystalline silicon film, a channel surface (crystalline silicon film / gate) is formed. An important point is to improve the interface characteristics of the insulating film). This interfacial property has a great effect on the ridge on the surface of the crystalline silicon film-on the other hand, the suboxide (lower oxide layer) at this interface
The effect of impurities such as carbon and carbon is also very large. Therefore, it is necessary to keep the interface between the (crystalline silicon film and the gate insulating film) as clean as possible, and it is most desirable to form the interface continuously without exposing it to the atmosphere.

However, in a general top gate type thin film transistor, it is necessary to perform a patterning step for separating a lower crystalline silicon film between elements before forming a gate insulating film. Difficult.
In addition, since there is actually a crystallization process of a crystalline silicon film, it is necessary to continuously form an amorphous silicon film, crystallize by irradiating strong light, and form a gate insulating film without exposing it to the atmosphere. However, it is an undeveloped technology in terms of equipment, and even if it can be realized, it becomes a very expensive equipment. Generally, after forming a crystalline silicon film to be an active region of a TFT, a photosensitive resin (photoresist) is applied, exposed and developed, unnecessary regions are removed by etching, and the photoresist is peeled off. After that, a gate insulating film is formed. Therefore, after the crystalline silicon is deposited, the surface of the active region, which is the most important for the TFT, that is, the channel surface is not only exposed to the air and is contaminated, but also the photoresist is directly in contact with the channel surface, which is caused by the photoresist. In addition, contamination caused by a stripping solution or etching accompanying the patterning process is added, which further deteriorates and destabilizes the interface characteristics.

The present invention solves all the above-mentioned problems in a semiconductor thin film used for a semiconductor device such as a TFT, and realizes a high-reliability high-performance semiconductor device or a high-quality liquid crystal display device. Things.

[0020]

SUMMARY OF THE INVENTION The present invention provides an active matrix liquid crystal display device having a larger size and a higher resolution, a driver monolithic type active matrix liquid crystal display device having a driver for driving a liquid crystal on the same substrate, and a high-speed active matrix liquid crystal display device. An object of the present invention is to provide a high-performance semiconductor element having high reliability in order to realize a high-resolution contact image sensor, a three-dimensional IC, and the like. That is, as described above, the present invention relates to a conventional problem in a high-quality crystalline silicon film obtained by irradiation with intense light such as a laser beam, and
The present invention simultaneously solves the problem of the interface between the (crystalline silicon film and the gate insulating film) in the OS type thin film transistor.

The present inventors have somehow solved the above-mentioned problems, and have high reliability and high performance using a crystalline silicon film as an active region, which can be applied to a high display quality liquid crystal display device or a thin film integrated circuit. I was studying day and night to see if we could realize a simple MOS TFT device. As a result, finally, by using the present invention having the following features, the above problems can be solved,
It turns out that the purpose can be coupled.

Specifically, the present invention has the following features.

(1) A MOS type semiconductor device using a crystalline silicon film formed on a substrate having an insulating surface and having an active region formed on the silicon film, wherein the active region is a silicon film After the outermost surface of the thin film is etched,
It is characterized by being formed by being covered with an upper insulating film without being exposed to the air.

(2) The insulating film constitutes a gate insulating film of a MOS thin film transistor, and a surface of the active region is a channel surface of the MOS thin film transistor.

(3) A semiconductor device having a MOS type thin film transistor for driving a plurality of pixel electrodes on a substrate having an insulating surface, wherein each of the thin film transistors is connected to an auxiliary capacitance component in parallel with a liquid crystal capacitance by the pixel electrode. At
The active region of each of the thin film transistors and the lower electrode of the auxiliary capacitance component are formed of the same crystalline silicon film, and the gate insulating film and the auxiliary capacitance component insulating film of the thin film transistor are formed of the same insulating film. The crystalline silicon film is formed by being covered with the insulating film without being exposed to the air after the outermost surface is thin-film etched.

(4) In the above (1) and (3), the silicon film constituting the active region is obtained by irradiating the amorphous silicon film with intense light such as an excimer laser and crystallizing the silicon film in a melting and solidifying process. Characterized in that:

(5) In the above (1) and (3), the silicon film constituting the active region is formed by introducing a catalytic element for promoting crystallization into the amorphous silicon film and subjecting the amorphous silicon film to a solid phase crystal growth step by heat treatment. The crystalline silicon film crystallized by the above is further irradiated with strong light such as an excimer laser and recrystallized.

Here, the crystalline silicon film crystallized in the solid phase crystal growth step is obtained by selectively introducing a catalytic element for promoting the crystallization into the amorphous silicon film and subjecting the amorphous silicon film to a heat treatment. It is preferable that the crystal is laterally grown from the region where the catalyst element is selectively introduced to the peripheral portion.

The strong light used to crystallize the amorphous silicon film or to recrystallize the crystalline silicon film crystallized in the solid phase crystal growth step has a wavelength of 5 nm.
It is preferable to use a laser beam of 00 nm or less, and it is particularly preferable to use a XeCl excimer laser beam having a wavelength of 308 nm.

Ni, Co, Pd, Pt, Cu, and A are catalyst elements for promoting crystallization of the amorphous silicon film.
It is preferable to use one or more elements selected from g, Au, In, Sn, A1, and Sb.
It is preferable to use at least an element.

(6) The average surface roughness Ra of the surface of the crystalline silicon film after the thin film etching is 5 nm or less.

(7) The thickness T of the crystalline silicon film to be etched has a relationship of T> Ra with respect to the average surface roughness Ra of the surface of the crystalline silicon film before the thin film etching. It is characterized by.

(8) The average surface roughness Ra is a value measured with an atomic force microscope (AFM) for a measurement area of 10 μm □ or less.

(9) The step of performing the thin film etching includes:
It is performed by reactive dry etching using a fluorinated gas such as CF ₄ or NF ₃ .

(10) The step of thin-film etching the surface of the crystalline silicon film and the step of forming and covering an insulating film on the surface of the crystalline silicon film are performed in the same pressure reducing device. And

(11) After the outermost surface of the crystalline silicon film is thin-film-etched, the newly exposed crystalline silicon film surface is exposed to a plasma atmosphere containing at least oxygen or hydrogen, and then the insulating film is formed. And a step of covering the surface of the crystalline silicon film.

The features of the present invention are as described above. The broad gist of the present invention is that a crystalline silicon film formed on a substrate having an insulating surface is used, and an active region is formed in the silicon film. In the MOS type semiconductor device, the active region is covered with an upper insulating film without exposing the outermost surface of the crystalline silicon film to the atmosphere after the thin film etching. Here, there are two points of the present invention,
The active region, that is, the outermost surface of the crystalline silicon film is etched in a thin film, and thereafter, the active region is covered with an upper insulating film without being exposed to the air. The former is mainly effective in reducing roughness such as ridges on the surface of the crystalline silicon film, and aims to remove the outermost surface of the crystalline silicon film contaminated in the manufacturing process and to provide a new clean surface. . The latter aims at maintaining a clean state by immediately protecting the clean surface of the crystalline silicon film obtained in the etching step with an insulating film before it is newly contaminated.

In particular, the present invention is effective for MOS type thin film transistors. By using the insulating film as it is as the gate insulating film of the TFT, the surface of the above-mentioned clean active region becomes its channel surface. That is, TFT
The interface between the active region (the crystalline silicon film and the gate insulating film), which controls the electrical characteristics of the semiconductor, is not exposed to the air at all, and the natural oxide film (suboxide) and impurities on the surface of the crystalline silicon film that deteriorate the interface characteristics Since there is no contamination at all, an interface state almost similar to the state of continuous formation can be obtained by a simple process. Therefore, TFT
The current driving capability (field effect mobility, rise coefficient, etc.) of the device is improved, and the reliability is greatly improved.

In improving the current driving capability and reliability of the TFT, the reduction of the surface roughness of the crystalline silicon film also greatly contributes. As described above, when the roughness of the surface of the crystalline silicon film serving as the TFT channel surface is large, not only does it become a scattering center for carriers, it also tends to cause electric field concentration and becomes a leak source, and the fixed charge density of the gate insulating film decreases. This is because there are many disadvantages such as increased interface characteristics. Therefore, the synergistic effect of the effect of reducing the roughness of the surface of the crystalline silicon film serving as the channel surface of the TFT and the cleanness of the interface described above,
The current drive capability and its reliability are dramatically improved.

In this respect, the present invention is particularly effective for a high-quality crystalline silicon film which is crystallized in the melting and solidification process by irradiating the amorphous silicon film with strong light such as a laser beam. As described above, during crystallization by intense light irradiation,
The silicon film has a melting point of 141 due to the energy of strong light.
Heated instantaneously to 4 ° C. or higher, for several tens of nsec. It is cooled to around room temperature in about a cooling time and solidified. At the time of the change from the liquid phase to the solid phase, the crystal grains collide, and the point at which the crystal grains collide rises like a mountain. That is, ridges are generated at the grain boundary of the crystalline silicon film. This phenomenon is remarkable particularly at the three poles where three crystal grains collide among the crystal grain boundaries. An outline of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a manufacturing process of a crystalline silicon semiconductor thin film of the present invention,
The manufacturing process proceeds in the order of (A) → (D). FIG. 1 (A)
5, an insulating base film 102 such as a silicon oxide film is formed on a substrate 101 made of glass or the like, and an amorphous silicon (a-Si) film 103 is further formed thereon. For this amorphous silicon (a-Si) film 103,
As shown in FIG. 1B, strong light 104 such as a laser is irradiated and crystallized in a melt-solidification process. As a result, the amorphous silicon (a-Si) film 103 becomes the crystalline silicon film 10.
It becomes 5. The crystalline silicon film 105 is composed of crystal grains 106, and the surface of the crystal grain boundary 107 rises like a mountain. That is, the ridge 108 appears.

Next, the thin film etching step, which is the point of the present invention, is performed. It is desirable to use reactive etching by a chemical reaction as the etching means at this time. This reactive etching has a property of progressing particularly at the crystal grain boundary where the bonding state of Si atoms is particularly poor. That is, when the crystalline silicon film 105 is subjected to reactive etching, the surface of the silicon film 105 is entirely thinned as shown in FIG. In particular, the etching progresses in the portion, and when viewed relatively, the ridge 108 is selectively etched and cut off.
Here, the exposed surface of the crystalline silicon film 109 is:
The contaminated area on the surface layer is peeled off, and the surface unevenness is reduced, and at the same time, it is in a very clean state. Then, as shown in FIG. 1D, the oxide film 1 is immediately used as an insulating film.
By covering the crystalline silicon film 109 with 10, a very clean and favorable state can be obtained as the interface 111 of (the crystalline silicon film 109 ＼the oxide film 110).

In the above-described process, it is most desirable that the crystalline silicon film 109 is covered with the oxide film 110 as an insulating film immediately, and ideally, continuous processing is performed in a vacuum without exposing to the air. This is because once the crystalline silicon film is exposed to the air, the surface is oxidized, and contamination such as carbon is generated as generally called natural contamination. Therefore, it is desirable that the step of thin-film etching the surface of the crystalline silicon film and the step of forming the oxide film to cover the surface of the crystalline silicon film be performed in the same decompression device. That is, as the etching method at this time, a plasma etching treatment under a reduced-pressure atmosphere is most desirable, and a reactive dry etching using a fluorine gas such as CF ₄ or NF ₃ is most desirable.

Further, recontamination of the surface of the crystalline silicon film during the plasma etching process (C, N,
F) In order to reduce damage during etching and the like, the newly exposed crystalline silicon film surface is exposed to a plasma containing at least oxygen or hydrogen after the etching process, and then an oxide film is formed as an insulating film. It is more desirable to cover the surface of the crystalline silicon film. Oxygen is particularly effective in removing the C-based material, but has the effect of reducing the interface state. Hydrogen has a high cleaning effect such as removal of N and F.

The surface roughness of the silicon film by the ridge in the present invention is defined by the average surface roughness Ra.
The average surface roughness Ra is a value obtained by averaging the absolute values of deviations from a reference surface (a flat surface having an average height of the designated surface) to the designated surface, and is represented by the following equation.

Ra = 1 / S ₀ ∬ | F (X, Y) −Z ₀ | dXdY where S ₀ is the area of the reference plane, Z ₀ is the height of the reference plane, and F
(X, Y) represents the height of the designated surface at the coordinates (X, Y). One object of the present invention is to reduce the unevenness of the silicon film surface due to the ridge by an etching process, so that the silicon film is formed at least over the average surface roughness Ra representing the average value of the surface roughness. Etching is required. When the thickness T of the silicon film to be etched is smaller than the average surface roughness Ra, the size of the ridge is slightly reduced, but the shape does not change. There is no big effect. Therefore, in the present invention, the average surface roughness Ra of the silicon film surface after intense light irradiation
In contrast, it is necessary that the thickness T of the crystalline silicon film to be etched has a relationship of at least T> Ra.

It is desirable that the average surface roughness Ra of the surface of the crystalline silicon film finally obtained after the thin film etching is 5 nm or less. Of course, the smaller the value, the better. However, if the value is at least 5 nm or less, the breakdown voltage and the interface characteristics of the upper insulating film are deteriorated.
Fluctuations in capacitance and the like can be suppressed to a level that hardly affects the element.

If the average surface roughness Ra is a value measured with an atomic force microscope (AFM) for a measurement area of 10 μm □ or less, there is measurement reliability up to the sub-nm order. The gist of the present invention is not spoiled.
In FIG. 1, the amorphous silicon film 103 was used as a starting film before crystallization by intense light irradiation. However, by using a crystalline silicon film obtained by a solid phase crystal growth process as a starting film, A more uniform crystalline silicon film can be obtained over the entire surface. This is because, as a problem at the time of crystallization due to the strong light irradiation, the stability of a laser or the like as a light source is not sufficient, and it is difficult to obtain a uniform crystalline silicon film over the entire surface of the substrate. By using a solid-phase grown crystalline silicon film as the starting film before intense light irradiation, it is recrystallized while leaving some information on the initial uniform crystallinity. The direct influence of the intense light irradiation step is reduced, and a more uniform crystalline silicon film is easily obtained. However, the crystalline silicon film itself crystallized only in the solid phase growth step has poor crystallinity as compared with the one crystallized by intense light irradiation. A high quality crystalline silicon film that can be used for high performance semiconductor devices.

Further, when a crystalline silicon film solid-phase crystallized using a catalyst element that promotes crystallization of an amorphous silicon film is used as a starting film before intense light irradiation, in addition to the uniformity surface, Further improved crystallinity, high-quality crystalline silicon film,
Then, a high-performance semiconductor device having excellent current driving capability can be realized. This is because a crystalline silicon film using the above catalyst element has a network structure of columnar crystals as described above. Although the catalyst element is extremely present in the crystal grain boundary portion and is in a poor crystal state, the crystallinity in each columnar crystal is good and almost a single crystal state is exhibited. When the crystalline silicon film is irradiated with strong light and recrystallized in the process of melting and solidifying, a part of each columnar crystal having a strong bonding state remains without being melted, and crystallization proceeds using the crystal as a seed crystal. As a result, the resulting crystalline silicon film becomes a very high-quality crystalline silicon film. That is, the crystalline silicon film solid-phase crystallized by the above-mentioned catalyst element is compared with a crystalline silicon film solid-phase-crystallized without using the conventional catalyst element, and is subjected to a recrystallization step by intense light irradiation. Is very compatible.

Further, when a silicon film which is solid-phase-crystallized one-dimensionally in the lateral direction with a catalyst element which promotes crystallization of an amorphous silicon film is used as a starting film before irradiation with strong light, the crystallinity is further improved. Thus, a high-quality crystalline silicon film, which is considered to be the best at present, can be obtained, and a high-performance semiconductor device having extremely excellent current driving capability can be realized. That is, in the silicon film, the columnar crystals are arranged in order in almost one direction, and in this region, there is no crystal grain boundary in principle. When this region is irradiated with strong light, the individual columnar crystals are bonded to each other, and a crystalline silicon region having very good crystallinity close to a single crystal state is obtained over a wide region.

The types of the catalytic elements usable in the present invention include Ni, Co, Pd, Pt, Cu, Ag, and Ni.
Au, In, Sn, Al, and Sb can be used. One or a plurality of elements selected from these elements have an effect of promoting crystallization in a very small amount, and the influence on the semiconductor device can be suppressed to a small level.

Further, among them, the most remarkable effect can be obtained particularly when Ni is used. The reason for this has not been fully understood, but we are considering the following model. The catalytic element does not act alone,
By combining with the silicon film and forming silicide, it acts on crystal growth. The model is such that the crystal structure at that time acts like a kind of template when the amorphous silicon film is crystallized, and promotes the crystallization of the amorphous silicon film. Ni forms silicide of _two Si and NiSi2. NiSi ₂ exhibits a fluorite-type crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover,
NiSi ₂ has a lattice constant of 5.406 ° and a lattice constant of 5.430 ° in a crystalline silicon diamond structure.
Has a value very close to. Therefore, NiSi ₂ is the best as a template for crystallizing an amorphous silicon film, and Ni is most preferably used as a catalyst element in the present invention.

The high-quality crystalline silicon semiconductor thin film of the present invention can be used for an active region of a semiconductor device in general, while an active matrix substrate for a liquid crystal display has, in addition to a channel region of a pixel TFT, It is desirable to form one electrode portion of an auxiliary capacitance (Cs) connected in parallel with the liquid crystal pixel capacitance. In an active matrix substrate for a liquid crystal display device, an auxiliary capacitor (Cs) is provided in parallel with a liquid crystal pixel capacitor in order to reduce a voltage drop phenomenon in a pixel electrode portion that occurs when a gate pulse signal is turned off. Since the larger the auxiliary capacitance (Cs) is, the smaller the voltage drop is, it is most preferable to form the same layer as the gate insulating film of the TFT from the viewpoint of simplifying the manufacturing process. However, the variation of the auxiliary capacitance (Cs) within the screen causes display unevenness such as flicker on the screen. When an electrode having an auxiliary capacitance (Cs) is manufactured using a crystalline silicon film obtained by conventional intense light irradiation, the auxiliary capacitance (Cs) varies due to the surface roughness caused by the ridge, and a liquid crystal display device with good display quality is provided. It was difficult to get. On the other hand, when the crystalline silicon film according to the present invention is used, since the surface roughness is greatly reduced, the variation of the auxiliary capacitance (Cs) can be suppressed, and the liquid crystal display of high display quality without display unevenness. A device is obtained.

As the intense light used in the present invention, it is desirable to use laser light having a wavelength of 500 nm or less. This is because, when crystallization or recrystallization of a silicon film by intense light irradiation is performed with strong light having a wavelength of 500 nm or less, the absorption coefficient of the silicon film is extremely high, so that the silicon substrate can be thermally damaged without causing thermal damage to the glass substrate. Only the film can be heated instantaneously. In addition, by using a laser beam, the silicon film can be instantaneously melted at a melting point of 1414.
High output can be achieved simply by heating to ° C. Among them, XeCl excimer laser light with a wavelength of 308 nm, in particular, has a large output, so that the beam size upon irradiating the substrate can be increased, it is easy to cope with a large-area substrate, and the output is relatively stable. Most desirable in doing.

[0054]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) A first embodiment using the present invention will be described below. Example 1 In this example, steps of manufacturing an active matrix substrate for a liquid crystal display device over a glass substrate by using the present invention will be described. In this active matrix substrate, an N-channel TFT is formed as an element for switching each surface element, and an auxiliary capacitor (C) is provided on the drain region side in parallel with the pixel liquid crystal capacitor.
s) is provided.

In the following, FIG. 2 is a cross-sectional view showing the outline of the manufacturing process of this embodiment, in which (A) → (E)
, The manufacturing process proceeds sequentially. FIG. 2 (E)
Is a completed view of a pixel TFT and an auxiliary capacitance (Cs) portion thereof manufactured in the present example.
4 and an auxiliary capacitance (Cs) region 226 are shown.

First, as shown in FIG. 2A, a glass substrate 201 having a thickness of 30
A base film 202 of about 0 nm made of silicon oxide is formed. This silicon oxide film is provided to prevent diffusion of impurities from the glass substrate. Next, an intrinsic (i-type) amorphous silicon (a-S) having a thickness of 20 to 100 nm, for example, 50 nm is formed by a low pressure CVD method, a plasma CVD method, or the like.
i) The film 203 is formed. When the a-Si film 203 is formed by the plasma CVD method, a large amount of hydrogen is contained in the film, which causes peeling of the film during laser irradiation later. It is necessary to perform a heat treatment for several hours to release hydrogen in the film.

After that, as shown in FIG. 2A, a laser beam 207 is irradiated to crystallize the a-Si film 203.
At this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec.) Was used as a laser beam. The irradiation condition of the laser beam 207 is such that the substrate is heated to 200 to 500 ° C., for example, 400 ° C. at the time of irradiation, and the energy density is 200 to 350 mJ / cm ² , for example, 300 mJ.
/ Cm ² . The laser beam 207 was sequentially scanned on the substrate surface, and the scanning pitch was set so that an arbitrary point on the a-Si film 203 was irradiated with laser 10 times each. By this step, the a-Si film 203 is heated to a temperature equal to or higher than its melting point, and is melted and solidified to form a crystalline silicon film having good crystallinity. Here, when the average surface roughness Ra of the surface of the crystalline silicon film was measured by an atomic force microscope (AFM), the value was about 6 to 7 nm.

Next, unnecessary portions of the crystalline silicon film are removed by patterning, thereby performing element isolation as shown in FIG. 2B, and subsequently, the active regions (source region, drain region) of the TFT. , A channel region) and an island-shaped crystalline silicon film 208 constituting a lower electrode of the storage capacitor (Cs).

Next, as shown in FIG. 2C, a photoresist is applied on the island-shaped crystalline silicon film 208,
Exposure and development are performed to form a mask 209. That is, the mask 209 is in a state where only a portion which will be a channel region of the TFT later is covered. Then, an impurity (phosphorus) 210 is implanted by ion doping using the photoresist mask 209 as a mask. Phosphine (PH ₃ ) is used as a doping gas, the acceleration voltage is 5 to 30 kV, for example, 15 kV, and the dose is 1 ×.
10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . By this step, the region into which the impurities are implanted becomes the source region 217 of the N-channel TFT portion 224 later, and the drain region of the N-channel TFT portion 224 and the lower electrode region 218 of the storage capacitor (Cs) are formed. Impurities 210 masked by photoresist mask 209
Is not implanted later becomes the channel region 216 of the N-channel TFT portion 224 as described above. afterwards,
The photoresist mask 209 is removed.

Then, in this state, the glass substrate 201 is introduced into the CVD apparatus. First, in the CVD apparatus, light etching is performed on the surface of the crystalline silicon film. This light etching step was performed by plasma etching using RF plasma under a reduced pressure atmosphere of about 0.1 Torr using, for example, CF ₄ and O ₂ as an etching gas. The etching rate in the plasma etching performed in this embodiment is about 30 nm / min, and the etching time is 20 s.
ec. Then, the crystalline silicon film 208 was etched by about 10 nm from the outermost surface. As a result, the thickness of the crystalline silicon film 208 became 40 nm. At this time, the surface of the crystalline silicon film 208 (particularly, the channel region 216) was measured by an atomic force microscope (AFM). As a result, the average surface roughness Ra was about 2 to 3 nm, which was greatly reduced from the initial value.

Subsequently, in the same CVD chamber,
After performing plasma treatment with oxygen to reduce the residual concentration of CF ₄ gas and improve the interfacial characteristics of (crystalline silicon film 絶 縁 gate insulating film), a thickness of 20 to 20 mm is applied so as to cover the island-shaped crystalline silicon film 208. A 150-nm, here 100-nm, silicon oxide film is formed as the gate insulating film 211. Here, TEOS (Tetra) is used for forming the silicon oxide film.
Ethoxy Ortho Silicate) was used as a raw material, and was decomposed and deposited by RF plasma CVD at a substrate temperature of 150 to 600 ° C., preferably 300 to 400 ° C. together with oxygen. Alternatively, TEOS is used as a raw material together with ozone gas by a low pressure CVD method or a normal pressure CVD method.
The substrate temperature is set to 350 to 600 ° C, preferably 400 to 55.
It may be formed at 0 ° C. After the film formation, the gate insulating film 21
In order to further improve the bulk characteristics of itself and the interface characteristics of (crystalline silicon film＼gate insulating film), annealing was performed at 500 to 600 ° C. for several hours in an inert gas atmosphere. At the same time, this annealing process
7 and the impurity 210 doped in the drain region and the lower electrode region 218 are activated, and the source region 217 is formed.
The resistance of the drain region and the lower electrode region 218 is reduced. As a result, the sheet resistance of the source region 217 and the drain region and the lower electrode region 218 is 800 to 1000.
Ω / □.

Subsequently, as shown in FIG. 2D, an aluminum film having a thickness of 300 to 500 nm, for example, 400 nm is formed by a sputtering method. Then, the aluminum film is patterned to form the gate electrode 212 and the upper electrode 213 in the storage capacitor (Cs) region 226. Here, the gate electrode 212 is a part of the n-th gate bus line in plan view, and has a storage capacitance (Cs).
Is formed as a part of the (n + 1) th gate bus line.

Then, as shown in FIG.
A silicon oxide film of about 00 nm is formed as the interlayer insulating film 219. If this silicon oxide film is formed using TEOS as a raw material by a plasma CVD method with oxygen and a reduced pressure CVD method or a normal pressure CVD method with ozone, a good interlayer insulating film having excellent step coverage can be obtained. Can be Next, a contact hole is formed in the interlayer insulating film 219, and a source electrode 220 and a pixel electrode 223 are formed. The source electrode 220 is formed of a metal material, for example, a two-layer film of titanium nitride and aluminum. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. The pixel electrode 223 is formed of a transparent conductive film such as ITO.

Finally, in a hydrogen atmosphere of 1 atm.
Annealing is performed at 0 ° C. for about 1 hour to complete the N-channel TFT portion 224 and the auxiliary capacitance (Cs) region 226 shown in FIG. By this annealing process, the (active region / gate insulating film) of the N-channel type TFT portion 224 is formed.
Has the effect of reducing dangling bonds that degrade the TFT characteristics by supplying hydrogen atoms to the interface of. In order to further protect the N-channel TFT 224, only necessary portions may be covered with a silicon nitride film formed by a plasma CVD method.

The TFT manufactured according to the above embodiment
Showed good characteristics of a field effect mobility of 50 to 80 cm ² / Vs and a threshold voltage of ^{2 to 3} V. In the channel region 216, the drain region, and the lower electrode region 218 of the N-channel type TFT portion 224, the surface average roughness Ra is reduced to about 2 to 3 nm. There is almost no current, and the non-uniformity of each capacitance can be kept small. As a result, a liquid crystal display panel was manufactured using the active matrix substrate manufactured in this example, and the entire display was performed. As a result, a high-reliability, high-display-quality liquid crystal display device without display unevenness was realized. .

(Embodiment 2) A second embodiment using the present invention will be described. In this embodiment, a description will be given of a process of manufacturing an N-channel TFT on a glass substrate in the case where the present invention is used. N-channel type T of this embodiment
The FT can be used not only as a driver circuit and a pixel portion of an active matrix type liquid crystal display device but also as an element constituting a CPU, a control circuit, a signal generation circuit, and the like on the same substrate. It goes without saying that TFTs can be applied not only to liquid crystal display devices but also to thin film integrated circuits that are generally called.

FIG. 3 is a cross-sectional view schematically showing the steps of manufacturing the TFT described in this embodiment, and the manufacturing steps sequentially proceed in the order of (A) → (E). First, as shown in FIG. 3A, a thickness of 30 mm is formed on a glass substrate 301 by, for example, a sputtering method.
A base film 302 of about 0 nm made of silicon oxide is formed. This silicon oxide film is provided to prevent diffusion of impurities from the glass substrate.

Next, by a low pressure CVD method, a thickness of 20 to 1
An intrinsic (I-type) amorphous silicon film (a-Si film) 303 having a thickness of 00 nm, for example, 50 nm is formed.

Next, as shown in FIG. 3A, the glass substrate 301 is held so that the surface of the a-Si film 303 is in contact with the aqueous solution 305 in which nickel is dissolved. In this embodiment,
Nickel acetate was used as the solute, and the nickel concentration in the aqueous solution was adjusted to 10 ppm. After that, the aqueous solution 305 is uniformly spread on the glass substrate 301 by a spinner and dried.

This is annealed in a hydrogen reducing atmosphere or an inert atmosphere at a heating temperature of 520 to 600 ° C. for several hours to several tens of hours, for example, at 550 ° C. for 4 hours for crystallization. At this time, nickel coated on the surface becomes a nucleus, and crystallization of the amorphous silicon film 303 occurs in a direction perpendicular to the glass substrate 301, and a crystalline silicon film 303a is formed as shown in FIG. Is done. The nickel applied to the surface was diffused throughout the crystalline silicon film 303a, and the nickel concentration in the crystalline silicon film 303a at this time was about 1 × 10 ¹⁸ atoms / cm ³ . At this time, each crystal grain is constituted by a network of columnar crystals having a width of 100 to 200 nm,
The crystal grain size was about μm.

After that, as shown in FIG. 3B, a laser beam 307 is irradiated to recrystallize the crystalline silicon film 303a. The laser light at this time was a XeCl excimer laser (wavelength 308 nm, pulse width 40 ns)
c. ) Was used. The laser light irradiation conditions 307, 200 to 500 ° C. The substrate upon irradiation, by heating for example to 400 ° C., the energy density 200~350mJ / cm ^2, for example was 300 mJ / cm ^2. The scanning pitch was set so that the laser beam 307 was sequentially scanned on the substrate surface, and laser irradiation was performed 10 times on any one point of the crystalline silicon film 303a. In this step, the crystalline silicon film 303a is heated to a temperature equal to or higher than its melting point, melted and solidified, and is partially recombined as a seed crystal to further improve the crystallinity. Here, an atomic force microscope (AF)
M), the average surface roughness Ra of the surface of the crystalline silicon film 303a was measured and was about 7 to 8 nm. The reason why the average surface roughness Ra is larger than that of the first embodiment is as follows.
Because the starting film in the laser irradiation is a crystalline silicon film, as described above, a part of the film is recrystallized as a seed crystal, and the crystal grain size grows larger, and the ridge increases accordingly. .

Next, as shown in FIG. 3 (C), unnecessary portions of the crystalline silicon film 303a are removed by patterning to perform element isolation, and subsequently, the active regions (source region, drain region, channel) of the TFT are formed. An island-shaped crystalline silicon film 308 to be a region is formed.

Then, in this state, the glass substrate 301 is introduced into the CVD apparatus, and first, the island-shaped crystalline silicon film 308 is formed.
Is lightly etched. In this light etching step, for example, NF ₃ or Ar is used as an etching gas.
This was performed by plasma etching using RF plasma.
The etching rate in the plasma etching performed in this embodiment is about 60 nm / min, and the etching time is 20 sec. Then, the island-shaped crystalline silicon film 308 was etched by about 20 nm from the outermost surface.
Thus, the thickness of the island-shaped crystalline silicon film 308 is 30 n.
m. At this time, the surface of the island-shaped crystalline silicon film 308 was measured by an atomic force microscope (AFM).
The average surface roughness Ra was about 2 to 3 nm, which was greatly reduced as compared with the initial value.

Subsequently, in the same chamber of the CVD apparatus, plasma treatment with hydrogen was performed to reduce the residual concentration of the NF ₃ gas and clean the surface of the crystalline silicon film 308 in an island shape. A silicon oxide film having a thickness of 20 to 150 nm, here 100 nm, is formed as the gate insulating film 311 so as to cover the island-shaped crystalline silicon film 308. Here, TEO is used for forming the silicon oxide film.
S (Tetra Ethoxy Ortho Sili)
cat) as a raw material and a substrate temperature of 150 to 150 together with oxygen.
Decomposition and deposition were performed at 600 ° C., preferably 300 to 400 ° C., by RF plasma CVD. After the film formation, the gate insulating film 3
11 itself bulk characteristics and (island-like crystalline silicon film 3
08＼ In order to improve the interface characteristics of the gate insulating film 311), annealing was performed at 500 to 600 ° C. for several hours in an inert gas atmosphere.

Subsequently, by the sputtering method,
An aluminum film having a thickness of 300 to 800 nm, for example, 500 nm is formed. Then, the gate electrode 312 is formed by patterning the aluminum film. Further, the surface of the aluminum electrode is anodized to form an oxide layer 314 on the surface. This state corresponds to FIG. The anodization is performed in an ethylene glycol solution containing tartaric acid at 1 to 5%, and the voltage is first increased to 220 V at a constant current, and the state is maintained for 1 hour to complete the process. The thickness of the obtained oxide layer 314 is 200 nm. In addition,
Since the oxide layer 314 has a thickness for forming an offset gate region in a later ion doping process, the length of the offset gate region can be determined in the anodic oxidation process.

Next, impurities (phosphorus) are implanted into the active region by ion doping using the gate electrode 312 and the oxide layer 314 around the gate electrode 312 as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 to 90 kV, for example, 80 kV, and the dose is 1 × 10 4
¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . By this step, the region into which the impurities are implanted becomes
FT source region 317 and drain region 318,
A region which is masked by the gate electrode 312 and its surrounding oxide layer 314 and into which impurities are not implanted later becomes a channel region 316 of the TFT.

Thereafter, as shown in FIG. 3D, annealing is performed by irradiating a laser beam 315 to activate the ion-implanted impurities, and at the same time, a portion where crystallinity is deteriorated in the above-described impurity introducing step is reduced. Improves crystallinity. At this time, a XeCl excimer laser (wavelength 308 nm, pulse width 40 sec.) Is used as the laser to be used, and the energy density I is 50 to 400 mJ / cm ² , preferably 200 to 250 mJ / cm ² ,
Shot irradiation was performed. The source region 317 and the drain region 3 into which the N-type impurity (phosphorus) thus formed is introduced.
The sheet resistance of No. 18 was 200 to 300 Ω / □.

Subsequently, a silicon oxide film having a thickness of about 600 nm is formed as an interlayer insulating film 319. When the silicon oxide film is formed by using TEOS as a raw material by a plasma CVD method with oxygen or a low pressure CVD method or a normal pressure CVD method with ozone, a good interlayer insulating film having excellent step coverage can be obtained. A film is obtained.

Next, a contact hole is formed in the interlayer insulating film 319, and a source electrode / source wiring 320 and a drain electrode / drain wiring 321 of the TFT are formed using a metal material, for example, a two-layer film of titanium nitride and aluminum. . The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer.
Finally, annealing is performed at 350 ° C. for about 1 hour in a hydrogen atmosphere at 1 atm to complete the N-channel TFT portion 324 shown in FIG.

When this TFT is used as an element for switching a pixel electrode, the source electrode / source wiring 32
0 or the drain electrode / drain wiring 321 is connected to a pixel electrode made of a transparent conductive film such as ITO, and a signal is input from the other electrode. In the case where the present TFT is used for a thin film integrated circuit, a contact hole may be formed also on the gate electrode 312 and a necessary wiring may be provided.

The N-channel TFT manufactured according to the above embodiment has a field-effect mobility of 100 to 150 cm.
² / Vs, showing good characteristics of a threshold voltage of ^1-2 V,
The leakage current in the TFT off region was as small as several pA, and the characteristics were excellent in stability and reliability.

(Embodiment 3) A third embodiment using the present invention will be described. In this embodiment, an N-channel TFT and a P-channel TF which form a peripheral driving circuit of an active matrix type liquid crystal display device and a general thin film integrated circuit are used.
A process for manufacturing a circuit having a CMOS structure in which Ts are connected in a complementary manner on a glass substrate will be described.

FIG. 4 is a plan view showing an outline of a manufacturing process of the TFT described in this embodiment. FIG. 5 is a diagram of FIG.
It is sectional drawing cut | disconnected by A ', and a process advances sequentially according to (A)-> (E). FIG. 5E is a completed view of the CMOS circuit according to the present embodiment, which is composed of an N-channel TFT section 424 and a P-channel TFT section 425.

First, as shown in FIG. 5A, a glass substrate 401 having a thickness of 30
A base film 402 of about 0 nm made of silicon oxide is formed. This silicon oxide film is provided to prevent diffusion of impurities from the glass substrate. Next, by a low pressure CVD method or a plasma CVD method,
For example, a 50 nm intrinsic (I-type) amorphous silicon film (a-
(Si film) 403 is formed.

Next, a photosensitive resin (photoresist) is applied on the a-Si film 403, and is exposed and developed to form a mask 4
04. Due to the through holes in the mask 404 made of photoresist, a
-The Si film 403 is exposed. That is, when the state of FIG. 5A is viewed from above, the a-Si
The film 403 is exposed, and the other portions are in a state of being remasked by the photoresist.

Next, as shown in FIG. 5A, a thin film 405 of nickel is deposited on the surface of the glass substrate 401. In this example, the distance between the deposition source and the substrate was made larger than usual, and the deposition rate was reduced, so that the thickness of the nickel thin film 405 was controlled to be about 1 to 2 nm. At this time, when the surface density of nickel on the substrate 401 was actually measured, it was about 1 × 10 ¹³ atoms / cm ² . And a mask 4 made of photoresist.
04, the nickel thin film 405 on the mask 404 is lifted off, and the a-Si film 40 in the region 400 is lifted off.
In No. 3, this means that a trace amount of nickel was selectively added. Then, this is annealed in an inert atmosphere, for example, at a heating temperature of 550 ° C. for 16 hours to be crystallized.

At this time, in the region 400, a-Si
With the nickel added to the surface of the film 403 as a nucleus, crystallization of the amorphous silicon film 403 occurs in a direction perpendicular to the glass substrate 401, and a crystalline silicon film 403a is formed. In the peripheral region of the region 400, crystal growth is performed in a lateral direction (a direction parallel to the substrate) from the region 400 as shown by an arrow 406 in FIG. The formed crystalline silicon film 403b is formed. Further, the amorphous silicon film 403 as the other region remains as the amorphous silicon film region 403c. The crystalline silicon film 403 grown in the lateral direction
The nickel concentration in b was about 1 × 10 ¹⁷ atoms / cm ³ . In the above crystal growth, the distance of crystal growth in the direction parallel to the substrate indicated by arrow 406 is 80 μm.
m.

Thereafter, as shown in FIG. 5B, laser light 407 is applied to the crystalline silicon films 403a and 403a.
3b is recrystallized. At this time, a XeCl excimer laser (wavelength: 308 nm, pulse width: 40 nsec.) Was used as a laser beam. The irradiation condition of the laser beam 407 is such that the substrate is irradiated at a temperature of 200 to 500 ° C.
Heat to 00 ° C, energy density 200-350mJ /
cm ² , for example, 300 mJ / cm ² . Laser light 4
07 is sequentially scanned with respect to the substrate surface, and 1 point is set to any one point of the crystalline silicon films 403a and 403b.
The scanning pitch was set so that laser irradiation was performed 0 times.
This step allows the crystalline silicon regions 403a and 40
3b is heated above its melting point, melts and solidifies, and is partially recombined as a seed crystal, resulting in better crystallinity. Further, the a-Si region 403c is crystallized into a crystalline silicon film 403d. Here, when the average surface roughness Ra of the surface of the crystalline silicon film 403b was measured by an atomic force microscope (AFM), the value was about 7 to 8 nm.

After that, as shown in FIG. 5C, the other crystalline silicon film is etched and removed by patterning so that the crystalline silicon film 403b region becomes an active region (element region) of a later TFT. To separate the elements,
The island-shaped crystalline silicon films 408n and 408p are formed.

Then, in this state, the glass substrate 401 is introduced into the CVD apparatus, and first, the crystalline silicon film 408n,
Light etching of the surface of 08p is performed. This light etching step was performed by plasma etching using RF plasma using, for example, CF ₄ and O ₂ as an etching gas. The etching rate in the plasma etching performed in this embodiment is about 30 nm / min, and the etching time is 40 sec. By setting, the crystalline silicon films 408n and 408p were etched by about 20 nm from the outermost surface. Thereby, the island-shaped crystalline silicon film 408 is formed.
The film thickness of n, 408p was 30 nm. At this time, the surface of the crystalline silicon film 408 was measured by an atomic force microscope (AFM). As a result, the average surface roughness Ra was about 2 to 3 nm, which was greatly reduced as compared with the initial value.

Subsequently, in the same chamber of the CVD apparatus, the residual concentration of CF ₄ gas was reduced and (the silicon film
After performing a plasma treatment with oxygen to improve the interface characteristics of the gate insulating film, the thickness is 20 to 150 n so as to continuously cover the island-shaped crystalline silicon films 408 n and 408 p.
m, a 100 nm silicon oxide film is formed here as the gate insulating film 411. For the formation of the silicon oxide film, TEOS (Tetra Ethoxy Ortho) is used here.
(Silicate) as a raw material and a substrate temperature of 150 to 600 ° C, preferably 300 to 400 ° C, together with oxygen.
Decomposed and deposited by RF plasma CVD. After the film formation, in order to improve the bulk characteristics of the gate insulating film 411 itself and the interface characteristics of the (crystalline silicon films 408n, 408p＼gate insulating film 411), the film thickness is set to 500 to 6 in an inert gas atmosphere.
Annealing was performed at 00 ° C. for several hours.

Next, as shown in FIG. 5D, a thickness of 400 to 800 nm, for example, 50
A film of 0 nm aluminum (containing 0.1 to 2% silicon) is formed, and the aluminum film is patterned to form gate electrodes 412n and 412p.

Next, the gate electrodes 412 are formed on the island-shaped crystalline silicon films 408n and 408p by ion doping.
Impurities (phosphorus and boron) are implanted using n, 412p as a mask. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) are used as the doping gas. In the former case, the accelerating voltage is 60 to 90 kV, for example, 80 kV, and in the latter case, the accelerating voltage is 40 kV to 80 kV, for example, 65 kV. Is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, phosphorus is 2 × 10 ¹⁵ cm ⁻² and boron is 5 × 10 ¹⁵ cm ⁻² . By this step, the gate electrodes 412n, 412p
The regions which are not masked and into which the impurities are not implanted become channel regions 416n and 416p of the TFT later. At the time of doping, each element is selectively doped by covering a region not requiring doping with a photoresist.

As a result, a source region 417n and a drain region 418n into which an N-type impurity has been implanted, and a source region 417p and a drain region 418p into which a P-type impurity has been implanted are formed, as shown in FIGS. 5D and 5E. As described above, the N-channel TFT section 424 and the P-channel TFT section 425
And can be formed. This state is viewed from above the substrate, as shown in FIG. 4. Here, in the island-shaped crystalline silicon films 408n and 408p, the arrow 406 indicating the crystal growth direction and the moving direction of the carrier (the direction from the source to the drain) are shown. They are arranged so as to be parallel. By adopting such an arrangement, a TFT having higher mobility can be obtained.

Thereafter, as shown in FIG. 5D, annealing is performed by irradiation with laser light 415 to activate the ion-implanted impurities. As the laser light, Xe
Cl excimer laser (wavelength 308 nm, pulse width 40
sec. ), And the laser beam was irradiated at an energy density of 250 mJ / cm ² for four shots per location.

Subsequently, as shown in FIG.
Using a silicon oxide film of 00 nm as the interlayer insulating film 419, T
Formed by a plasma CVD method using EOS as a raw material,
A contact hole is formed in this, and a TFT is formed by a metal material, for example, a two-layer film of titanium nitride and aluminum.
The source electrode / source wiring 420, the source / drain electrode 421, and the drain electrode / drain wiring 422 are formed. Finally, at 350 ° C. under a hydrogen atmosphere of 1 atm.
Anneal for about one hour to obtain an N-channel TFT unit 4
24 and a P-channel type TFT portion 425 are completed.

The CMO fabricated according to the above embodiment
In the S structure circuit, the field-effect mobility of each TFT is 150 to ²⁰⁰ cm ² / V for an N-channel TFT.
The s-type and P-channel type TFTs are as high as 80 to 120 cm ² / Vs, and the threshold voltage is 0 to 1 V for the N-channel type TFTs, and is −2 to -3 V for the P-channel type TFTs. Furthermore, a highly reliable CMOS structure circuit was obtained with almost no characteristic deterioration due to repeated measurement.

Although the third embodiment according to the present invention has been specifically described above, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. is there.

For example, in the above three embodiments,
The silicon film surface serving as an active region is plasma-etched using a CVD apparatus, and then a gate insulating film is continuously formed by a plasma CVD method. Alternatively, a PVD method such as sputtering may be used. In the case where a sputtering apparatus is used, the gate insulating film may be formed by sputtering after the outermost surface of the crystalline silicon film is physically shaved in a reverse sputtering step. Further, as the treatment before the formation of the gate insulating film, the combined use of the above-described oxygen plasma treatment and hydrogen plasma treatment is more effective.

When the a-Si film is crystallized, XeCl
Although an excimer laser was used, the same effect can be obtained, of course, in the case of crystallization by irradiation of various other intense light, and the same applies to a KrF excimer laser having a wavelength of 248 nm or a continuous oscillation Ar laser having a wavelength of 488 nm. It is.

In the second and third embodiments, the solid-phase crystal growth method employs a method of crystallizing in a short time using a catalytic element. The same effect can be obtained by using the method. In the second and third embodiments, as a method of introducing nickel as a catalyst element, a method of applying an aqueous solution in which a nickel salt is dissolved on the surface of an amorphous silicon film, or a method of forming a nickel thin film by a vapor deposition method. In this method, a small amount of nickel is added to cause crystal growth. However, a method in which nickel is introduced into the substrate surface before the first amorphous silicon film is formed, and nickel is diffused from the lower layer of the amorphous silicon film to perform crystal growth. That is, crystal growth may be performed from the upper surface side or the lower surface side of the amorphous silicon film. Also, as a method for introducing nickel,
In addition, various methods can be used. For example, as a solvent for dissolving a nickel salt, a method of diffusing an SOG (spin-on-glass) material from a SiO ₂ film as a solvent is also effective, a method of forming a thin film by a sputtering method or a plating method, or a method of directly introducing the ion doping method. You can also use other methods. Further, as impurity metal elements that promote crystallization, Co, Pd, P
The effect can be obtained by using t, Cu, Ag, Au, In, Sn, Al, and Sb.

Further, as an application of the present invention, in addition to an active matrix type substrate for liquid crystal display, for example, a contact type image sensor, a thermal head with a built-in driver, and a driver built-in type using an organic EL as a light emitting element. An optical writing element, a display element, a three-dimensional IC, and the like can be considered. By using the present invention, high performance such as high speed and high resolution of these elements is realized. Further, the present invention is not limited to the MOS transistors described in the above embodiments,
It can be widely applied to all semiconductor processes including a bipolar transistor and an electrostatic induction transistor using a crystalline semiconductor as an element material.

[0103]

According to the present invention, a high-quality crystalline silicon thin film having no surface irregularities can be obtained, and a MOS
In the type transistor, very good interface characteristics can be obtained at the interface between the active region (the crystalline silicon film and the gate insulating film). As a result, a very high performance and highly reliable thin film semiconductor device can be realized.
In particular, in a liquid crystal display device, it is possible to eliminate display unevenness caused by the silicon film surface unevenness, improve the switching characteristics of the pixel TFT, and achieve high performance and high integration required for the TFT constituting the peripheral drive circuit portion. -A full driver monolithic active matrix substrate that constitutes the active matrix section and peripheral drive circuit section on the board can be realized.
The module can be made compact, high performance, and low cost.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an outline of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a view showing a manufacturing process of the first embodiment in the order of processes.

FIG. 3 is a diagram showing a manufacturing process of a second embodiment in the order of processes.

FIG. 4 is a diagram showing an outline of a third embodiment.

FIG. 5 is a view showing the manufacturing steps of the third embodiment in the order of steps.

FIG. 6 shows an atomic force microscope (AF) of a crystalline silicon film surface.
M) is a diagram showing the image sketched below.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Substrate 102 Underlayer 103 Amorphous silicon film 104 Intense light 105 Crystalline silicon film 106 Crystal grain 107 Crystal grain boundary 108 Ridge 109 Crystalline silicon film 110 Oxide film 111 Interface 201, 301, 401 Glass substrate 202, 302, 402 Underlayers 203, 303, 403 Amorphous silicon (a-Si)
Film 404 Mask 305 Aqueous solution 405 Nickel thin film 406 Arrows 207, 307, 407 Laser light 208, 308, 408 Island crystalline silicon film 209 Mask 210 Impurities 211, 311, 411 Gate insulating film 212, 312, 412 Top of gate electrode 213 Electrode 314 Oxide layer 315, 415 Laser light 216, 316, 416 Channel region 217, 317, 417 Source region 218 Drain region and lower electrode region 318, 418 Drain region 219, 319, 419 Interlayer insulating film 220 Source electrode 320, 420 Source electrode / source wiring 321, 422 Drain electrode / drain wiring 421 Source / drain electrode 223 Pixel electrode 224, 324, 424 N-channel TFT section 425 P-channel TFT section 226 Auxiliary capacity (Cs) area

Claims (11)

[Claims] 1. A MOS type semiconductor device in which an active region is formed on a silicon film having crystallinity formed on a substrate having an insulating surface, wherein the active region is formed of a silicon film. A method for manufacturing a semiconductor device, comprising: forming a thin film on the outermost surface, and exposing the film to an upper insulating film without exposing the film to the atmosphere. 2. The method according to claim 1, wherein the insulating film forms a gate insulating film of a MOS type thin film transistor, and a surface of the active region is formed by MO.
2. The method according to claim 1, wherein the semiconductor device is a channel surface of an S-type thin film transistor. 3. A semiconductor device comprising a MOS type thin film transistor for driving a plurality of pixel electrodes on a substrate having an insulating surface, wherein each of the thin film transistors is connected to an auxiliary capacitance component in parallel with a liquid crystal capacitance by the pixel electrode. An active region of each of the thin film transistors and a lower electrode of the auxiliary capacitance component are formed of the same layer of crystalline silicon film,
And the gate insulating film of the thin film transistor and the insulating film of the auxiliary capacitance component are formed of the same insulating film, the crystalline silicon film, after the outermost surface is etched thin, without exposing to the air, A method of manufacturing a semiconductor device, wherein the semiconductor device is formed by being covered with the insulating film. 4. The silicon film constituting the active region is obtained by irradiating the amorphous silicon film with strong light such as an excimer laser,
4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is crystallized in the melting and solidifying process. 5. The method according to claim 1, wherein the silicon film constituting the active region is formed by introducing a catalytic element for promoting crystallization into an amorphous silicon film and crystallizing the amorphous silicon film in a solid phase crystal growth step by heat treatment. 4. The method according to claim 1, wherein the film is further recrystallized by irradiating the film with strong light such as an excimer laser. 6. The method for manufacturing a semiconductor device according to claim 1, wherein an average surface roughness Ra of the crystalline silicon film surface after the thin film etching is 5 nm or less. 7. The film thickness T of the crystalline silicon film to be etched has a relationship of T> Ra with respect to the average surface roughness Ra of the crystalline silicon film surface before the thin film etching. 4. The method for manufacturing a semiconductor device according to claim 1, wherein 8. The method according to claim 4, wherein the average surface roughness Ra is a value measured with an atomic force microscope (AFM) for a measurement area of 10 μm □ or less. A method for manufacturing a semiconductor device. 9. The method of performing thin film etching, comprising:
A method according to claim 1 or 3, wherein to be characterized to be performed by dry etching reactive with fluoride gases such as ₄ or NF _3. 10. The step of thin-film etching the surface of the crystalline silicon film and the step of forming and covering an insulating film on the surface of the crystalline silicon film are performed in the same pressure reducing device. 4. The method of manufacturing a semiconductor device according to claim 1, wherein 11. A method for forming a thin film on the outermost surface of the crystalline silicon film, exposing the newly exposed surface of the crystalline silicon film to a plasma atmosphere containing at least oxygen or hydrogen, and then forming the insulating film. 4. The method according to claim 1, further comprising a step of covering a surface of the crystalline silicon film.