JPH10134523A5 - - Google Patents

Info

Publication number
JPH10134523A5
JPH10134523A5 JP1997256401A JP25640197A JPH10134523A5 JP H10134523 A5 JPH10134523 A5 JP H10134523A5 JP 1997256401 A JP1997256401 A JP 1997256401A JP 25640197 A JP25640197 A JP 25640197A JP H10134523 A5 JPH10134523 A5 JP H10134523A5
Authority
JP
Japan
Prior art keywords
signal
phase
locked loop
phase locked
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997256401A
Other languages
English (en)
Japanese (ja)
Other versions
JP3967800B2 (ja
JPH10134523A (ja
Filing date
Publication date
Priority claimed from EP96306940A external-priority patent/EP0831483B1/en
Application filed filed Critical
Publication of JPH10134523A publication Critical patent/JPH10134523A/ja
Publication of JPH10134523A5 publication Critical patent/JPH10134523A5/ja
Application granted granted Critical
Publication of JP3967800B2 publication Critical patent/JP3967800B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP25640197A 1996-09-24 1997-09-22 信号処理装置 Expired - Fee Related JP3967800B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP96306940A EP0831483B1 (en) 1996-09-24 1996-09-24 Data processing apparatus and methods
GB96306940.6 1996-09-24

Publications (3)

Publication Number Publication Date
JPH10134523A JPH10134523A (ja) 1998-05-22
JPH10134523A5 true JPH10134523A5 (enExample) 2005-06-02
JP3967800B2 JP3967800B2 (ja) 2007-08-29

Family

ID=8225095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25640197A Expired - Fee Related JP3967800B2 (ja) 1996-09-24 1997-09-22 信号処理装置

Country Status (4)

Country Link
US (1) US5896067A (enExample)
EP (1) EP0831483B1 (enExample)
JP (1) JP3967800B2 (enExample)
DE (1) DE69623284T2 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69617677T2 (de) * 1996-09-24 2002-08-08 Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto Datenverarbeitungsgerät und -verfahren
JPH11154377A (ja) * 1997-09-17 1999-06-08 Sony Corp データ記録装置及び方法、並びにデータ再生装置及び方法
US6477200B1 (en) * 1998-11-09 2002-11-05 Broadcom Corporation Multi-pair gigabit ethernet transceiver
US6771725B2 (en) * 1998-11-09 2004-08-03 Broadcom Corporation Multi-pair gigabit ethernet transceiver
KR20000042571A (ko) * 1998-12-26 2000-07-15 전주범 디지탈 브이씨알의 재생 등화기
JP3767238B2 (ja) * 1999-03-26 2006-04-19 松下電器産業株式会社 信号処理装置
US6484286B1 (en) * 1999-09-01 2002-11-19 Lsi Logic Corporation Error signal calculation from a Viterbi output
US7333570B2 (en) 2000-03-14 2008-02-19 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US6630868B2 (en) * 2000-07-10 2003-10-07 Silicon Laboratories, Inc. Digitally-synthesized loop filter circuit particularly useful for a phase locked loop
US6701140B1 (en) * 2000-09-14 2004-03-02 3Com Corporation Digital receive phase lock loop with cumulative phase error correction and dynamically programmable correction rate
GB2377349B (en) * 2001-07-07 2004-10-13 Hewlett Packard Co Adaptive filter control
JP3808343B2 (ja) * 2001-10-03 2006-08-09 三菱電機株式会社 Ｐｌｌ回路
US6549079B1 (en) 2001-11-09 2003-04-15 Analog Devices, Inc. Feedback systems for enhanced oscillator switching time
GB2383697A (en) * 2001-12-27 2003-07-02 Zarlink Semiconductor Inc Method of speeding lock of PLL
US8306176B2 (en) * 2002-06-19 2012-11-06 Texas Instruments Incorporated Fine-grained gear-shifting of a digital phase-locked loop (PLL)
US7839178B2 (en) * 2002-08-20 2010-11-23 Seagate Technology Llc High speed digital phase/frequency comparator for phase locked loops
US7126378B2 (en) 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US7092472B2 (en) * 2003-09-16 2006-08-15 Rambus Inc. Data-level clock recovery
US7397848B2 (en) * 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US7233164B2 (en) * 2003-12-17 2007-06-19 Rambus Inc. Offset cancellation in a multi-level signaling system
US7738617B1 (en) 2004-09-29 2010-06-15 Pmc-Sierra, Inc. Clock and data recovery locking technique for large frequency offsets
US11153129B1 (en) * 2020-06-01 2021-10-19 International Business Machines Corporation Feedforward equalizer with programmable roaming taps
CN117249846B (zh) * 2023-11-17 2024-02-09 浙江明哲电子科技有限公司 一种编码器预解码处理方法、系统及存储介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4231071A (en) * 1978-07-17 1980-10-28 Digital Equipment Corporation Reader for data recorded on magnetic disks at plural densities
US4590602A (en) * 1983-08-18 1986-05-20 General Signal Wide range clock recovery circuit
US4672637A (en) * 1985-07-31 1987-06-09 Halpern Peter H Adaptive bit synchronizer
US4847876A (en) * 1986-12-31 1989-07-11 Raytheon Company Timing recovery scheme for burst communication systems
US4872155A (en) * 1987-03-13 1989-10-03 Pioneer Electronic Corporation Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock
US4896336A (en) * 1988-08-29 1990-01-23 Rockwell International Corporation Differential phase-shift keying demodulator
US5065413A (en) * 1989-12-09 1991-11-12 Sony Corporation Phase locked loop circuit
US5015970A (en) * 1990-02-15 1991-05-14 Advanced Micro Devices, Inc. Clock recovery phase lock loop having digitally range limited operating window
US5159292A (en) * 1992-02-25 1992-10-27 Thomson Consumer Electronics, Inc. Adaptive phase locked loop
GB9324918D0 (en) * 1993-12-04 1994-01-26 Hewlett Packard Ltd High-density data recording
US5512860A (en) * 1994-12-02 1996-04-30 Pmc-Sierra, Inc. Clock recovery phase locked loop control using clock difference detection and forced low frequency startup

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