JPH1013036A - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JPH1013036A
JPH1013036A JP8163152A JP16315296A JPH1013036A JP H1013036 A JPH1013036 A JP H1013036A JP 8163152 A JP8163152 A JP 8163152A JP 16315296 A JP16315296 A JP 16315296A JP H1013036 A JPH1013036 A JP H1013036A
Authority
JP
Japan
Prior art keywords
organic resin
thin film
multilayer wiring
resin insulating
film wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8163152A
Other languages
Japanese (ja)
Inventor
Takeshi Kume
健士 久米
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP8163152A priority Critical patent/JPH1013036A/en
Publication of JPH1013036A publication Critical patent/JPH1013036A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To make a wiring conductor as a thin-film wiring conductor formed by the thin-film formation technique, at the same time incorporate a capacitance element inside the conductor for miniaturization, and to provide a multilayer wiring board with a high-density wiring. SOLUTION: A wiring board consists of an insulation substrate 1 with a through hole 5 that penetrates through both upper and lower main surfaces, a conductive layer 6 led from the upper surface of the insulation substrate 1 to the lower surface via the inner wall of the through hole 5, an organic resin filling body 7 filled into the inside of the through hole 6, and a multilayer wiring part 4 deposited at least on one main surface of the insulation substrate 1 and alternately laminated in a plurality of organic resin insulation layers 3a, 3b, and 3c and a plurality of thin-film wiring conductors 4a, 4b, and 4c, and at the same time where one part of the thin-film wiring conductor 4a is electrically connected to the conductive layer 6. In this case, at least the above organic resin insulation layer 3b contains a dielectric material filler with a specific specific dielectric constant being 20 or larger, an organic resin insulation layer 3b containing the dielectric material filler is held oppositely by one portion of the thin-film wiring conductors 4a and 4b being provided on the upper and lower surfaces for forming a capacity element A, and at the same time, the capacitive element A is connected to the thin-film wiring conductors 4a and 4b electrically.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多層配線基板に関
し、より詳細には混成集積回路装置や半導体素子を収容
する半導体素子収納用パッケージ等に使用される多層配
線基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board used for a hybrid integrated circuit device, a semiconductor element housing package for housing a semiconductor element, and the like.

【0002】[0002]

【従来の技術】従来、半導体素子等の能動部品や容量素
子、抵抗器等の受動部品を多数搭載し、所定の電子回路
を構成するようになした混成集積回路装置は、通常、絶
縁基板の内部及び表面にタングステン、モリブデン等の
高融点金属粉末から成る配線導体を形成した構造の配線
基板を準備し、次に前記配線基板の表面に半導体素子や
容量素子、抵抗器等を搭載取着するとともに該半導体素
子等の電極を前記配線導体に接続することによって混成
集積回路装置となる。
2. Description of the Related Art Conventionally, a hybrid integrated circuit device which mounts a large number of active components such as semiconductor devices and passive components such as capacitors and resistors to form a predetermined electronic circuit is usually provided with an insulating substrate. A wiring board having a structure in which a wiring conductor made of a high melting point metal powder such as tungsten or molybdenum is formed inside and on the surface is prepared, and then a semiconductor element, a capacitor element, a resistor, and the like are mounted on the surface of the wiring board. At the same time, by connecting an electrode of the semiconductor element or the like to the wiring conductor, a hybrid integrated circuit device is obtained.

【0003】かかる従来の混成集積回路装置等に使用さ
れる配線基板は一般にセラミックスの積層技術及びスク
リーン印刷法等の厚膜技術を採用することによって製作
されており、具体的には以下の方法によって製作されて
いる。
[0003] Wiring boards used in such conventional hybrid integrated circuit devices and the like are generally manufactured by employing a ceramic lamination technology and a thick film technology such as a screen printing method, and more specifically, by the following method. Has been produced.

【0004】即ち、 (1)先ず、アルミナ等の電気絶縁性に優れたセラミッ
ク原料粉末に有機溶剤、溶媒を添加混合して複数枚のセ
ラミック生シートを得るとともに該各セラミック生シー
トの上下面にタングステン、モリブデン等の高融点金属
粉末から成る導電ペーストを従来周知のスクリーン印刷
法等の厚膜手法を採用することによって所定パターンに
印刷塗布する。
[0004] (1) First, an organic solvent and a solvent are added to and mixed with a ceramic raw material powder such as alumina which is excellent in electrical insulation to obtain a plurality of ceramic green sheets, and the raw ceramic sheets are formed on the upper and lower surfaces of each ceramic raw sheet. A conductive paste composed of a high melting point metal powder such as tungsten or molybdenum is printed and applied in a predetermined pattern by employing a conventionally known thick film method such as a screen printing method.

【0005】(2)次に前記各セラミック生シートを積
層し、積層体を得るとともにこれを約1500℃の温度
で焼成し、内部及び表面にタングステン、モリブデン等
の高融点金属粉末から成る配線導体を有する絶縁基板を
得る。
(2) Each of the above ceramic green sheets is laminated to obtain a laminate, which is fired at a temperature of about 1500 ° C., and a wiring conductor made of a high melting point metal powder such as tungsten, molybdenum or the like inside and on the surface. Is obtained.

【0006】(3)そして最後に、前記配線導体のう
ち、大気中に露出する表面にニッケル及び金等の耐蝕性
に優れ、良導電性で、半田等のロウ材と濡れ性(反応
性)の良い金属をめっき法により被着させ、これによっ
て製品としての配線基板が完成する。
(3) Finally, the surface of the wiring conductor exposed to the atmosphere is excellent in corrosion resistance such as nickel and gold, has good conductivity, and has wettability (reactivity) with a brazing material such as solder. A good metal is deposited by a plating method, thereby completing a wiring board as a product.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、この従
来の配線基板においては、配線導体がタングステンやモ
リブデン等の高融点金属粉末から成る導電ペーストをス
クリーン印刷法等の厚膜手法を採用し所定パターンに印
刷塗布することによって形成されており、配線導体の微
細化が困難で配線導体を高密度に形成することができな
いという欠点を有していた。
However, in this conventional wiring board, the wiring conductor is formed into a predetermined pattern by applying a conductive paste made of a high melting point metal powder such as tungsten or molybdenum by a screen printing method or the like. It is formed by printing and applying, and has a drawback that it is difficult to miniaturize the wiring conductor and it is not possible to form the wiring conductor at high density.

【0008】またこの従来の配線基板は表面に半導体素
子等の能動部品や容量素子、抵抗器等の受動部品が多数
搭載され、部品の搭載数に応じて大型化してしまうとい
う欠点も有していた。
In addition, the conventional wiring board has a drawback that active components such as semiconductor devices and passive components such as capacitors and resistors are mounted on the surface thereof, and the size thereof increases in accordance with the number of mounted components. Was.

【0009】[0009]

【課題を解決するための手段】本発明は上述の欠点に鑑
み案出されたもので、その目的は配線導体を薄膜形成技
術により形成される薄膜配線導体とするとともに内部に
容量素子を内蔵させることによって小型にして、且つ配
線が高密度の多層配線基板を提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object the purpose of making a wiring conductor a thin film wiring conductor formed by a thin film forming technique and incorporating a capacitive element therein. Accordingly, it is an object of the present invention to provide a multilayer wiring board which is reduced in size and has a high density of wiring.

【0010】本発明は、上下両主面に貫通する貫通孔を
有する絶縁基板と、該絶縁基板の上面から貫通孔内壁を
経て下面に導出する導電層と、前記貫通孔の内部に充填
された有機樹脂充填体と、前記絶縁基板の少なくとも一
主面上に被着され、複数の有機樹脂絶縁層と複数の薄膜
配線導体とを交互に多層に配設するとともに薄膜配線導
体の一部が前記導電層に電気的に接続されている多層配
線部とから成る多層配線基板であって、前記有機樹脂絶
縁層の少なくとも一層に比誘電率が20以上の誘電物フ
ィラーを含有させるとともに該誘電物フィラーが含有さ
れている有機樹脂絶縁層をその上下両面に配設されてい
る薄膜配線導体の一部で対向挟持させることによって容
量素子を形成するとともに該容量素子を薄膜配線導体間
に電気的接続させたことを特徴とするものである。
According to the present invention, there is provided an insulating substrate having a through hole penetrating both upper and lower main surfaces, a conductive layer extending from the upper surface of the insulating substrate to the lower surface through the inner wall of the through hole, and filled in the through hole. The organic resin filler, which is attached on at least one main surface of the insulating substrate, and a plurality of organic resin insulating layers and a plurality of thin film wiring conductors are alternately arranged in a multilayer and a part of the thin film wiring conductor is A multilayer wiring board comprising a multilayer wiring portion electrically connected to a conductive layer, wherein at least one of the organic resin insulating layers contains a dielectric filler having a relative dielectric constant of 20 or more, and the dielectric filler Is formed between the thin film wiring conductors by electrically sandwiching the organic resin insulating layer containing the same between the thin film wiring conductors disposed on the upper and lower surfaces thereof. It is characterized in.

【0011】また本発明は、前記誘電物フィラーの粒径
が直径0.5μm乃至50μmのチタン酸バリウム、チ
タン酸ストロンチウムの少なくとも1種よりなっている
ことを特徴とするものである。
Further, the present invention is characterized in that the dielectric filler has a particle size of at least one of barium titanate and strontium titanate having a diameter of 0.5 μm to 50 μm.

【0012】本発明の多層配線基板によれば、絶縁基板
上に薄膜形成技術によって配線を形成したことから配線
の微細化が可能となり、配線を極めて高密度に形成する
ことが可能となる。
According to the multilayer wiring board of the present invention, since the wiring is formed on the insulating substrate by the thin film forming technique, the wiring can be miniaturized, and the wiring can be formed at an extremely high density.

【0013】また本発明の多層配線基板によれば、有機
樹脂絶縁層の少なくとも一層に比誘電率が20以上の誘
電物フィラーを含有させるとともに該誘電物フィラーが
含有されている有機樹脂絶縁層をその上下両面に配設さ
れている薄膜配線導体の一部で対向挟持させることによ
って容量素子を形成するとともに該容量素子を薄膜配線
導体間に電気的接続させたことから多層配線基板に半導
体素子や容量素子、抵抗器等の部品を搭載して混成集積
回路装置等となす場合、多層配線基板に別途、容量素子
を多数実装する必要はなく、その結果、多層配線基板に
実装される部品の数が減り、混成集積回路装置等を小型
となすことが可能となる。
Further, according to the multilayer wiring board of the present invention, at least one of the organic resin insulating layers contains a dielectric filler having a relative dielectric constant of 20 or more, and the organic resin insulating layer containing the dielectric filler is provided. The capacitive element is formed by opposing and sandwiching a part of the thin film wiring conductors disposed on the upper and lower surfaces thereof, and the capacitive element is electrically connected between the thin film wiring conductors. When a component such as a capacitor and a resistor is mounted to form a hybrid integrated circuit device or the like, it is not necessary to separately mount a large number of capacitors on the multilayer wiring board. As a result, the number of components mounted on the multilayer wiring board is reduced. And the size of the hybrid integrated circuit device and the like can be reduced.

【0014】[0014]

【発明の実施の形態】次に、本発明を添付図面に基づき
詳細に説明する。図1は、本発明の多層配線基板の一実
施例を示し、1は絶縁基板、2は多層配線部である。
Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a multilayer wiring board according to the present invention, wherein 1 is an insulating substrate, and 2 is a multilayer wiring section.

【0015】前記絶縁基板1はその上面に3つの有機樹
脂絶縁層3a、3b、3cと3つの層の薄膜配線導体4
a、4b、4cを交互に多層に配設して成る多層配線部
2が形成されており、該多層配線部2を支持する支持部
材として作用する。
The insulating substrate 1 has three organic resin insulating layers 3a, 3b, 3c and three thin film wiring conductors 4 on its upper surface.
The multilayer wiring portion 2 is formed by alternately arranging a, 4b and 4c in multiple layers, and functions as a support member for supporting the multilayer wiring portion 2.

【0016】前記絶縁基板1は酸化アルミニウム質焼結
体やムライト質焼結体等の酸化物系セラミックス、或い
は表面に酸化物膜を有する窒化アルミニウム質焼結体、
炭化珪素質焼結体等の非酸化物系セラミックス、更には
ガラス繊維を織る込んだ布にエポキシ樹脂を含浸させた
ガラスエポキシ樹脂等の電気絶縁材料で形成されてお
り、例えば、酸化アルミニウム質焼結体で形成されてい
る場合には、アルミナ、シリカ、カルシア、マグネシア
等の原料粉末に適当な有機溶剤、溶媒を添加混合して泥
漿状となすとともにこれを従来周知のドクターブレード
法やカレンダーロール法を採用することによってセラミ
ックグリーンシート(セラミック生シート)を形成し、
しかる後、前記セラミックグリーンシートに適当な打ち
抜き加工を施し、所定形状となすとともに高温(約16
00℃)で焼成することによって、或いはアルミナ等の
原料粉末に適当な有機溶剤、溶媒を添加混合して原料粉
末を調整するとともに該原料粉末をプレス成形機によっ
て所定形状に成形し、最後に前記成形体を約1600℃
の温度で焼成することによって製作され、またガラスエ
ポキシ樹脂から成る場合は、例えばガラス繊維を織り込
んだ布にエポキシ樹脂の前駆体を含浸させるとともに該
エポキシ樹脂前駆体を所定の温度で熱硬化させることに
よって製作される。
The insulating substrate 1 is made of an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or an aluminum nitride sintered body having an oxide film on its surface.
It is made of an electrically insulating material such as a non-oxide ceramic such as a silicon carbide sintered body, and a glass epoxy resin in which a cloth woven with glass fibers is impregnated with an epoxy resin. In the case of a compact, a suitable organic solvent and a solvent are added to raw material powders such as alumina, silica, calcia, and magnesia to form a slurry by mixing and adding the same to a conventionally known doctor blade method or calender roll. By forming the ceramic green sheet (ceramic raw sheet) by adopting the method,
Thereafter, the ceramic green sheet is subjected to an appropriate punching process so as to have a predetermined shape and a high temperature (about 16 ° C.).
(00 ° C.) or by mixing a raw material powder such as alumina with an appropriate organic solvent and a solvent to adjust the raw material powder and form the raw material powder into a predetermined shape by a press molding machine. About 1600 ° C
If it is made by firing at a temperature of, and made of glass epoxy resin, for example, impregnating the epoxy resin precursor into a cloth woven of glass fibers and heat curing the epoxy resin precursor at a predetermined temperature Produced by

【0017】また前記絶縁基板1には上下両主面に貫通
する孔径が例えば、直径300μm〜500μmの貫通
孔5が形成されており、該貫通孔5の内壁には両端が絶
縁基板1の上下両面に導出する導電層6が被着されてい
る。
The insulating substrate 1 is formed with a through hole 5 having a diameter of, for example, 300 μm to 500 μm, which penetrates the upper and lower main surfaces. Conductive layers 6 leading to both sides are applied.

【0018】前記貫通孔5は後述する絶縁基板1の上面
に形成される多層配線部2の薄膜配線導体4aと外部電
気回路とを電気的に接続する、或いは絶縁基板1の上下
両主面に多層配線部2を配設した場合には両主面の多層
配線部2の薄膜配線導体同士を電気的に接続する導電層
6を形成するための形成孔として作用し、絶縁基板1に
ドリル孔あけ加工法を施すことによって絶縁基板1の所
定位置、所定形状に形成される。
The through hole 5 electrically connects the thin-film wiring conductor 4a of the multilayer wiring portion 2 formed on the upper surface of the insulating substrate 1 to be described later and an external electric circuit, or is formed on both upper and lower main surfaces of the insulating substrate 1. When the multilayer wiring portion 2 is provided, it acts as a forming hole for forming a conductive layer 6 for electrically connecting the thin film wiring conductors of the multilayer wiring portion 2 on both main surfaces, and a drill hole is formed in the insulating substrate 1. A predetermined position and a predetermined shape of the insulating substrate 1 are formed by performing the opening method.

【0019】更に前記貫通孔5の内壁及び絶縁基板1の
上下両面に被着形成されている導電層6は例えば、銅や
ニッケル等の金属材料から成り、従来周知のめっき法及
びエッチン法を採用することによって貫通孔5の内壁に
両端を絶縁基板1の上下両面に導出させた状態で被着形
成される。
The conductive layer 6 formed on the inner wall of the through hole 5 and on the upper and lower surfaces of the insulating substrate 1 is made of a metal material such as copper or nickel. As a result, the inner wall of the through hole 5 is adhered and formed with both ends being led out to the upper and lower surfaces of the insulating substrate 1.

【0020】前記導電層6は絶縁基板1の主面に配設さ
れる多層配線部2の薄膜配線導体3aを外部電気回路に
電気的に接続したり、絶縁基板1の上下両主面に配設さ
れる各々の多層配線部2の薄膜配線導体同士を電気的に
接続する作用をなす。
The conductive layer 6 electrically connects the thin-film wiring conductor 3a of the multilayer wiring portion 2 provided on the main surface of the insulating substrate 1 to an external electric circuit, or is provided on both upper and lower main surfaces of the insulating substrate 1. It functions to electrically connect the thin film wiring conductors of each of the provided multilayer wiring portions 2 to each other.

【0021】また前記絶縁基板1に形成した貫通孔5は
その内部にエポキシ樹脂から成る有機樹脂充填体7が充
填されており、該有機樹脂充填体7によって貫通孔5が
完全に埋められ、同時に有機樹脂充填体7の両端面が絶
縁基板1の上下両主面に被着させた導電層6の面と同一
平面となっている。
The through hole 5 formed in the insulating substrate 1 is filled with an organic resin filler 7 made of epoxy resin. The through hole 5 is completely filled with the organic resin filler 7, and Both end surfaces of the organic resin filler 7 are flush with the surface of the conductive layer 6 attached to the upper and lower main surfaces of the insulating substrate 1.

【0022】前記有機樹脂充填体7は絶縁基板1の上面
及び/又は下面に後述する複数の有機樹脂絶縁層3a、
3b、3cと複数の層の薄膜配線導体4a、4b、4c
とから成る多層配線部2を形成する際、多層配線部2の
各有機樹脂絶縁層3a、3b、3cと各薄膜配線導体4
a、4b、4cの平坦化を維持する作用をなす。
The organic resin filler 7 is provided on the upper and / or lower surface of the insulating substrate 1 with a plurality of organic resin insulating layers 3a to be described later.
3b, 3c and a plurality of layers of thin film wiring conductors 4a, 4b, 4c
When the multi-layer wiring portion 2 is formed, each organic resin insulating layer 3a, 3b, 3c of the multi-layer wiring portion 2 and each thin-film wiring conductor 4
a, 4b, and 4c maintain the flatness.

【0023】尚、前記有機樹脂充填体7は絶縁基板1の
貫通孔5内にエポキシ樹脂の前駆体を充填し、しかる
後、これに80℃〜200℃の温度を0.5〜3時間印
加し、完全に熱硬化させることによって絶縁基体1の貫
通孔5内に充填される。
The organic resin filler 7 fills the through-hole 5 of the insulating substrate 1 with an epoxy resin precursor, and then is applied with a temperature of 80 ° C. to 200 ° C. for 0.5 to 3 hours. Then, it is completely filled in the through holes 5 of the insulating substrate 1 by thermosetting.

【0024】更に前記絶縁基板1はその上面3つの有機
樹脂絶縁層3a、3b、3cと3つの層の薄膜配線導体
4a、4b、4cとが交互に多層に配設された多層配線
部2が形成されており、且つ該薄膜配線導体4aは導電
層6と電気的に接続されている。
Further, the insulating substrate 1 has a multilayer wiring portion 2 in which three organic resin insulating layers 3a, 3b, 3c and three thin-film wiring conductors 4a, 4b, 4c are alternately arranged on the upper surface. The thin film wiring conductor 4 a is formed and is electrically connected to the conductive layer 6.

【0025】前記多層配線部2を構成する有機樹脂絶縁
層3a、3b、3cは上下に位置する薄膜配線導体4
a、4b、4cの電気的絶縁を図る作用を為し、各薄膜
配線導体4a、4b、4cは電気信号を伝達するための
伝達路として作用する。
The organic resin insulating layers 3a, 3b and 3c constituting the multilayer wiring section 2 are composed of thin film wiring conductors 4 located above and below.
The thin film wiring conductors 4a, 4b, and 4c serve as transmission paths for transmitting electric signals.

【0026】前記多層配線部2の各有機樹脂絶縁層3
a、3b、3cはエポキシ樹脂から成り、例えば、エポ
キシ樹脂から成る場合、ビスフェノールA型エポキシ樹
脂、ノボラック型エポキシ樹脂、グリシジルエステル型
エポキシ樹脂等にアミン系硬化剤、イミダゾール系硬化
剤、酸無水物系硬化剤等の硬化剤を添加混合してペース
ト状のエポキシ樹脂前駆体を得るとともに該エポキシ樹
脂前駆体を絶縁基板1の上部にスピンコート法により被
着させ、しかる後、これを約80℃〜200℃の熱で
0.5乃至3時間熱処理し、熱硬化させることによって
形成される。
Each organic resin insulating layer 3 of the multilayer wiring section 2
a, 3b and 3c are made of an epoxy resin. For example, when made of an epoxy resin, bisphenol A type epoxy resin, novolak type epoxy resin, glycidyl ester type epoxy resin, etc. are used as an amine-based curing agent, an imidazole-based curing agent, and an acid anhydride. A curing agent such as a system curing agent is added and mixed to obtain a paste-like epoxy resin precursor, and the epoxy resin precursor is applied to the upper part of the insulating substrate 1 by a spin coating method. It is formed by heat-treating with heat of about 200 ° C. for 0.5 to 3 hours and heat-curing.

【0027】また前記各有機樹脂絶縁層3a、3b、3
cはその各々の所定位置に最小径が有機樹脂絶縁層の厚
みに対して約1.5倍程度のスルーホール8が形成され
ており、該スルーホール8は後述する各有機樹脂絶縁層
3a、3b、3cを介して上下に位置する各薄膜配線導
体4a、4b、4cの各々を電気的に接続するスルーホ
ール導体9を形成するための形成孔として作用する。
Each of the organic resin insulating layers 3a, 3b, 3
As for c, a through hole 8 whose minimum diameter is about 1.5 times the thickness of the organic resin insulating layer is formed at a predetermined position of each of the organic resin insulating layers 3a, It functions as a forming hole for forming a through-hole conductor 9 that electrically connects each of the thin film wiring conductors 4a, 4b, and 4c located above and below via 3b and 3c.

【0028】前記各有機樹脂絶縁層3a、3b、3cに
設けるスルーホール8は例えば、フォトリソグラフィー
技術、具体的には各有機樹脂絶縁層3a、3b、3c上
にレジスト材を塗布するとともにこれに露光、現像を施
すことによって所定位置に所定形状の窓部を形成し、次
に前記レジスト材の窓部にエッチング液を配し、レジス
ト材の窓部に位置する有機樹脂絶縁層3a、3b、3c
を除去して、有機樹脂絶縁層3a、3b、3cに穴(ス
ルーホール)を形成し、最後に前記レジスト材を有機樹
脂絶縁層3a、3b、3c上より剥離させ除去すること
によって行われる。
The through holes 8 provided in each of the organic resin insulating layers 3a, 3b, 3c are formed, for example, by photolithography, specifically, by coating a resist material on each of the organic resin insulating layers 3a, 3b, 3c. A window having a predetermined shape is formed at a predetermined position by performing exposure and development, and then an etchant is disposed on the window of the resist material, and the organic resin insulating layers 3a, 3b, 3c
Is removed to form holes (through holes) in the organic resin insulating layers 3a, 3b, 3c, and finally, the resist material is peeled off from the organic resin insulating layers 3a, 3b, 3c and removed.

【0029】更に前記各有機樹脂絶縁層3a、3b、3
cの各々の上面には所定パターンの薄膜配線導体4a、
4b、4cが、また各有機樹脂絶縁層3a、3b、3c
に設けたスルーホール8の内壁にはスルーホール導体9
が各々配設されており、スルーホール導体9によって有
機樹脂絶縁層3a、3b、3cの各々を間に挟んで上下
に位置する各薄膜配線導体4a、4b、4cが電気的に
接続されるようになっている。
Further, each of the organic resin insulating layers 3a, 3b, 3
c on the upper surface of each of the thin film wiring conductors 4a of a predetermined pattern,
4b and 4c are the respective organic resin insulating layers 3a, 3b and 3c.
The through hole conductor 9 is provided on the inner wall of the through hole 8
Are disposed, and the through-hole conductors 9 electrically connect the thin film wiring conductors 4a, 4b, and 4c located vertically above and below the organic resin insulating layers 3a, 3b, and 3c, respectively. It has become.

【0030】前記各有機樹脂絶縁層3a、3b、3cの
上面及びスルーホール8内に配設される薄膜配線導体4
a、4b、4c及びスルーホール導体9は銅、ニッケ
ル、金、アルミニウム等の金属材料を無電解めっき法や
蒸着法、スパッタリング法等の薄膜形成技術及びエッチ
ング加工技術を採用することによって形成され、例えば
銅で形成されている場合には、各有機樹脂絶縁層3a、
3b、3cの上面及びスルーホール8の内表面に硫酸銅
0.06モル/リットル、ホルマリン0.3モル/リッ
トル、水酸化ナトリウム0.35モル/リットル、エチ
レンジアミン四酢酸0.35モル/リットルからなる無
電解銅メッキ浴を用いて厚さ1μm乃至40μmの銅層
を被着させ、しかる後、前記銅層をエッチング加工法に
より所定パターンに加工することによって各有機樹脂絶
縁層3a、3b、3c間及び各有機樹脂絶縁層3a、3
b、3cのスルーホール8内壁に配設される。この場
合、薄膜配線導体4a、4b、4cは薄膜形成技術によ
り形成されることから配線の微細化が可能であり、これ
によって薄膜配線導体4a、4b、4cを極めて高密度
に形成することが可能となる。
The thin film wiring conductors 4 provided on the upper surfaces of the organic resin insulating layers 3a, 3b, 3c and in the through holes 8
a, 4b, 4c and the through-hole conductor 9 are formed by employing a metal material such as copper, nickel, gold, and aluminum by using a thin film forming technique such as an electroless plating method, a vapor deposition method, and a sputtering method and an etching processing technique; For example, when formed of copper, each of the organic resin insulating layers 3a,
0.06 mol / l of copper sulfate, 0.3 mol / l of formalin, 0.35 mol / l of sodium hydroxide, 0.35 mol / l of ethylenediaminetetraacetic acid on the upper surfaces of 3b and 3c and the inner surface of through hole 8 A copper layer having a thickness of 1 μm to 40 μm is deposited by using an electroless copper plating bath, and then the copper layer is processed into a predetermined pattern by an etching method, whereby each of the organic resin insulating layers 3a, 3b, and 3c is formed. Between and each organic resin insulating layer 3a, 3
b, 3c are disposed on the inner wall of the through hole 8. In this case, since the thin film wiring conductors 4a, 4b, and 4c are formed by a thin film forming technique, the wiring can be miniaturized, whereby the thin film wiring conductors 4a, 4b, and 4c can be formed at an extremely high density. Becomes

【0031】尚、前記多層配線部2は各有機樹脂絶縁層
3a、3b、3cの厚みが100μmを越えると各有機
樹脂絶縁層3a、3b、3cにフォトリソグラフィー技
術を採用することによってスルーホール8を形成する
際、エッチングの加工時間が長くなってスルーホール8
を所望する鮮明な形状に形成するのが困難となり、また
5μm未満となると各有機樹脂絶縁層3a、3b、3c
の上面に上下に位置する有機樹脂絶縁層の接合強度を上
げるための粗面加工を施す際、各有機樹脂絶縁層3a、
3b、3cに不要な穴が形成され上下に位置する薄膜配
線導体4a、4b、4cに不要な電気的短絡を招来して
しまう危険性がある。従って、前記有機樹脂絶縁層各有
機樹脂絶縁層3a、3b、3cはその各々の厚みを5μ
m乃至100μmの範囲としておくことが好ましい。
When the thickness of each of the organic resin insulating layers 3a, 3b and 3c exceeds 100 μm, the through-holes 8 are formed in the multilayer wiring section 2 by adopting a photolithography technique for each of the organic resin insulating layers 3a, 3b and 3c. When forming a through hole, the etching processing time becomes longer and the through hole 8 is formed.
Is difficult to form into a desired clear shape, and if it is less than 5 μm, each organic resin insulating layer 3a, 3b, 3c
When roughening is performed to increase the bonding strength of the organic resin insulating layers located above and below on the upper surface of each of the organic resin insulating layers 3a,
Unnecessary holes are formed in 3b and 3c, and there is a danger that unnecessary electrical short circuits may be caused in the thin film wiring conductors 4a, 4b and 4c located above and below. Therefore, each of the organic resin insulating layers 3a, 3b and 3c has a thickness of 5 μm.
It is preferable to set the range of m to 100 μm.

【0032】また前記多層配線部2の各薄膜配線導体4
a、4b、4cはその厚みが1μm未満となると各薄膜
配線導体4a、4b、4cの電気抵抗が大きなものとな
って各薄膜配線導体4a、4b、4cに所定の電気信号
を伝達させることが困難なものとなり、また40μmを
越えると各薄膜配線導体4a、4b、4cを各有機樹脂
絶縁層3a、3b、3cに被着させる際、各薄膜配線導
体4a、4b、4c内に大きな応力が内在し、該内在応
力によって各薄膜配線導体4a、4b、4cが各有機樹
脂絶縁層3a、3b、3cより剥離し易いものとなる。
従って、前記多層配線部2の各薄膜配線導体4a、4
b、4cの厚みを1μm乃至40μmの範囲としておく
ことが好ましい。
Each thin-film wiring conductor 4 of the multilayer wiring section 2
When the thickness of each of the thin film wiring conductors 4a, 4b, and 4c is less than 1 μm, the electric resistance of each thin film wiring conductor 4a, 4b, and 4c becomes large, and a predetermined electric signal can be transmitted to each thin film wiring conductor 4a, 4b, and 4c. When the thickness exceeds 40 μm, when the thin film wiring conductors 4a, 4b, and 4c are applied to the organic resin insulating layers 3a, 3b, and 3c, a large stress is generated in the thin film wiring conductors 4a, 4b, and 4c. The thin film wiring conductors 4a, 4b, and 4c are inherently separated from the organic resin insulating layers 3a, 3b, and 3c by the intrinsic stress.
Therefore, each of the thin film wiring conductors 4a, 4a,
It is preferable to set the thickness of b and 4c in the range of 1 μm to 40 μm.

【0033】更に前記薄膜配線導体4a、4b、4cは
その表面が中心線平均粗さ(Ra)で0.05μm≦R
a≦5μm、表面の2.5mmの長さにおける凹凸の高
さ(Pc)のカウント値を0.01μm≦Pc≦0.1
μmが30000個以上、0.1μm≦Pc≦1μmが
3000個乃至10000個、1μm≦Pc≦10μm
が500個以下となるように粗しておくと各有機樹脂絶
縁層3a、3b、3cと各薄膜配線導体4a、4b、4
cとはその接合面積が極めて広いものとなり、その結
果、各有機樹脂絶縁層3a、3b、3cと各薄膜配線導
体4a、4b、4cとの密着性が著しく向上し、有機樹
脂絶縁層3a、3b、3cや薄膜配線導体4a、4b、
4cに外力が印加されても該外力によって各有機樹脂絶
縁層3a、3b、3cと各薄膜配線導体4a、4b、4
cとの間に剥離が発生することはなく、両者の接合を極
めて強固となすことができる。従って、前記各薄膜配線
導体4a、4b、4cはその表面が中心線平均粗さ(R
a)で0.05μm≦Ra≦5μm、表面の2.5mm
の長さにおける凹凸の高さ(Pc)のカウント値を0.
01μm≦Pc≦0.1μmが30000個以上、0.
1μm≦Pc≦1μmが3000個乃至10000個、
1μm≦Pc≦10μmが500個以下となるように粗
しておくことが好ましい。
The surface of the thin film wiring conductors 4a, 4b, 4c has a center line average roughness (Ra) of 0.05 μm ≦ R
a ≦ 5 μm, the count value of the height of irregularities (Pc) at a length of 2.5 mm on the surface is 0.01 μm ≦ Pc ≦ 0.1
30000 μm or more, 3000 μm to 10000 μm ≦ Pc ≦ 1 μm, 1 μm ≦ Pc ≦ 10 μm
Is roughened to be 500 or less, each organic resin insulating layer 3a, 3b, 3c and each thin film wiring conductor 4a, 4b, 4
c has a very large bonding area, and as a result, the adhesion between each organic resin insulating layer 3a, 3b, 3c and each thin film wiring conductor 4a, 4b, 4c is remarkably improved, and the organic resin insulating layer 3a, 3b, 3c and thin film wiring conductors 4a, 4b,
Even if an external force is applied to 4c, each organic resin insulating layer 3a, 3b, 3c and each thin film wiring conductor 4a, 4b, 4c
No separation occurs between the two and c, and the bonding between the two can be made extremely strong. Accordingly, the surface of each of the thin film wiring conductors 4a, 4b, 4c has a center line average roughness (R
In a) 0.05 μm ≦ Ra ≦ 5 μm, 2.5 mm on the surface
The count value of the height (Pc) of the unevenness in the length of.
30 μm or more of 0.01 μm ≦ Pc ≦ 0.1 μm;
1 μm ≦ Pc ≦ 1 μm is 3000 to 10000,
It is preferable that 1 μm ≦ Pc ≦ 10 μm is roughened so as to be 500 or less.

【0034】また更に前記有機樹脂絶縁層3a、3b、
3cと各薄膜配線導体4a、4b、4cとからなる配線
導体部2は有機樹脂絶縁層3bに比誘電率が20以上の
誘電物フィラーが含有され、かつ有機樹脂絶縁層3bを
その上下両面に配設された薄膜配線導体4a、4bの一
部で対向挟持せることによって容量素子Aが形成されて
おり、該容量素子Aは薄膜配線導体4a、4bに電気的
に接続されている。
Further, the organic resin insulating layers 3a, 3b,
3c and the thin film wiring conductors 4a, 4b, 4c, the wiring conductor portion 2 includes a dielectric filler having a relative dielectric constant of 20 or more in the organic resin insulating layer 3b, and the organic resin insulating layer 3b is provided on both upper and lower surfaces thereof. The capacitive element A is formed by being sandwiched between a part of the disposed thin film wiring conductors 4a and 4b, and the capacitive element A is electrically connected to the thin film wiring conductors 4a and 4b.

【0035】前記容量素子Aの静電容量値は比誘電率が
20以上の誘電物フィラーが含有された有機樹脂絶縁層
3bの比誘電率と、有機樹脂絶縁層3bの厚みと、薄膜
配線導体4a、4bの対向面積の大きさによって決定さ
れ、有機樹脂絶縁層3bに含有させる誘電物フィラーの
比誘電率及び薄膜配線導体4a、4bの対向面積の大き
さを可変することによって所定の静電容量値に調整され
る。
The capacitance value of the capacitor A is determined by the relative dielectric constant of the organic resin insulating layer 3b containing a dielectric filler having a relative dielectric constant of 20 or more, the thickness of the organic resin insulating layer 3b, and the thickness of the thin film wiring conductor. The predetermined electrostatic capacity is determined by the size of the opposing area of the thin film wiring conductors 4a and 4b, and is determined by the size of the opposing area of the organic resin insulating layer 3b. Adjusted to the capacitance value.

【0036】前記容量素子Aは絶縁基板1上に設けた多
層配線部2の内部に内蔵されており、そのためこの多層
配線基板に半導体素子や容量素子、抵抗器等の部品を搭
載して混成集積回路装置等となす場合、多層配線基板に
別途、容量素子を多数実装する必要はなく、その結果、
多層配線基板に実装される部品の数が減り、混成集積回
路装置等を小型となすことが可能となる。
The capacitive element A is built in the multilayer wiring section 2 provided on the insulating substrate 1. Therefore, components such as a semiconductor element, a capacitive element and a resistor are mounted on the multilayer wiring board and mixedly integrated. In the case of a circuit device or the like, it is not necessary to separately mount a large number of capacitive elements on a multilayer wiring board.
The number of components mounted on the multilayer wiring board is reduced, and the size of the hybrid integrated circuit device or the like can be reduced.

【0037】尚、前記誘電物フィラーの有機樹脂絶縁層
3bへの含有はエポキシ樹脂等の有機樹脂前駆体を使用
して有機樹脂絶縁層3bを形成する際に予め有機樹脂前
駆体に誘電物フィラーを添加混合させておくことによっ
て有機樹脂絶縁層3bに含有される。
It should be noted that the dielectric filler is contained in the organic resin insulating layer 3b when the organic resin precursor such as an epoxy resin is used to form the organic resin insulating layer 3b. Is contained in the organic resin insulating layer 3b by adding and mixing.

【0038】また前記有機樹脂絶縁層3bに含有される
誘電物フィラーはその比誘電率が20(室温1MHz)
未満となると有機樹脂絶縁層3bの比誘電率が小さくな
って容量素子Aの静電容量値が実用に供しない小さな値
となってしまう。従って、前記有機樹脂絶縁層3bに含
有される誘電物フィラーはその比誘電率が20(室温1
MHz)以上のものに特定され、チタン酸バリウムやチ
タン酸ストロンチウム等の比誘電率が高い材料が好適に
使用される。
The dielectric filler contained in the organic resin insulating layer 3b has a relative dielectric constant of 20 (room temperature 1 MHz).
When the value is less than the specific dielectric constant of the organic resin insulating layer 3b, the capacitance value of the capacitor A becomes a small value that is not practically used. Therefore, the dielectric filler contained in the organic resin insulating layer 3b has a relative dielectric constant of 20 (room temperature 1).
MHz) or more, and a material having a high relative dielectric constant, such as barium titanate or strontium titanate, is suitably used.

【0039】更に前記誘電物フィラーはその粒径が直径
0.5μm未満となると誘電物フィラーの比表面積が大
きくなってこの誘電物フィラーを添加混合した有機樹脂
前駆体の粘度を高くしてしまい、その結果、この誘電物
フィラーを添加混合した有機樹脂前駆体をスピンコート
法等を採用して有機樹脂絶縁層3bを形成する際、有機
樹脂絶縁層3bの厚みが不均一となり、有機樹脂絶縁層
3bを所定の均一厚みとすることが困難となってしま
い、また50μmを越えると誘電物フィラーによって有
機樹脂絶縁層3bの表面に凹凸が形成され、容量素子A
が形成される領域における有機樹脂絶縁層3bの比誘電
率にバラツキが発生したり、有機樹脂絶縁層3bにおけ
る誘電物フィラーの接着強度が低下し、誘電物フィラー
が有機樹脂絶縁層3bより脱落したりしてしまう危険性
がある。従って、前記誘電物フィラーはその粒径を直径
0.5μm乃至50μmの範囲としておくことが好まし
い。
Further, when the particle size of the dielectric filler is less than 0.5 μm in diameter, the specific surface area of the dielectric filler increases, and the viscosity of the organic resin precursor added and mixed with the dielectric filler increases, As a result, when the organic resin precursor to which the dielectric filler is added and mixed is used to form the organic resin insulating layer 3b by spin coating or the like, the thickness of the organic resin insulating layer 3b becomes non-uniform, It is difficult to make the thickness of the capacitor 3b a predetermined uniform thickness. If the thickness exceeds 50 μm, irregularities are formed on the surface of the organic resin insulating layer 3b by the dielectric filler, and the capacitor A
The relative dielectric constant of the organic resin insulating layer 3b varies in the region where the layer is formed, the adhesive strength of the dielectric filler in the organic resin insulating layer 3b decreases, and the dielectric filler drops off from the organic resin insulating layer 3b. There is a risk that Therefore, the dielectric filler preferably has a particle diameter in a range of 0.5 μm to 50 μm.

【0040】また更に前記誘電物フィラーの有機樹脂絶
縁層3bへの含有量は、誘電物フィラーの量が有機樹脂
絶縁層3bの全有機樹脂量に対し20重量%未満となる
と有機樹脂絶縁層3bの比誘電率が小さく、実用に供す
ることができる容量素子Aを形成するのが困難となり、
また75重量%を越えると有機樹脂絶縁層3bにおける
誘電物フィラーの接着強度が低下し、誘電物フィラーが
有機樹脂絶縁層3bより脱落してしまう危険性がある。
従って、前記誘電物フィラーの有機樹脂絶縁層3bへの
含有量は20重量%乃至75重量%の範囲としておくこ
とが好ましい。
Further, the content of the dielectric filler in the organic resin insulating layer 3b is such that when the amount of the dielectric filler is less than 20% by weight based on the total organic resin content of the organic resin insulating layer 3b, Has a small relative dielectric constant, making it difficult to form a capacitive element A that can be put to practical use.
If the content exceeds 75% by weight, the adhesive strength of the dielectric filler in the organic resin insulating layer 3b decreases, and there is a risk that the dielectric filler may fall off the organic resin insulating layer 3b.
Therefore, the content of the dielectric filler in the organic resin insulating layer 3b is preferably set in the range of 20% by weight to 75% by weight.

【0041】かくして本発明の多層配線基板によれば、
例えば、絶縁基板1の上面に被着させた多層配線部2上
に半導体素子等の能動部品や容量素子、抵抗器等の受動
部品を実装させることによって混成集積回路装置とな
り、絶縁基板1の下面に被着されている導電層6を外部
電気回路に接続すればかかる混成集積回路装置が外部電
気回路に電気的に接続されることとなる。
Thus, according to the multilayer wiring board of the present invention,
For example, a hybrid integrated circuit device is obtained by mounting active components such as a semiconductor device, passive components such as a capacitor, and a resistor on the multilayer wiring portion 2 attached to the upper surface of the insulating substrate 1. Is connected to an external electric circuit, the hybrid integrated circuit device is electrically connected to the external electric circuit.

【0042】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば、上述の実施例において
は絶縁基板1の上面のみに複数の有機樹脂絶縁層3a、
3b、3cと複数の薄膜配線導体4a、4b、4cとか
ら成る多層配線部2を設けたが、該多層配線部2を絶縁
基板1の下面側のみに設けても、上下の両主面に設けて
もよい。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. A plurality of organic resin insulating layers 3a only on the upper surface of
Although the multilayer wiring portion 2 including the thin film wiring conductors 3a and 3b and the plurality of thin film wiring conductors 4a, 4b and 4c is provided, the multilayer wiring portion 2 may be provided only on the lower surface side of the insulating substrate 1 or may be provided on both upper and lower main surfaces. It may be provided.

【0043】[0043]

【発明の効果】本発明の多層配線基板によれば、絶縁基
板上に薄膜形成技術によって配線を形成したことから配
線の微細化が可能となり、配線を極めて高密度に形成す
ることが可能となる。
According to the multilayer wiring board of the present invention, since the wiring is formed on the insulating substrate by the thin film forming technique, the wiring can be miniaturized and the wiring can be formed at an extremely high density. .

【0044】また本発明の多層配線基板によれば、有機
樹脂絶縁層の少なくとも一層に比誘電率が20以上の誘
電物フィラーを含有させるとともに該誘電物フィラーが
含有されている有機樹脂絶縁層をその上下両面に配設さ
れている薄膜配線導体の一部で対向挟持させることによ
って容量素子を形成するとともに該容量素子を薄膜配線
導体間に電気的接続させたことから多層配線基板に半導
体素子や容量素子、抵抗器等の部品を搭載して混成集積
回路装置等となす場合、多層配線基板に別途、容量素子
を多数実装する必要はなく、その結果、多層配線基板に
実装される部品の数が減り、混成集積回路装置等を小型
となすことが可能となる。
According to the multilayer wiring board of the present invention, at least one of the organic resin insulating layers contains a dielectric filler having a relative dielectric constant of 20 or more, and the organic resin insulating layer containing the dielectric filler is provided. The capacitive element is formed by opposing and sandwiching a part of the thin film wiring conductors disposed on the upper and lower surfaces thereof, and the capacitive element is electrically connected between the thin film wiring conductors. When a component such as a capacitor and a resistor is mounted to form a hybrid integrated circuit device or the like, it is not necessary to separately mount a large number of capacitors on the multilayer wiring board. As a result, the number of components mounted on the multilayer wiring board is reduced. And the size of the hybrid integrated circuit device and the like can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層配線基板の一実施例を示す断面図
である。
FIG. 1 is a sectional view showing one embodiment of a multilayer wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1・・・絶縁基板 2・・・多層配線部 3a、3b、3c・・有機樹脂絶縁層 4a、4b、4c・・薄膜配線導体 5・・・貫通孔 6・・・導電層 7・・・有機樹脂充填体 A・・・容量素子 DESCRIPTION OF SYMBOLS 1 ... Insulating board 2 ... Multilayer wiring part 3a, 3b, 3c ... Organic resin insulating layer 4a, 4b, 4c ... Thin film wiring conductor 5 ... Through-hole 6 ... Conductive layer 7 ... Organic resin filler A: Capacitance element

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】上下両主面に貫通する貫通孔を有する絶縁
基板と、該絶縁基板の上面から貫通孔内壁を経て下面に
導出する導電層と、前記貫通孔の内部に充填された有機
樹脂充填体と、前記絶縁基板の少なくとも一主面上に被
着され、複数の有機樹脂絶縁層と複数の薄膜配線導体と
を交互に多層に配設するとともに薄膜配線導体の一部が
前記導電層に電気的に接続されている多層配線部とから
成る多層配線基板であって、前記有機樹脂絶縁層の少な
くとも一層に比誘電率が20以上の誘電物フィラーを含
有させるとともに該誘電物フィラーが含有されている有
機樹脂絶縁層をその上下両面に配設されている薄膜配線
導体の一部で対向挟持させることによって容量素子を形
成するとともに該容量素子を薄膜配線導体間に電気的接
続させたことを特徴とする多層配線基板。
An insulating substrate having a through hole penetrating both upper and lower main surfaces, a conductive layer extending from an upper surface of the insulating substrate to a lower surface via an inner wall of the through hole, and an organic resin filled in the through hole A filler and a plurality of organic resin insulating layers and a plurality of thin film wiring conductors are alternately disposed on the at least one main surface of the insulating substrate, and a part of the thin film wiring conductor is formed on the conductive layer. A multilayer wiring board comprising a multilayer wiring portion electrically connected to the organic resin insulating layer, wherein at least one of the organic resin insulating layers contains a dielectric filler having a relative dielectric constant of 20 or more, and the dielectric filler contains The capacitor element is formed by sandwiching the organic resin insulating layer formed between the thin film wiring conductors disposed on the upper and lower surfaces thereof, and the capacitor element is electrically connected between the thin film wiring conductors. Especially Multilayer wiring substrate having a.
【請求項2】前記誘電物フィラーがチタン酸バリウム、
チタン酸ストロンチウムの少なくとも1種よりなること
を特徴とする請求項1に記載の多層配線基板。
2. The method according to claim 1, wherein the dielectric filler is barium titanate;
2. The multilayer wiring board according to claim 1, comprising at least one of strontium titanate.
【請求項3】前記誘電物フィラーの粒径が直径0.5μ
m乃至50μmであることを特徴とする請求項1及び請
求項2に記載の多層配線基板。
3. The dielectric filler has a particle diameter of 0.5 μm.
3. The multilayer wiring board according to claim 1, wherein the thickness of the multilayer wiring board is in a range of m to 50 μm.
JP8163152A 1996-06-24 1996-06-24 Multilayer wiring board Pending JPH1013036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8163152A JPH1013036A (en) 1996-06-24 1996-06-24 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8163152A JPH1013036A (en) 1996-06-24 1996-06-24 Multilayer wiring board

Publications (1)

Publication Number Publication Date
JPH1013036A true JPH1013036A (en) 1998-01-16

Family

ID=15768221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8163152A Pending JPH1013036A (en) 1996-06-24 1996-06-24 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JPH1013036A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214445B1 (en) 1998-12-25 2001-04-10 Ngk Spark Plug Co., Ltd. Printed wiring board, core substrate, and method for fabricating the core substrate
WO2004010751A1 (en) * 2002-07-18 2004-01-29 Hitachi Chemical Co., Ltd. Multilayer wiring board, method for producing the same, semiconductor device and radio electronic device
KR100817344B1 (en) * 2002-07-18 2008-03-26 히다치 가세고교 가부시끼가이샤 Multilayer wiring board, method for producing the same, semiconductor device and radio electronic device
US8120173B2 (en) * 2005-05-03 2012-02-21 Lockheed Martin Corporation Thin embedded active IC circuit integration techniques for flexible and rigid circuits

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214445B1 (en) 1998-12-25 2001-04-10 Ngk Spark Plug Co., Ltd. Printed wiring board, core substrate, and method for fabricating the core substrate
WO2004010751A1 (en) * 2002-07-18 2004-01-29 Hitachi Chemical Co., Ltd. Multilayer wiring board, method for producing the same, semiconductor device and radio electronic device
US7239013B2 (en) 2002-07-18 2007-07-03 Hitachi Chemical Co., Ltd. Multilayer wiring board, method for producing the same, semiconductor device and radio electronic device
KR100817344B1 (en) * 2002-07-18 2008-03-26 히다치 가세고교 가부시끼가이샤 Multilayer wiring board, method for producing the same, semiconductor device and radio electronic device
CN100413383C (en) * 2002-07-18 2008-08-20 日立化成工业株式会社 Multilayer wiring board, method for producing the same, semiconductor device and radio electronic device
US7592250B2 (en) 2002-07-18 2009-09-22 Hitachi Chemical Company, Ltd. Multilayer wiring board, manufacturing method thereof, semiconductor device, and wireless electronic device
US8120173B2 (en) * 2005-05-03 2012-02-21 Lockheed Martin Corporation Thin embedded active IC circuit integration techniques for flexible and rigid circuits

Similar Documents

Publication Publication Date Title
JPH1013036A (en) Multilayer wiring board
JP3071723B2 (en) Method for manufacturing multilayer wiring board
JPH1093246A (en) Multilayer wiring board
JPH1093248A (en) Multilayer wiring board
JPH10322029A (en) Multilayered wiring board
JPH1041632A (en) Multilayer wiring board
JPH10150272A (en) Multilayer wiring board
JP3688844B2 (en) Multilayer wiring board
JPH1013033A (en) Multilayer wiring board
JPH10340978A (en) Mounting structure for electronic component onto wiring board
JPH1093247A (en) Multilayer wiring board
JPH114080A (en) Multilayered wiring board
JPH10163634A (en) Multilayer wiring board
JPH11186434A (en) Multi-layer wiring substrate
JPH1126939A (en) Multilayered wiring board
JPH1022637A (en) Multilayer wiring board
JPH10326966A (en) Multilayered wiring board
JPH11233909A (en) Wiring board
JPH114079A (en) Multilayered wiring board
JPH10322030A (en) Multilayered wiring board
JPH1197852A (en) Multilayered wiring board
JPH11150370A (en) Multilayer wiring board
JPH1197851A (en) Multilayered wiring board
JPH1092879A (en) Multilayer wiring board
JPH11233679A (en) Multilayer wiring board

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040108

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20040203