JPH1041632A - Multilayer wiring board - Google Patents
Multilayer wiring boardInfo
- Publication number
- JPH1041632A JPH1041632A JP8197908A JP19790896A JPH1041632A JP H1041632 A JPH1041632 A JP H1041632A JP 8197908 A JP8197908 A JP 8197908A JP 19790896 A JP19790896 A JP 19790896A JP H1041632 A JPH1041632 A JP H1041632A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- organic resin
- layer
- wiring
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、多層配線基板に関
し、より詳細には混成集積回路装置や半導体素子を収容
する半導体素子収納用パッケージ等に使用される多層配
線基板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board used for a hybrid integrated circuit device, a semiconductor element housing package for housing a semiconductor element, and the like.
【0002】[0002]
【従来の技術】従来、半導体素子等の能動部品や容量素
子、抵抗素子等の受動部品を多数搭載し、所定の電子回
路を構成するようになした混成集積回路装置は、通常、
絶縁基板の内部及び表面にタングステン、モリブデン等
の高融点金属粉末から成る配線導体を形成した構造の配
線基板を準備し、次に前記配線基板の表面に半導体素子
や容量素子、抵抗素子等を搭載取着するとともに該半導
体素子等の電極を前記配線導体に接続することによって
混成集積回路装置となる。2. Description of the Related Art Conventionally, a hybrid integrated circuit device in which a large number of active components such as a semiconductor device and passive components such as a capacitance device and a resistance device are mounted to constitute a predetermined electronic circuit is usually used.
Prepare a wiring board having a structure in which a wiring conductor made of a refractory metal powder such as tungsten or molybdenum is formed inside and on the surface of the insulating substrate, and then mount semiconductor elements, capacitance elements, resistance elements, etc. on the surface of the wiring board. By attaching and connecting the electrodes of the semiconductor element and the like to the wiring conductor, a hybrid integrated circuit device is obtained.
【0003】かかる従来の混成集積回路装置等に使用さ
れる配線基板は一般にセラミックスの積層技術及びスク
リーン印刷法等の厚膜技術を採用することによって製作
されており、具体的には以下の方法によって製作されて
いる。[0003] Wiring boards used in such conventional hybrid integrated circuit devices and the like are generally manufactured by employing a ceramic lamination technology and a thick film technology such as a screen printing method, and more specifically, by the following method. Has been produced.
【0004】即ち、 (1)先ず、アルミナ等の電気絶縁性に優れたセラミッ
ク原料粉末に有機溶剤、溶媒を添加混合して複数枚のセ
ラミック生シートを得るとともに該各セラミック生シー
トの上下面にタングステン、モリブデン等の高融点金属
粉末から成る導電ペーストを従来周知のスクリーン印刷
法等の厚膜手法を採用することによって所定パターンに
印刷塗布する。[0004] (1) First, an organic solvent and a solvent are added to and mixed with a ceramic raw material powder such as alumina which is excellent in electrical insulation to obtain a plurality of ceramic green sheets, and the raw ceramic sheets are formed on the upper and lower surfaces of each ceramic raw sheet. A conductive paste composed of a high melting point metal powder such as tungsten or molybdenum is printed and applied in a predetermined pattern by employing a conventionally known thick film method such as a screen printing method.
【0005】(2)次に前記各セラミック生シートを積
層し、積層体を得るとともにこれを約1500℃の温度
で焼成し、内部及び表面にタングステン、モリブデン等
の高融点金属粉末から成る配線導体を有する絶縁基板を
得る。(2) Each of the above ceramic green sheets is laminated to obtain a laminate, which is fired at a temperature of about 1500 ° C., and a wiring conductor made of a high melting point metal powder such as tungsten, molybdenum or the like inside and on the surface. Is obtained.
【0006】(3)そして最後に、前記配線導体のう
ち、大気中に露出する表面にニッケル及び金等の耐蝕性
に優れ、良導電性で、半田等のロウ材と濡れ性(反応
性)の良い金属をめっき法により被着させ、これによっ
て製品としての配線基板が完成する。(3) Finally, the surface of the wiring conductor exposed to the atmosphere is excellent in corrosion resistance such as nickel and gold, has good conductivity, and has wettability (reactivity) with a brazing material such as solder. A good metal is deposited by a plating method, thereby completing a wiring board as a product.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、この従
来の配線基板においては、配線導体がタングステンやモ
リブデン等の高融点金属粉末から成る導電ペーストをス
クリーン印刷法等の厚膜手法を採用し所定パターンに印
刷塗布することによって形成されており、配線導体の微
細化が困難で配線導体を高密度に形成することができな
いという欠点を有していた。However, in this conventional wiring board, the wiring conductor is formed into a predetermined pattern by applying a conductive paste made of a high melting point metal powder such as tungsten or molybdenum by a screen printing method or the like. It is formed by printing and applying, and has a drawback that it is difficult to miniaturize the wiring conductor and it is not possible to form the wiring conductor at high density.
【0008】またこの従来の配線基板は表面に半導体素
子等の能動部品や容量素子、抵抗素子等の受動部品が多
数搭載され、部品の搭載数に応じて大型化してしまうと
いう欠点も有していた。In addition, the conventional wiring board has a drawback that active components such as semiconductor elements and passive components such as capacitance elements and resistance elements are mounted on the surface thereof, and the size increases in accordance with the number of mounted components. Was.
【0009】[0009]
【課題を解決するための手段】本発明は上述の欠点に鑑
み案出されたもので、その目的は配線導体を薄膜形成技
術により形成される薄膜配線導体とするとともに内部に
抵抗素子を内蔵させることによって小型にして、且つ配
線が高密度の多層配線基板を提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to make a wiring conductor a thin film wiring conductor formed by a thin film forming technique and to internally incorporate a resistance element. Accordingly, it is an object of the present invention to provide a multilayer wiring board which is reduced in size and has a high density of wiring.
【0010】本発明は、上下両主面に貫通する貫通孔を
有する絶縁基板と、該絶縁基板の上面から貫通孔内壁を
経て下面に導出する導電層と、前記貫通孔の内部に充填
された有機樹脂充填体と、前記絶縁基板の少なくとも一
主面上に被着され、複数の有機樹脂絶縁層と複数の薄膜
配線導体とを交互に多層に配設するとともに薄膜配線導
体の一部が前記導電層に電気的に接続されている多層配
線部とから成る多層配線基板であって、前記少なくとも
一つの有機樹脂絶縁層上に薄膜抵抗体層を被着させると
ともに該薄膜抵抗体層に少なくとも一対の薄膜配線導体
の一部を接触させ、薄膜配線導体間に抵抗素子を電気的
に接続させたことを特徴とするものである。According to the present invention, there is provided an insulating substrate having a through hole penetrating both upper and lower main surfaces, a conductive layer extending from the upper surface of the insulating substrate to the lower surface through the inner wall of the through hole, and filled in the through hole. The organic resin filler, which is attached on at least one main surface of the insulating substrate, and a plurality of organic resin insulating layers and a plurality of thin film wiring conductors are alternately arranged in a multilayer and a part of the thin film wiring conductor is A multilayer wiring board comprising: a multilayer wiring portion electrically connected to a conductive layer, wherein a thin film resistor layer is provided on the at least one organic resin insulating layer, and at least one pair of the thin film resistor layers is provided on the thin film resistor layer. And a resistor element is electrically connected between the thin film wiring conductors.
【0011】また本発明は、前記薄膜抵抗体が窒化タン
タル、タンタルシリサイド、ニッケル・クロム、ニッケ
ル・クロムシリサイド、モリブデンシリサイド、タング
ステンシリサイド、チタンシリサイド、ニッケルシリサ
イド、クロムシリサイド、ニオブシリケート、タンタル
シリケートの少なくとも1種からなることを特徴とする
ものである。Further, the present invention is characterized in that the thin film resistor is at least one of tantalum nitride, tantalum silicide, nickel chromium, nickel chromium silicide, molybdenum silicide, tungsten silicide, titanium silicide, nickel silicide, chromium silicide, niobium silicate and tantalum silicate. It is characterized by comprising one kind.
【0012】更に本発明は前記薄膜抵抗体の厚みが0.
1μm乃至5μmであることを特徴とするものである。Further, according to the present invention, the thickness of the thin film resistor is set to 0.1.
The thickness is 1 μm to 5 μm.
【0013】本発明の多層配線基板によれば、絶縁基板
上に薄膜形成技術によって配線を形成したことから配線
の微細化が可能となり、配線を極めて高密度に形成する
ことが可能となる。According to the multilayer wiring board of the present invention, since the wiring is formed on the insulating substrate by the thin film forming technique, the wiring can be miniaturized, and the wiring can be formed at an extremely high density.
【0014】また本発明の多層配線基板によれば、複数
の有機樹脂絶縁層と複数の薄膜配線導体とを交互に多層
に配設して成る多層配線部の少なくとも一つの有機樹脂
絶縁層上に薄膜抵抗体層を被着させるとともに該薄膜抵
抗体層に少なくとも一対の薄膜配線導体の一部を接触さ
せ、薄膜配線導体間に抵抗素子を電気的に接続させたこ
とから多層配線基板に半導体素子や容量素子、抵抗素子
等の部品を搭載して混成集積回路装置等となす場合、多
層配線基板に別途、抵抗素子を多数実装する必要はな
く、その結果、多層配線基板に実装される部品の数が減
り、混成集積回路装置等を小型となすことが可能とな
る。Further, according to the multilayer wiring board of the present invention, a plurality of organic resin insulating layers and a plurality of thin film wiring conductors are alternately arranged in multiple layers on at least one organic resin insulating layer of a multilayer wiring portion. Since the thin-film resistor layer is applied and at least a part of the pair of thin-film wiring conductors is brought into contact with the thin-film resistor layer, and the resistive element is electrically connected between the thin-film wiring conductors, the semiconductor element is mounted on the multilayer wiring board. When a hybrid integrated circuit device is formed by mounting components such as a capacitor, a resistor, and a resistor, it is not necessary to separately mount a large number of resistors on the multilayer wiring board. The number is reduced, and the size of the hybrid integrated circuit device or the like can be reduced.
【0015】[0015]
【発明の実施の形態】次に、本発明を添付図面に基づき
詳細に説明する。図1は、本発明の多層配線基板の一実
施例を示し、1は絶縁基板、2は有機樹脂絶縁層、3は
薄膜配線導体である。Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a multilayer wiring board according to the present invention, wherein 1 is an insulating substrate, 2 is an organic resin insulating layer, and 3 is a thin film wiring conductor.
【0016】前記絶縁基板1はその上面に有機樹脂絶縁
層2と薄膜配線導体3とから成る多層配線部4が配設さ
れており、該多層配線部4を支持する支持部材として作
用する。On the upper surface of the insulating substrate 1, a multilayer wiring portion 4 comprising an organic resin insulating layer 2 and a thin film wiring conductor 3 is disposed, and functions as a support member for supporting the multilayer wiring portion 4.
【0017】前記絶縁基板1は酸化アルミニウム質焼結
体やムライト質焼結体等の酸化物系セラミックス、或い
は表面に酸化物膜を有する窒化アルミニウム質焼結体、
炭化珪素質焼結体等の非酸化物系セラミックス、更には
ガラス繊維を織る込んだ布にエポキシ樹脂を含浸させた
ガラスエポキシ樹脂等の電気絶縁材料で形成されてお
り、例えば、酸化アルミニウム質焼結体で形成されてい
る場合には、アルミナ、シリカ、カルシア、マグネシア
等の原料粉末に適当な有機溶剤、溶媒を添加混合して泥
漿状となすとともにこれを従来周知のドクターブレード
法やカレンダーロール法を採用することによってセラミ
ックグリーンシート(セラミック生シート)を形成し、
しかる後、前記セラミックグリーンシートに適当な打ち
抜き加工を施し、所定形状となすとともに高温(約16
00℃)で焼成することによって、或いはアルミナ等の
原料粉末に適当な有機溶剤、溶媒を添加混合して原料粉
末を調整するとともに該原料粉末をプレス成形機によっ
て所定形状に成形し、最後に前記成形体を約1600℃
の温度で焼成することによって製作され、またガラスエ
ポキシ樹脂から成る場合は、例えばガラス繊維を織り込
んだ布にエポキシ樹脂の前駆体を含浸させるとともに該
エポキシ樹脂前駆体を所定の温度で熱硬化させることに
よって製作される。The insulating substrate 1 is made of an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or an aluminum nitride sintered body having an oxide film on its surface.
It is made of an electrically insulating material such as a non-oxide ceramic such as a silicon carbide sintered body, and a glass epoxy resin in which a cloth woven with glass fibers is impregnated with an epoxy resin. In the case of a compact, a suitable organic solvent and a solvent are added to raw material powders such as alumina, silica, calcia, and magnesia to form a slurry by mixing and adding the same to a conventionally known doctor blade method or calender roll. By forming the ceramic green sheet (ceramic raw sheet) by adopting the method,
Thereafter, the ceramic green sheet is subjected to an appropriate punching process so as to have a predetermined shape and a high temperature (about 16 ° C.).
(00 ° C.) or by mixing a raw material powder such as alumina with an appropriate organic solvent and a solvent to adjust the raw material powder and form the raw material powder into a predetermined shape by a press molding machine. About 1600 ° C
If it is made by firing at a temperature of, and made of glass epoxy resin, for example, impregnating the epoxy resin precursor into a cloth woven of glass fibers and heat curing the epoxy resin precursor at a predetermined temperature Produced by
【0018】また前記絶縁基板1には上下両主面に貫通
する孔径が例えば、直径300μm〜500μmの貫通
孔5が形成されており、該貫通孔5の内壁には両端が絶
縁基板1の上下両面に導出する導電層6が被着されてい
る。The insulating substrate 1 is formed with a through hole 5 having a diameter of, for example, 300 μm to 500 μm, which penetrates the upper and lower main surfaces. Conductive layers 6 leading to both sides are applied.
【0019】前記貫通孔5は後述する絶縁基板1の上面
に形成される多層配線部4の薄膜配線導体3と外部電気
回路とを電気的に接続する、或いは絶縁基板1の上下両
主面に多層配線部4を配設した場合には両主面の多層配
線部4の薄膜配線導体3同士を電気的に接続する導電層
6を形成するための形成孔として作用し、絶縁基板1に
ドリル孔あけ加工法を施すことによって絶縁基板1の所
定位置、所定形状に形成される。The through hole 5 electrically connects the thin film wiring conductor 3 of the multilayer wiring portion 4 formed on the upper surface of the insulating substrate 1 to be described later and an external electric circuit, or is formed on both upper and lower main surfaces of the insulating substrate 1. When the multilayer wiring portion 4 is provided, it acts as a forming hole for forming a conductive layer 6 for electrically connecting the thin film wiring conductors 3 of the multilayer wiring portion 4 on both main surfaces, and a drill is formed in the insulating substrate 1. A predetermined position and a predetermined shape of the insulating substrate 1 are formed by performing a hole forming method.
【0020】更に前記貫通孔5の内壁及び絶縁基板1の
上下両面には導電層6が被着形成されており、該導電層
6は例えば、銅やニッケル等の金属材料から成り、従来
周知のめっき法及びエッチング法を採用することによっ
て貫通孔5の内壁に両端を絶縁基板1の上下両面に導出
させた状態で被着形成される。Further, a conductive layer 6 is formed on the inner wall of the through hole 5 and the upper and lower surfaces of the insulating substrate 1, and the conductive layer 6 is made of a metal material such as copper or nickel. By adopting the plating method and the etching method, it is formed on the inner wall of the through hole 5 with both ends being led out to the upper and lower surfaces of the insulating substrate 1.
【0021】前記導電層6は絶縁基板1の主面に配設さ
れる多層配線部4の薄膜配線導体3を外部電気回路に電
気的に接続したり、絶縁基板1の上下両主面に配設され
る各々の多層配線部4の薄膜配線導体3同士を電気的に
接続する作用をなす。The conductive layer 6 electrically connects the thin-film wiring conductors 3 of the multilayer wiring portion 4 provided on the main surface of the insulating substrate 1 to an external electric circuit, and is provided on both upper and lower main surfaces of the insulating substrate 1. It functions to electrically connect the thin film wiring conductors 3 of the respective multilayer wiring portions 4 to be provided.
【0022】また前記絶縁基板1に形成した貫通孔5は
その内部にエポキシ樹脂から成る有機樹脂充填体7が充
填されており、該有機樹脂充填体7によって貫通孔5が
完全に埋められ、同時に有機樹脂充填体7の両端面が絶
縁基板1の上下両主面に被着させた導電層6の面と同一
平面となっている。The through-hole 5 formed in the insulating substrate 1 is filled with an organic resin filler 7 made of epoxy resin, and the through-hole 5 is completely filled with the organic resin filler 7. Both end surfaces of the organic resin filler 7 are flush with the surface of the conductive layer 6 attached to the upper and lower main surfaces of the insulating substrate 1.
【0023】前記有機樹脂充填体7は絶縁基板1の上面
及び/又は下面に後述する有機樹脂絶縁層2と薄膜配線
導体3とから成る多層配線部4を形成する際、多層配線
部4の有機樹脂絶縁層2と薄膜配線導体3の平坦化を維
持する作用をなす。The organic resin filler 7 is used to form a multilayer wiring portion 4 comprising an organic resin insulating layer 2 and a thin film wiring conductor 3 which will be described later on the upper surface and / or lower surface of the insulating substrate 1. It functions to keep the resin insulating layer 2 and the thin film wiring conductor 3 flat.
【0024】尚、前記有機樹脂充填体7は絶縁基板1の
貫通孔5内にエポキシ樹脂の前駆体を充填し、しかる
後、これに80℃〜200℃の温度を0.5乃至3時間
印加し、完全に熱硬化させることによって絶縁基体1の
貫通孔5内に充填される。The organic resin filler 7 fills the through-hole 5 of the insulating substrate 1 with an epoxy resin precursor, and then is applied with a temperature of 80 ° C. to 200 ° C. for 0.5 to 3 hours. Then, it is completely filled in the through holes 5 of the insulating substrate 1 by thermosetting.
【0025】更に前記絶縁基板1はその上面に有機樹脂
絶縁層2と薄膜配線導体3とが交互に多層に配設された
多層配線部4が形成されており、且つ該薄膜配線導体3
の一部は導電層6と電気的に接続されている。Further, the insulating substrate 1 is provided with a multilayer wiring portion 4 on the upper surface of which an organic resin insulating layer 2 and thin film wiring conductors 3 are alternately arranged in multiple layers.
Are electrically connected to the conductive layer 6.
【0026】前記多層配線部4を構成する有機樹脂絶縁
層2は上下に位置する薄膜配線導体3の電気的絶縁を図
る作用を為すとともに薄膜配線導体3は電気信号を伝達
するための伝達路として作用する。The organic resin insulating layer 2 constituting the multilayer wiring portion 4 functions to electrically insulate the thin film wiring conductors 3 positioned above and below, and the thin film wiring conductors 3 serve as transmission paths for transmitting electric signals. Works.
【0027】前記多層配線部4の有機樹脂絶縁層2はエ
ポキシ樹脂から成り、例えば、エポキシ樹脂から成る場
合、ビスフェノールA型エポキシ樹脂、ノボラック型エ
ポキシ樹脂、グリシジルエステル型エポキシ樹脂等にア
ミン系硬化剤、イミダゾール系硬化剤、酸無水物系硬化
剤等の硬化剤を添加混合してペースト状のエポキシ樹脂
前駆体を得るとともに該エポキシ樹脂前駆体を絶縁基板
1の上部にスピンコート法により被着させ、しかる後、
これを約80℃〜200℃の熱で0.5乃至3時間熱処
理し、熱硬化させることによって形成される。The organic resin insulating layer 2 of the multilayer wiring portion 4 is made of an epoxy resin. For example, when the organic resin insulating layer 2 is made of an epoxy resin, an amine-based curing agent such as a bisphenol A type epoxy resin, a novolak type epoxy resin, a glycidyl ester type epoxy resin, or the like is used. A curing agent such as an imidazole-based curing agent and an acid anhydride-based curing agent is added and mixed to obtain a paste-like epoxy resin precursor, and the epoxy resin precursor is applied to the upper portion of the insulating substrate 1 by spin coating. After a while
This is formed by heat-treating with heat of about 80 ° C. to 200 ° C. for 0.5 to 3 hours and heat curing.
【0028】また前記有機樹脂絶縁層2はその各々の所
定位置に最小径が有機樹脂絶縁層2の厚みに対して約
1.5倍程度のスルーホール8が形成されており、該ス
ルーホール8は後述する有機樹脂絶縁層2を介して上下
に位置する薄膜配線導体3の各々を電気的に接続するス
ルーホール導体9を形成するための形成孔として作用す
る。The organic resin insulating layer 2 has a through hole 8 at a predetermined position, the minimum diameter of which is about 1.5 times the thickness of the organic resin insulating layer 2. Acts as a forming hole for forming a through-hole conductor 9 for electrically connecting each of the thin film wiring conductors 3 positioned above and below via an organic resin insulating layer 2 described later.
【0029】前記有機樹脂絶縁層2に設けるスルーホー
ル8は例えば、フォトリソグラフィー技術、具体的には
有機樹脂絶縁層2上にレジスト材を塗布するとともにこ
れに露光、現像を施すことによって所定位置に所定形状
の窓部を形成し、次に前記レジスト材の窓部にエッチン
グ液を配し、レジスト材の窓部に位置する有機樹脂絶縁
層2を除去して、有機樹脂絶縁層2に穴(スルーホー
ル)を形成し、最後に前記レジスト材を有機樹脂絶縁層
2上より剥離させ除去することによって行われる。The through holes 8 provided in the organic resin insulating layer 2 are formed at predetermined positions by, for example, photolithography, specifically, applying a resist material on the organic resin insulating layer 2 and exposing and developing the resist material. A window having a predetermined shape is formed, and then an etchant is disposed on the window of the resist material, the organic resin insulating layer 2 located on the window of the resist material is removed, and a hole ( A through hole is formed, and finally, the resist material is peeled off from the organic resin insulating layer 2 and removed.
【0030】更に前記各有機樹脂絶縁層2の上面には所
定パターンの薄膜配線導体3が、また各有機樹脂絶縁層
2に設けたスルーホール8の内壁にはスルーホール導体
9が各々配設されており、スルーホール導体9によって
間に有機樹脂絶縁層2を挟んで上下に位置する各薄膜配
線導体3の各々が電気的に接続されるようになってい
る。Further, a thin-film wiring conductor 3 having a predetermined pattern is provided on the upper surface of each organic resin insulating layer 2, and a through-hole conductor 9 is provided on the inner wall of a through hole 8 provided in each organic resin insulating layer 2. Each of the thin-film wiring conductors 3 positioned above and below the organic resin insulating layer 2 with the through-hole conductor 9 interposed therebetween is electrically connected.
【0031】前記各有機樹脂絶縁層2の上面及びスルー
ホール8内に配設される薄膜配線導体3及びスルーホー
ル導体9は銅、ニッケル、金、アルミニウム等の金属材
料を無電解めっき法や蒸着法、スパッタリング法等の薄
膜形成技術及びエッチング加工技術を採用することによ
って形成され、例えば銅で形成されている場合には、有
機樹脂絶縁層2の上面及びスルーホール8の内表面に硫
酸銅0.06モル/リットル、ホルマリン0.3モル/
リットル、水酸化ナトリウム0.35モル/リットル、
エチレンジアミン四酢酸0.35モル/リットルからな
る無電解銅メッキ浴を用いて厚さ1μm乃至40μmの
銅層を被着させ、しかる後、前記銅層をエッチング加工
法により所定パターンに加工することによって各有機樹
脂絶縁層2間及び各有機樹脂絶縁層2のスルーホール8
内壁に配設される。この場合、薄膜配線導体3は薄膜形
成技術により形成されることから配線の微細化が可能で
あり、これによって薄膜配線導体3を極めて高密度に形
成することが可能となる。The thin-film wiring conductor 3 and the through-hole conductor 9 provided on the upper surface of each of the organic resin insulating layers 2 and in the through-holes 8 are made of a metal material such as copper, nickel, gold, or aluminum by electroless plating or vapor deposition. For example, in the case of being formed of copper, copper sulfate is formed on the upper surface of the organic resin insulating layer 2 and the inner surface of the through hole 8 when the thin film forming technique and the etching technique are employed. 0.06 mol / liter, formalin 0.3 mol /
Liter, sodium hydroxide 0.35 mol / l,
A copper layer having a thickness of 1 μm to 40 μm is applied using an electroless copper plating bath composed of 0.35 mol / liter of ethylenediaminetetraacetic acid, and thereafter, the copper layer is processed into a predetermined pattern by an etching method. Between each organic resin insulating layer 2 and through hole 8 in each organic resin insulating layer 2
It is arranged on the inner wall. In this case, since the thin-film wiring conductor 3 is formed by a thin-film forming technique, the wiring can be miniaturized, whereby the thin-film wiring conductor 3 can be formed at an extremely high density.
【0032】尚、前記多層配線部4は各有機樹脂絶縁層
2の厚みが100μmを越えると有機樹脂絶縁層2にフ
ォトリソグラフィー技術を採用することによってスルー
ホール8を形成する際、エッチングの加工時間が長くな
ってスルーホール8を所望する鮮明な形状に形成するの
が困難となり、また5μm未満となると有機樹脂絶縁層
2の上面に上下に位置する有機樹脂絶縁層2の接合強度
を上げるための粗面加工を施す際、有機樹脂絶縁層2に
不要な穴が形成され上下に位置する薄膜配線導体3に不
要な電気的短絡を招来してしまう危険性がある。従っ
て、前記有機樹脂絶縁層2はその各々の厚みを5μm乃
至100μmの範囲としておくことが好ましい。When the thickness of each organic resin insulating layer 2 exceeds 100 μm, the multi-layer wiring portion 4 employs a photolithography technique in the organic resin insulating layer 2 to form a through hole 8 by using an etching processing time. Becomes longer, making it difficult to form the through hole 8 into a desired sharp shape. If the thickness is less than 5 μm, the bonding strength of the organic resin insulating layer 2 located above and below the organic resin insulating layer 2 is increased. When roughening is performed, there is a risk that unnecessary holes may be formed in the organic resin insulating layer 2 and unnecessary electrical short circuits may occur in the thin film wiring conductors 3 located above and below. Therefore, it is preferable that the thickness of each of the organic resin insulating layers 2 is in the range of 5 μm to 100 μm.
【0033】また前記多層配線部4の各薄膜配線導体2
はその厚みが1μm未満となると各薄膜配線導体3の電
気抵抗が大きなものとなって各薄膜配線導体3に所定の
電気信号を伝達させることが困難なものとなり、また4
0μmを越えると薄膜配線導体3を有機樹脂絶縁層2に
被着させる際、薄膜配線導体3内に大きな応力が内在
し、該内在応力によって薄膜配線導体3が有機樹脂絶縁
層2より剥離し易いものとなる。従って、前記多層配線
部4の各薄膜配線導体2の厚みを1μm乃至40μmの
範囲としておくことが好ましい。Each of the thin film wiring conductors 2 of the multilayer wiring portion 4
When the thickness is less than 1 μm, the electric resistance of each thin-film wiring conductor 3 becomes large, and it becomes difficult to transmit a predetermined electric signal to each thin-film wiring conductor 3.
If the thickness exceeds 0 μm, when the thin film wiring conductor 3 is applied to the organic resin insulating layer 2, a large stress is present inside the thin film wiring conductor 3, and the thin film wiring conductor 3 is easily peeled off from the organic resin insulating layer 2 due to the intrinsic stress. It will be. Therefore, it is preferable that the thickness of each thin-film wiring conductor 2 of the multilayer wiring section 4 be set in a range of 1 μm to 40 μm.
【0034】更に前記薄膜配線導体3はその表面が中心
線平均粗さ(Ra)で0.05μm≦Ra≦5μm、表
面の2.5mmの長さにおける凹凸の高さ(Pc)のカ
ウント値を0.01μm≦Pc≦0.1μmが3000
0個以上、0.1μm≦Pc≦1μmが3000個乃至
10000個、1μm≦Pc≦10μmが500個以下
となるように粗しておくと有機樹脂絶縁層2と薄膜配線
導体3とはその接合面積が極めて広いものとなり、その
結果、有機樹脂絶縁層2と薄膜配線導体3との密着性が
著しく向上し、有機樹脂絶縁層2や薄膜配線導体3に外
力が印加されても該外力によって有機樹脂絶縁層2と薄
膜配線導体3との間に剥離が発生することはなく、両者
の接合を極めて強固となすことができる。従って、前記
薄膜配線導体3はその表面が中心線平均粗さ(Ra)で
0.05μm≦Ra≦5μm、表面の2.5mmの長さ
における凹凸の高さ(Pc)のカウント値を0.01μ
m≦Pc≦0.1μmが30000個以上、0.1μm
≦Pc≦1μmが3000個乃至10000個、1μm
≦Pc≦10μmが500個以下となるように粗してお
くことが好ましい。Further, the surface of the thin film wiring conductor 3 has a center line average roughness (Ra) of 0.05 μm ≦ Ra ≦ 5 μm, and the count value of the height of irregularities (Pc) at a length of 2.5 mm on the surface. 0.01 μm ≦ Pc ≦ 0.1 μm is 3000
If it is roughened so that 0 or more, and 0.1 μm ≦ Pc ≦ 1 μm is 3000 to 10000, and 1 μm ≦ Pc ≦ 10 μm is 500 or less, the bonding between the organic resin insulating layer 2 and the thin film wiring conductor 3 is made. The area becomes extremely large, and as a result, the adhesion between the organic resin insulating layer 2 and the thin film wiring conductor 3 is remarkably improved, and even when an external force is applied to the organic resin insulating layer 2 and the thin film wiring conductor 3, the organic force is reduced by the external force. No separation occurs between the resin insulating layer 2 and the thin-film wiring conductor 3, and the bonding between them can be made extremely strong. Accordingly, the surface of the thin film wiring conductor 3 has a center line average roughness (Ra) of 0.05 μm ≦ Ra ≦ 5 μm, and the count value of the height of irregularities (Pc) at a length of 2.5 mm of the surface is 0. 01μ
m ≦ Pc ≦ 0.1 μm: 30,000 or more, 0.1 μm
≦ Pc ≦ 1 μm: 3000 to 10000, 1 μm
It is preferable to roughen so that ≦ Pc ≦ 10 μm becomes 500 or less.
【0035】また更に前記有機樹脂絶縁層2は、その少
なくとも一層の上面に薄膜抵抗体層10が被着されお
り、該薄膜抵抗体層10はその両端に一対の薄膜配線導
体3を接触させることによって薄膜配線導体3間に抵抗
素子Aが電気的に接続されている。Further, the organic resin insulating layer 2 has a thin-film resistor layer 10 attached to at least one upper surface thereof, and the thin-film resistor layer 10 is brought into contact with a pair of thin-film wiring conductors 3 at both ends. Thereby, the resistance element A is electrically connected between the thin film wiring conductors 3.
【0036】前記薄膜抵抗体層10は窒化タンタル、タ
ンタルシリサイド、ニッケル・クロム、ニッケル・クロ
ムシリサイド、モリブデンシリサイド、タングステンシ
リサイド、チタンシリサイド、ニッケルシリサイド、ク
ロムシリサイド、ニオブシリケート、タンタルシリケー
トの少なくとも1種からなり、スパッタリング法や蒸着
法及びエッチング加工法等を採用することによって有機
樹脂絶縁層2の上面で、一対の薄膜配線導体3間に形成
される。The thin film resistor layer 10 is made of at least one of tantalum nitride, tantalum silicide, nickel chromium, nickel chromium silicide, molybdenum silicide, tungsten silicide, titanium silicide, nickel silicide, chromium silicide, niobium silicate, and tantalum silicate. In other words, by adopting a sputtering method, a vapor deposition method, an etching method, or the like, it is formed between the pair of thin film wiring conductors 3 on the upper surface of the organic resin insulating layer 2.
【0037】尚、前記薄膜抵抗体層10はそれをタンタ
ルシリケートで形成しておくと薄膜抵抗体層10を有機
樹脂絶縁層2に強固に接合させて形成することができ
る。従って、前記薄膜抵抗体層10はそれをタンタルシ
リケートで形成しておくことが好ましい。When the thin film resistor layer 10 is formed of tantalum silicate, it can be formed by firmly joining the thin film resistor layer 10 to the organic resin insulating layer 2. Therefore, it is preferable that the thin film resistor layer 10 is formed of tantalum silicate.
【0038】また前記抵抗素子Aは絶縁基板1上に設け
た多層配線部4の内部に内蔵されており、そのためこの
多層配線基板に半導体素子や容量素子、抵抗素子等の部
品を搭載して混成集積回路装置等となす場合、多層配線
基板に別途、抵抗素子を多数実装する必要はなく、その
結果、多層配線基板に実装される部品の数が減り、混成
集積回路装置等を小型となすことが可能となる。The resistance element A is built in the multilayer wiring section 4 provided on the insulating substrate 1. Therefore, components such as semiconductor elements, capacitance elements and resistance elements are mounted on the multilayer wiring board and mixed. In the case of an integrated circuit device, it is not necessary to separately mount a large number of resistance elements on the multilayer wiring board. As a result, the number of components mounted on the multilayer wiring board is reduced, and the size of the hybrid integrated circuit device is reduced. Becomes possible.
【0039】更に前記薄膜抵抗体層10はその厚みが
0.1μm未満であると薄膜抵抗体層10に欠陥が生
じ、安定した特性を得ることが困難となる傾向にあり、
また5μmを越えると薄膜抵抗体層10を形成する際に
内部に応力が生じ、該応力によって薄膜抵抗体層10が
有機樹脂絶縁層2より剥離し易くなる傾向にある。従っ
て、前記薄膜抵抗体層10はその厚みを0.1μm乃至
5μmの範囲としておくことが好ましい。Further, if the thickness of the thin film resistor layer 10 is less than 0.1 μm, defects tend to occur in the thin film resistor layer 10 and it tends to be difficult to obtain stable characteristics.
On the other hand, when the thickness exceeds 5 μm, stress is generated inside the thin film resistor layer 10 when the thin film resistor layer 10 is formed, and the thin film resistor layer 10 tends to be easily separated from the organic resin insulating layer 2 by the stress. Therefore, it is preferable that the thickness of the thin film resistor layer 10 be in the range of 0.1 μm to 5 μm.
【0040】また更に前記薄膜抵抗体層10に一対の薄
膜配線導体3を接触させて成る抵抗素子Aはその電気抵
抗値が一対の薄膜配線導体3間に配される薄膜抵抗体層
10の長さ及び薄膜抵抗体層の導電率によって決定さ
れ、一対の薄膜配線導体3間に配される薄膜抵抗体層1
0の長さを可変することによって抵抗素子Aの電気抵抗
値が任意の所定値に調整される。Further, the resistance element A formed by bringing a pair of thin film wiring conductors 3 into contact with the thin film resistor layer 10 has an electric resistance value equal to the length of the thin film resistor layer 10 disposed between the pair of thin film wiring conductors 3. And the conductivity of the thin-film resistor layer, and the thin-film resistor layer 1 disposed between the pair of thin-film wiring conductors 3
By changing the length of 0, the electric resistance value of the resistance element A is adjusted to an arbitrary predetermined value.
【0041】かくして本発明の多層配線基板によれば、
例えば、絶縁基板1の上面に被着させた多層配線部4上
に半導体素子等の能動部品や容量素子、抵抗素子等の受
動部品を実装させることによって混成集積回路装置とな
り、絶縁基板1の下面に被着されている導電層6を外部
電気回路に接続すればかかる混成集積回路装置が外部電
気回路に電気的に接続されることとなる。Thus, according to the multilayer wiring board of the present invention,
For example, a hybrid integrated circuit device is obtained by mounting active components such as semiconductor elements and passive components such as capacitance elements and resistance elements on the multilayer wiring portion 4 attached to the upper surface of the insulating substrate 1, and the lower surface of the insulating substrate 1 Is connected to an external electric circuit, the hybrid integrated circuit device is electrically connected to the external electric circuit.
【0042】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば、上述の実施例において
は絶縁基板1の上面のみに有機樹脂絶縁層2と薄膜配線
導体3とから成る多層配線部4を設けたが、多層配線部
4を絶縁基板1の下面側のみに設けても、上下の両主面
に設けてもよい。It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. Is provided only on the upper surface of the substrate, the multilayer wiring portion 4 including the organic resin insulating layer 2 and the thin film wiring conductor 3 is provided. However, the multilayer wiring portion 4 may be provided only on the lower surface side of the insulating substrate 1 or provided on both upper and lower main surfaces. You may.
【0043】[0043]
【発明の効果】本発明の多層配線基板によれば、絶縁基
板上に薄膜形成技術によって配線を形成したことから配
線の微細化が可能となり、配線を極めて高密度に形成す
ることが可能となる。According to the multilayer wiring board of the present invention, since the wiring is formed on the insulating substrate by the thin film forming technique, the wiring can be miniaturized and the wiring can be formed at an extremely high density. .
【0044】また本発明の多層配線基板によれば、複数
の有機樹脂絶縁層と複数の薄膜配線導体とを交互に多層
に配設して成る多層配線部の少なくとも一つの有機樹脂
絶縁層上に薄膜抵抗体層を被着させるとともに該薄膜抵
抗体層に少なくとも一対の薄膜配線導体の一部を接触さ
せ、薄膜配線導体間に抵抗素子を電気的に接続させたこ
とから多層配線基板に半導体素子や容量素子、抵抗素子
等の部品を搭載して混成集積回路装置等となす場合、多
層配線基板に別途、抵抗素子を多数実装する必要はな
く、その結果、多層配線基板に実装される部品の数が減
り、混成集積回路装置等を小型となすことが可能とな
る。Further, according to the multilayer wiring board of the present invention, a plurality of organic resin insulating layers and a plurality of thin film wiring conductors are alternately arranged in multiple layers on at least one organic resin insulating layer of a multilayer wiring portion. Since the thin-film resistor layer is applied and at least a part of the pair of thin-film wiring conductors is brought into contact with the thin-film resistor layer, and the resistive element is electrically connected between the thin-film wiring conductors, the semiconductor element is mounted on the multilayer wiring board. When a hybrid integrated circuit device is formed by mounting components such as a capacitor, a resistor, and a resistor, it is not necessary to separately mount a large number of resistors on the multilayer wiring board. The number is reduced, and the size of the hybrid integrated circuit device or the like can be reduced.
【図1】本発明の多層配線基板の一実施例を示す断面図
である。FIG. 1 is a sectional view showing one embodiment of a multilayer wiring board of the present invention.
1・・・絶縁基板 2・・・有機樹脂絶縁層 3・・・薄膜配線導体 4・・・多層配線部 5・・・貫通孔 6・・・導電層 7・・・有機樹脂充填体 10・・薄膜抵抗体層 A・・・抵抗素子 DESCRIPTION OF SYMBOLS 1 ... Insulating board 2 ... Organic resin insulating layer 3 ... Thin film wiring conductor 4 ... Multilayer wiring part 5 ... Through-hole 6 ... Conductive layer 7 ... Organic resin filler 10 ...・ Thin film resistor layer A ・ ・ ・ Resistor element
Claims (3)
基板と、該絶縁基板の上面から貫通孔内壁を経て下面に
導出する導電層と、前記貫通孔の内部に充填された有機
樹脂充填体と、前記絶縁基板の少なくとも一主面上に被
着され、複数の有機樹脂絶縁層と複数の薄膜配線導体と
を交互に多層に配設するとともに薄膜配線導体の一部が
前記導電層に電気的に接続されている多層配線部とから
成る多層配線基板であって、前記少なくとも一つの有機
樹脂絶縁層上に薄膜抵抗体層を被着させるとともに該薄
膜抵抗体層に少なくとも一対の薄膜配線導体の一部を接
触させ、薄膜配線導体間に抵抗素子を電気的に接続させ
たことを特徴とする多層配線基板。An insulating substrate having a through hole penetrating both upper and lower main surfaces, a conductive layer extending from an upper surface of the insulating substrate to a lower surface via an inner wall of the through hole, and an organic resin filled in the through hole A filler and a plurality of organic resin insulating layers and a plurality of thin film wiring conductors are alternately disposed on the at least one main surface of the insulating substrate, and a part of the thin film wiring conductor is formed on the conductive layer. A multi-layer wiring board electrically connected to the at least one organic resin insulating layer, wherein a thin-film resistor layer is applied on the at least one organic resin insulating layer, and at least one pair of thin films is formed on the thin-film resistor layer. A multilayer wiring board wherein a part of a wiring conductor is brought into contact and a resistive element is electrically connected between thin film wiring conductors.
シリサイド、ニッケル・クロム、ニッケル・クロムシリ
サイド、モリブデンシリサイド、タングステンシリサイ
ド、チタンシリサイド、ニッケルシリサイド、クロムシ
リサイド、ニオブシリケート、タンタルシリケートの少
なくとも1種からなることを特徴とする請求項1に記載
の多層配線基板。2. The thin film resistor is made of at least one of tantalum nitride, tantalum silicide, nickel chromium, nickel chrome silicide, molybdenum silicide, tungsten silicide, titanium silicide, nickel silicide, chromium silicide, niobium silicate, and tantalum silicate. The multilayer wiring board according to claim 1, wherein:
μmであることを特徴とする請求項1に記載の多層配線
基板。3. A thin film resistor having a thickness of 0.1 μm to 5 μm.
The multilayer wiring board according to claim 1, wherein the thickness is μm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8197908A JPH1041632A (en) | 1996-07-26 | 1996-07-26 | Multilayer wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8197908A JPH1041632A (en) | 1996-07-26 | 1996-07-26 | Multilayer wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH1041632A true JPH1041632A (en) | 1998-02-13 |
Family
ID=16382283
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8197908A Pending JPH1041632A (en) | 1996-07-26 | 1996-07-26 | Multilayer wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH1041632A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11284339A (en) * | 1998-03-26 | 1999-10-15 | Ibiden Co Ltd | Manufacture of multi-layer printed circuit board |
JP2002314028A (en) * | 2001-04-17 | 2002-10-25 | Iep Technologies:Kk | Semiconductor device, manufacturing method therefor, and mounting structure thereof |
WO2003007379A1 (en) * | 2001-07-12 | 2003-01-23 | Hitachi, Ltd. | Electronic circuit component |
-
1996
- 1996-07-26 JP JP8197908A patent/JPH1041632A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11284339A (en) * | 1998-03-26 | 1999-10-15 | Ibiden Co Ltd | Manufacture of multi-layer printed circuit board |
JP2002314028A (en) * | 2001-04-17 | 2002-10-25 | Iep Technologies:Kk | Semiconductor device, manufacturing method therefor, and mounting structure thereof |
KR100885352B1 (en) * | 2001-04-17 | 2009-02-26 | 가시오게산키 가부시키가이샤 | Semiconductor Device And Manufacturing Method Thereof |
WO2003007379A1 (en) * | 2001-07-12 | 2003-01-23 | Hitachi, Ltd. | Electronic circuit component |
US7586755B2 (en) | 2001-07-12 | 2009-09-08 | Hitachi, Ltd. | Electronic circuit component |
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