JP3688844B2 - Multilayer wiring board - Google Patents

Multilayer wiring board Download PDF

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Publication number
JP3688844B2
JP3688844B2 JP04367797A JP4367797A JP3688844B2 JP 3688844 B2 JP3688844 B2 JP 3688844B2 JP 04367797 A JP04367797 A JP 04367797A JP 4367797 A JP4367797 A JP 4367797A JP 3688844 B2 JP3688844 B2 JP 3688844B2
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Japan
Prior art keywords
organic resin
layer
thin film
wiring conductor
layers
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JP04367797A
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Japanese (ja)
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JPH10242651A (en
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健士 久米
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Kyocera Corp
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Kyocera Corp
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Description

【0001】
【発明の属する技術分野】
本発明は多層配線基板に関し、より詳細には混成集積回路装置や半導体素子を収容する半導体素子収納用パッケージ等に使用される多層配線基板に関するものである。
【0002】
【従来の技術】
従来、半導体素子等の能動部品や容量素子、抵抗器等の自動部品を多数搭載し、所定の電子回路を構成するようになした混成集積回路装置は、通常、絶縁基板の内部及び表面にタングステン、モリブデン等の高融点金属粉末から成る配線導体を形成した構造の配線基板を準備し、次に前記配線基板の表面に半導体素子や容量素子、抵抗器等を搭載取着するとともに該半導体素子等の電極を前記配線導体に接続することによって混成集積回路装置となる。
【0003】
かかる従来の混成集積回路装置等に使用される配線基板は一般にセラミックスの積層技術及びスクリーン印刷法等の厚膜技術を採用することによって製作されており、具体的には以下の方法によって製作されている。
【0004】
即ち、
(1)まず、アルミナ等の電気絶縁性に優れたセラミック原料粉末に有機溶剤、溶媒を添加混合して複数枚のセラミック生シートを得るとともに該各セラミック生シートの上下面にタングステン、モリブデン等の高融点金属粉末から成る導電ペーストを従来周知のスクリーン印刷法等の厚膜技術を採用することによって所定パターンに印刷塗布する。
【0005】
(2)次に前記各セラミック生シートを積層し、積層体を得るとともにこれを約1500℃の温度で焼成し、内部及び表面にタングステン、モリブデン等の高融点金属粉末から成る配線導体を有する絶縁基板を得る。
【0006】
(3)そして最後に、前記配線導体のうち、大気中に露出する表面にニッケル及び金等の耐蝕性に優れ、良導電性で、半田等のロウ材と濡れ性(反応性)の良い金属をめっき法により被着させ、これによって製品としての配線基板が完成する。
【0007】
【発明が解決しようとする課題】
しかしながら、この従来の配線基板においては、配線導体がタングステンやモリブデン等の高融点金属粉末から成る導電ペーストをスクリーン印刷法等の厚膜技術を採用し、所定パターンに印刷塗布することによって形成されており、配線導体の微細化が困難で配線導体を高密度に形成することができないという欠点を有していた。
【0008】
またこの従来の配線基板は表面に半導体素子等の能動部品や容量素子、抵抗器等の受動部品が多数搭載され、部品の搭載数に応じて大型化してしまうという欠点も有していた。
【0009】
本発明は上述の欠点に鑑み案出されたもので、その目的は配線導体を薄膜技術により形成される薄膜配線導体とすることによって配線を高密度とし、かつ内部に容量素子を内蔵することによって混成集積回路装置等としたとき装置を小型となすことができる多層配線基板を提供することにある。
【0010】
【課題を解決するための手段】
本発明の多層配線基板は、基板上に、有機樹脂絶縁層と薄膜配線導体層とを交互に多層に配設するとともに上下に位置する薄膜配線導体層を各有機樹脂絶縁層に設けたスルーホール導体を介して接続してなる多層配線基板であって、前記有機樹脂絶縁層の少なくとも1層に穴部を設け、該穴部内に誘電体磁器を挿入させるとともに該誘電体磁器の上下面に厚み2μm〜40μmの有機樹脂層を介し薄膜配線導体層の一部を対向配置させて該対向する薄膜配線導体層間に容量素子を電気的に接続したことを特徴とするものである。
【0011】
また本発明は、前記有機樹脂層の厚みが2μm乃至40μmであることを特徴とするものである。
【0012】
更に本発明は、前記有機樹脂層に、酸化珪素、酸化アルミニウム、窒化アルミニウム、チタン酸化合物、ジルコン酸化合物の少なくとも1種から成る粉末を10重量%乃至95重量%含有させたことを特徴とするものである。
【0013】
本発明の多層配線基板によれば、配線導体を薄膜技術によって形成したことから配線導体の微細化が可能となり、配線導体を極めて高密度に形成することが可能となる。
【0014】
また本発明の多層配線基板によれば、有機樹脂絶縁層に穴部を設け、該穴部内に誘電体磁器を挿入させるとともに誘電体磁器の上下面に薄膜配線導体層の一部を対向配置させたことから、誘電体磁器の比誘電率、厚み、幅、長さを調整することによって所定の静電容量値を有する容量素子を任意数内蔵させることができ、多層配線基板に半導体素子や容量素子、抵抗器等の部品を搭載して混成集積回路装置となす場合、多層配線基板に別途容量素子を多数実装する必要はなく、その結果、多層配線基板に実装される部品の数が減り、混成集積回路装置等を小型となすこともできる。
【0015】
更に本発明の多層配線基板によれば、誘電体磁器の上下面と薄膜配線導体層との間に有機樹脂層を介在させたことから有機樹脂層によって誘電体磁器と薄膜配線導体層との接合が強固となり、薄膜配線導体層の所定位置に所定静電容量値の容量素子を高い信頼性で電気的接続することが可能となるとともに有機樹脂絶縁層に設けた穴が誘電体磁器と有機樹脂層とによって完全に埋められ、上部に位置する有機樹脂絶縁層を平坦として薄膜配線導体層を断線等を招来することなく所定パターンに形成することが可能となる。
【0016】
【発明の実施の形態】
次に本発明を添付図面に基づき詳細に説明する。
図1及び図2は、本発明の多層配線基板の一実施例を示し、1は基板、2は多層配線部である。
【0017】
前記基板1はその上面に3つの有機樹脂絶縁層3a、3b、3cと3つの薄膜配線導体層4a、4b、4cを交互に多層に配設して成る多層配線部2が形成されており、該多層配線部2を支持する支持部材として作用する。
【0018】
前記基板1は酸化アルミニウム質焼結体やムライト質焼結体等の酸化物系セラミックス、或いは表面に酸化物膜を有する窒化アルミニウム質焼結体や炭化珪素質焼結体等の非酸化物系セラミックス、更にはガラス繊維を織り込んだ布にエポキシ樹脂やビスマレイミドトリアジン樹脂を含浸させたガラスエポキシ樹脂基板やビスマレイミドトリアジン基板等の電気絶縁材料で形成されており、例えば、酸化アルミニウム質焼結体で形成されている場合には、アルミナ、シリカ、カルシア、マグネシア等の原料粉末に適当な有機溶剤、溶媒を添加混合して泥漿状となすとともにこれを従来周知のドクターブレード法やカレンダーロール法を採用することによってセラミックグリーンシート(セラミック生シート)を形成し、しかる後、前記セラミックグリーンシートに適当な打ち抜き加工を施し、所定形状となすとともに高温(約1600℃)で焼成することによって、或いはアルミナ等の原料粉末に適当な有機溶剤、溶媒を添加混合して原料粉末を調整するとともに該原料粉末をプレス成形機によって所定形状に成形し、最後に前記成形体を約1600℃の温度で焼成することによって製作され、またガラスエポキシ樹脂基板やビスマレイミドトリアジン基板等で形成されている場合は、ガラス繊維を織り込んだ布にエポキシ樹脂やビスマレイミドトリアジン樹脂の前駆体を含浸させたものを複数枚積層し、しかる後、前記エポキシ樹脂やビスマレイミドトリアジン樹脂の前駆体を所定の温度(100℃〜200℃)で熱硬化させることによって製作される。
【0019】
また前記基板1には上下両主面に貫通する孔径が例えば、直径300μm〜500μmの貫通孔5が形成されており、該貫通孔5の内壁には両端が基板1の上下両面に導出する導電層6が被着されている。
【0020】
前記貫通孔5は後述する基板1の上面に形成される多層配線部2の薄膜配線導体層4aと外部電気回路とを電気的に接続する、或いは基板1の上下両主面に多層配線部2を配設した場合には両主面の多層配線部2の薄膜配線導体層同士を電気的に接続する導電層6を形成するための形成孔として作用し、基板1にドリル孔あけ加工法を施すことによって基板1の所定位置に所定形状に形成される。
【0021】
更に前記貫通孔5の内壁及び基板1の上下両面に被着形成されている導電層6は例えば、銅やニッケル等の金属材料から成り、従来周知のめっき法及びエッチング法を採用することによって貫通孔5の内壁に両端を基板1の上下両面に導出させた状態で被着形成される。
【0022】
前記導電層6は基板1の主面に配設される多層配線部2の薄膜配線導体層3aを外部電気回路に電気的に接続したり、基板1の上下両主面に配設される各々の多層配線部2の薄膜配線導体層同士を電気的に接続する作用をなす。
【0023】
また前記基板1に形成した貫通孔5はその内部にエポキシ樹脂から成る有機樹脂充填体7が充填されており、該有機樹脂充填体7によって貫通孔5が完全に埋められ、同時に有機樹脂充填体7の両端面が基板1の上下両主面に被着させた導電層6の面と同一平面となっている。
【0024】
前記有機樹脂充填体7は基板1の上面及び/又は下面に後述する複数の有機樹脂絶縁層3a、3b、3cと複数の薄膜配線導体層4a、4b、4cとから成る多層配線部2を形成する際、多層配線部2の各有機樹脂絶縁層3a、3b、3cと各薄膜配線導体層4a、4b、4cの平坦化を維持する作用をなす。
【0025】
なお、前記有機樹脂充填体7は基板1の貫通孔5内にエポキシ樹脂の前駆体を充填し、しかる後、これに80℃〜200℃の温度を0.5〜3時間印加し、完全に熱硬化させることによって基板1の貫通孔5内に充填される。
【0026】
更に前記基板1はその上面に3つの有機樹脂絶縁層3a、3b、3cと3つの薄膜配線導体層4a、4b、4cとが交互に多層に配設された多層配線部2が形成されており、かつ薄膜配線導体層4aは導電層6と電気的に接続されている。
【0027】
前記多層配線部2を構成する有機樹脂絶縁層3a、3b、3cは上下に位置する薄膜配線導体層4a、4b、4cの電気的絶縁を図る作用をなし、各薄膜配線導体層4a、4b、4cは電気信号を伝達するための伝達路として作用する。
【0028】
前記多層配線部2の各有機樹脂絶縁層3a、3b、3cは、エポキシ樹脂、ビスマレイミドポリアジド樹脂、ポリフェニレンエーテル樹脂、ふっ素樹脂等の有機樹脂から成り、例えば、エポキシ樹脂から成る場合、ビスフェノールA型エポキシ樹脂、ノボラック型エポキシ樹脂、グリシジルエステル型エポキシ樹脂等にアミン系硬化剤、イミダゾール系硬化剤、酸無水物系硬化剤等の硬化剤を添加混合してペースト状のエポキシ樹脂前駆体を得るとともに該エポキシ樹脂前駆体を基板1の上部にスピンコート法により被着させ、しかる後、これを80〜200℃の熱で0.5〜3時間熱処理し、熱硬化させることによって形成される。
【0029】
また前記各有機樹脂絶縁層3a、3b、3cはその各々の所定位置に最小径が有機樹脂絶縁層2の厚みに対して約1.5倍程度のスルーホール8が形成されており、該スルーホール8は後述する有機樹脂絶縁層2を介して上下に位置する薄膜配線導体層3の各々を電気的に接続するスルーホール導体9を形成するための形成孔として作用する。
【0030】
前記各有機樹脂絶縁層3a、3b、3cに設けるスルーホール8は例えば、フォトリソグラフィー技術、具体的には各有機樹脂絶縁層3a、3b、3c上にレジスト材を塗布するとともにこれに露光、現像を施すことによって所定位置に所定形状の窓部を形成し、次に前記レジスト材の窓部にエッチング液を配し、レジスト材の窓部に位置する有機樹脂絶縁層3a、3b、3cを除去して、有機樹脂絶縁層3a、3b、3cに穴(スルーホール)を形成し、最後に前記レジスト材を有機樹脂絶縁層3a、3b、3c上より剥離させ除去することによって行われる。
【0031】
更に前記各有機樹脂絶縁層3a、3b、3cの各々の上面には所定パターンの薄膜配線導体層4a、4b、4cが、また各有機樹脂絶縁層3a、3b、3cに設けたスルーホール8の内壁にはスルーホール導体9が各々配設されており、スルーホール導体9によって有機樹脂絶縁層3a、3b、3cを間に挟んで上下に位置する各薄膜配線導体層4a、4b、4cが電気的に接続されるようになっている。
【0032】
前記各有機樹脂絶縁層3a、3b、3cの上面及びスルーホール8の内壁に配設される薄膜配線導体層4a、4b、4c及びスルーホール導体9は銅、ニッケル、金、アルミニウム等の金属材料を無電解めっき法や蒸着法、スパッタリング法等の薄膜技術及びフォトリソグラフィー技術を採用することによって形成され、例えば、銅で形成されている場合には、有機樹脂絶縁層3a、3b、3cの上面及びスルーホール8の内表面に、硫酸銅0.06モル/リットル、ホルマリン0.3モル/リットル、水酸化ナトリウム0.35モル/リットル、エチレンジアミン四酢酸0.35モル/リットルから成る無電解銅めっき浴を用いて厚さ1μm乃至40μmの銅層を被着させ、しかる後、前記銅層をフォトリソグラフィー技術により所定パターンに加工することによって各有機樹脂絶縁層3a、3b、3c間、及びスルーホール8内壁に配設される。この場合、薄膜配線導体層4a、4b、4c及びスルーホール導体9は薄膜技術により形成されることから配線の微細化が可能であり、これによって薄膜配線導体層4a、4b、4cを極めて高密度に形成することが可能となる。
【0033】
なお、前記多層配線部2は各有機樹脂絶縁層3a、3b、3cの厚みが100μmを越えると各有機樹脂絶縁層3a、3b、3cにフォトリソグラフィー技術を採用することによってスルーホール8を形成する際、エッチングの加工時間が長くなってスルーホール8を所望する鮮明な形状に形成するのが困難となり、また5μm未満となると各有機樹脂絶縁層3a、3b、3cの上面に上下に位置する有機樹脂絶縁層の接合強度を上げるための粗面加工を施す際、各有機樹脂絶縁層3a、3b、3cに不要な穴が形成され上下に位置する薄膜配線導体層4a、4b、4cに不要な電気的短絡を招来してしまう危険性がある。従って、前記有機樹脂絶縁層3a、3b、3cはその各々の厚みを5μm〜100μmの範囲としておくことが重要である。
【0034】
また前記多層配線部2の各薄膜配線導体層4a、4b、4cはその厚みが1μm未満となると各薄膜配線導体層4a、4b、4cの電気抵抗値が大きなものとなって各薄膜配線導体層4a、4b、4cに所定の電気信号を伝達させることが困難となり、また40μmを越えると薄膜配線導体層4a、4b、4cを有機樹脂絶縁層3a、3b、3cに被着させる際に薄膜配線導体層4a、4b、4cの内部に大きな応力が内在し、該大きな内在応力によって薄膜配線導体層4a、4b、4cが有機樹脂絶縁層3a、3b、3cから剥離し易いものとなる。従って、前記多層配線部2の各薄膜配線導体層4a、4b、4cの厚みは1μm〜40μmの範囲としておくことが好ましい。
【0035】
更に前記有機樹脂絶縁層3a、3b、3cと薄膜配線導体層4a、4b、4cとで形成形成される多層配線部2はその有機樹脂絶縁層3bに穴部Hが設けられているとともに該穴部H内に誘電体磁器10が挿入されており、該誘電体磁器10をその上下両面に配設されている薄膜配線導体層4a、4bの一部で対向挟持することによって容量素子Aが形成され、該容量素子Aは薄膜配線導体層4a、4bに電気的に接続されている。
【0036】
前記有機樹脂絶縁層3bに形成されている穴部Hは誘電体磁器10を収容するための空所として作用し、有機樹脂絶縁層3bにスルーホール8を形成するのと同様の方法、具体的には有機樹脂絶縁層3b上にレジスト材を塗布するとともにこれに露光、現像を施すことによって所定位置に所定形状の窓部を形成し、次に前記レジスト材の窓部にエッチング液を配し、レジスト材の窓部に位置する有機樹脂絶縁層3bを除去して、有機樹脂絶縁層3bに穴部Hを形成し、最後に前記レジスト材を有機樹脂絶縁層3b上より剥離させ除去することによって行われる。
【0037】
また前記有機樹脂絶縁層3bの穴部H内に挿入される誘電体磁器10はチタン酸バリウムやチタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム等の比誘電率が高い磁器から成り、例えば、チタン酸バリウムから成る場合、炭酸パリウム、酸化チタン、チタン酸マグネシウム等の原料粉末を仮焼、反応させてチタン酸バリウムを得、次にこれを微粉に粉砕するとともに適当な有機溶剤、溶媒を添加混合して泥漿物となし、最後に前記泥漿物をドクターブレード法やカレンダーロール法等によりグリーンシートとなすとともにこれを高温で焼成することによって製作される。
【0038】
前記有機樹脂絶縁層3bの穴部H内に挿入された誘電体磁器10の上下両面を薄膜配線導体層4a、4bの一部で対向挟持して成る容量素子Aはその静電容量値が誘電体磁器10の比誘電率、誘電体磁器10の厚み及び誘電体磁器10を挟んでの薄膜配線導体層4a、4bの対向面積によって決定され、誘電体磁器10の比誘電率や誘電体磁器10の厚み等を調整することによって所定の静電容量値が得られる。
【0039】
また前記容量素子Aは基板1上に設けた多層配線部2の内部に内蔵されており、そのためこの多層配線基板に半導体素子や容量素子、抵抗器等の部品を搭載して混成集積回路装置等となす場合、多層配線基板に別途、容量素子を多数搭載実装する必要はなく、その結果、多層配線基板に実装される部品の数が減り、混成集積回路装置等を小型となすことが可能となる。
【0040】
更に前記誘電体磁器10の上下両面を薄膜配線導体層4a、4bの一部で対向挟持して成る容量素子Aは図2に示す如く、誘電体磁器10の上下面と薄膜配線導体層4a、4bとの間に有機樹脂層11が配されている。
【0041】
前記有機樹脂層11は誘電体磁器10の上下面に薄膜配線導体層4a、4bを強固に接合させるとともに有機樹脂絶縁層3bに設けた穴部Hを誘電体磁器10とで完全に埋める作用をなし、これによって薄膜配線導体層4a、4bの所定位置に所定静電容量値の容量素子Aを高い信頼性で電気的接続することが可能となるとともに有機樹脂絶縁層3bの上部に位置する有機樹脂絶縁層3cを平坦として薄膜配線導体層4b、4c等を断線等を招来することなく所定パターンに形成することが可能となる。
【0042】
前記有機樹脂層11は有機樹脂絶縁層3bと同質の材料、具体的にはエポキシ樹脂、ビスマレイミドポリアジド樹脂、ポリフェニレンエーテル樹脂、ふっ素樹脂等の有機樹脂から成り、例えば、エポキシ樹脂から成る場合、ビスフェノールA型エポキシ樹脂、ノボラック型エポキシ樹脂、グリシジルエステル型エポキシ樹脂等にアミン系硬化剤、イミダゾール系硬化剤、酸無水物系硬化剤等の硬化剤を添加混合してペースト状のエポキシ樹脂前駆体を得るとともに該エポキシ樹脂前駆体を有機樹脂絶縁層3bの穴部H内に充填し、次に有機樹脂絶縁層3bの穴部H内に誘電体磁器10を挿入させるとともに該誘電体磁器10の上部に再度、前記エポキシ樹脂前駆体を適量充填させ、最後に前記エポキシ樹脂前駆体を80〜200℃の温度で熱処理し、熱硬化させることによって誘電体磁器10の上下面と薄膜配線導体層4a、4bとの間に配される。
【0043】
また前記有機樹脂層11はその厚みが2μm乃至40μmとなっており、厚みが2μm未満であると誘電体磁器10の上下面と薄膜配線導体層4a、4bとの接合が弱くなる傾向にあり、また40μmを超えると薄膜配線導体層4a、4b間に接続される容量素子Aの静電容量値が小さくなり、大きな静電容量値の容量素子Aを内蔵することが困難となる危険性がある。従って、前記有機樹脂層11はその厚みを2μm乃至40μmの範囲としておくことが好ましい。
【0044】
更に前記有機樹脂層11はその内部に酸化珪素、酸化アルミニウム、窒化アルミニウム、チタン酸化合物、ジルコン酸化合物の少なくとも1種から成る粉末を10重量%乃至95重量%含有させておくと、有機樹脂層11の表面に微小な凹凸が多量に形成されて薄膜配線導体層4a、4bと有機樹脂層11との接合面積が増大し、これによって両者の接合強度を大幅に向上させることができるとともに有機樹脂層11の熱膨張係数を調整し、熱が印加された際に有機樹脂層11が穴部Hより膨張突出しその上下に位置する薄膜配線導体層4a、4bを押圧して薄膜配線導体層4a、4bに断線等を招来させるのが有効に防止できる。従って、前記有機樹脂層11はその内部に酸化珪素、酸化アルミニウム、窒化アルミニウム、チタン酸化合物、ジルコン酸化合物の少なくとも1種から成る粉末を添加混合させておくことが好ましい。
【0045】
また更に前記有機樹脂層11の内部に酸化珪素や酸化アルミニウム、窒化アルミニウム、チタン酸化合物、ジルコン酸化合物等から成る粉末を添加混合させておく場合、その添加量が10重量%未満であると有機樹脂層11の熱膨張係数を充分に調整することができず、熱の印加によって有機樹脂層11の一部が穴部Hの上下側に膨張突出し、薄膜配線導体層4a、4bに断線等を招来させてしまう危険性があり、また95重量%を越えると有機樹脂層11の強度が劣化してしまう危険性がある。従って、前記有機樹脂層11の内部に酸化珪素や酸化アルミニウム、窒化アルミニウム、チタン酸化合物、ジルコン酸化合物等から成る粉末を添加混合させておく場合、粉末の添加量は10重量%乃至95重量%の範囲が好ましい。
【0046】
かくして上述の多層配線基板によれば、最上層の有機樹脂絶縁層2上面に設けたボンディングパッド10に半導体素子や容量素子等の電子部品Aの電極を熱圧着等により接続させ、電子部品Aの電極をボンディングパッド10を介して薄膜配線導体層3に電気的に接続させることによって半導体装置や混成集積回路装置となり、薄膜配線導体層3の一部を外部電気回路に接続すれば前記電子部品Aが外部電気回路に接続されることとなる。
【0047】
なお、本発明は上述の実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば上述の実施例においては基板1の上面側のみに複数の有機樹脂絶縁層3a、3b、3cと複数の薄膜配線導体層4a、4b、4cとを交互に積層して形成される多層配線部2を被着させたが、該多層配線部2を基板1の下面側のみに設けても、上下の両主面に設けてもよい。
【0048】
また上述の実施例において、有機樹脂絶縁層3a、3b、3cと薄膜配線導体層4a、4b、4cとを交互に多層に配設して形成される多層配線部2は各有機樹脂絶縁層3a、3b、3cの上面を中心線平均粗さ(Ra)で0.05μm≦Ra≦5μmの粗面としておくと有機樹脂絶縁層3a、3b、3cと薄膜配線導体層4a、4b、4cとの接合及び上下に位置する有機樹脂絶縁層3a、3b、3c同士の接合を強固となすことができる。従って、前記多層配線部2の各有機樹脂絶縁層3a、3b、3cはその上面をエッチング加工法等によって粗し、中心線平均粗さ(Ra)で0.05μm≦Ra≦5μmの粗面としておくことが好ましい。
【0049】
更に前記有機樹脂絶縁層3a、3b、3cはその表面の2.5mmの長さにおける凹凸の高さ(Pc)のカウント値を、1μm≦Pc≦10μmが500個以上、0.1μm≦Pc≦1μmが2500個以上、0.01μm≦Pc≦0.1μmが12500以上としておくと有機樹脂絶縁層3a、3b、3cと薄膜配線導体層4a、4b、4cとの接合及び上下に位置する有機樹脂絶縁層3a、3b、3c同士の接合がより強固となる。従って、前記有機樹脂絶縁層3a、3b、3cはその表面の2.5mmの長さにおける凹凸の高さ(Pc)のカウント値を、1μm≦Pc≦10μmが500個以上、0.1μm≦Pc≦1μmが2500個以上、0.01μm≦Pc≦0.1μmが12500以上としておくとことが好ましい。
【0050】
前記中心線平均粗さ(Ra)が0.05μm≦Ra≦5μm、2.5mmの長さにおける凹凸の高さ(Pc)のカウント値が、1μm≦Pc≦10μmが500個以上、0.1μm≦Pc≦1μmが2500個以上、0.01μm≦Pc≦0.1μmが12500以上の有機樹脂絶縁層3a、3b、3cは、該有機樹脂絶縁層3a、3b、3cの上面にCHF3 、CF4 、Ar等のガスを吹きつけリアクティブイオンエッチング処理をすることによって表面が所定の粗さに粗される。
【0051】
なお、前記有機樹脂絶縁層3a、3b、3c上面の中心線平均粗さ(Ra)及び2.5mmの長さにおける凹凸の高さ(Pc)のカウント値は、有機樹脂絶縁層3a、3b、3cの表面を原子間力顕微鏡(Digital Instruments Inc.製のDimension 3000-Nano Scope III)で50μm角の対角(70μm)に走査させてその表面状態を検査測定し、その測定結果より各々の数値を出した。
【0052】
【発明の効果】
本発明の多層配線基板によれば、基板上に薄膜技術によって配線を形成したことから配線の微細化が可能となり、配線を極めて高密度に形成することが可能となる。
【0053】
また本発明の多層配線基板によれば、有機樹脂絶縁層に穴部を設け、該穴部内に誘電体磁器を挿入させるとともに誘電体磁器の上下面に薄膜配線導体層の一部を対向配置させたことから、誘電体磁器の比誘電率、厚み、幅、長さを調整することによって所定の静電容量値を有する容量素子を任意数内蔵させることができ、多層配線基板に半導体素子や容量素子、抵抗器等の部品を搭載して混成集積回路装置となす場合、多層配線基板に別途容量素子を多数実装する必要はなく、その結果、多層配線基板に実装される部品の数が減り、混成集積回路装置等を小型となすこともできる。
【0054】
更に本発明の多層配線基板によれば、誘電体磁器の上下面と薄膜配線導体層との間に有機樹脂層を介在させたことから有機樹脂層によって誘電体磁器と薄膜配線導体層との接合が強固となり、薄膜配線導体層の所定位置に所定静電容量値の容量素子を高い信頼性で電気的接続することが可能となるとともに有機樹脂絶縁層に設けた穴が誘電体磁器と有機樹脂層とによって完全に埋められ、上部に位置する有機樹脂絶縁層を平坦として薄膜配線導体層を断線等を招来することなく所定パターンに形成することが可能となる。
【図面の簡単な説明】
【図1】本発明の多層配線基板の一実施例を示す断面図である。
【図2】図1に示す多層配線基板の要部拡大断面図である。
【符号の説明】
1・・・・・・・・・・・基板
2・・・・・・・・・・・多層配線部
3a、3b、3c・・・・有機樹脂絶縁層
4a、4b、4c・・・・薄膜配線導体層
8・・・・・・・・・・・スルーホール
9・・・・・・・・・・・スルーホール導体
10・・・・・・・・・・誘電体磁器
11・・・・・・・・・・有機樹脂層
A・・・・・・・・・・・容量素子
H・・・・・・・・・・・穴部
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board used for a hybrid integrated circuit device, a semiconductor element housing package for housing semiconductor elements, and the like.
[0002]
[Prior art]
Conventionally, a hybrid integrated circuit device in which a large number of active parts such as semiconductor elements and automatic parts such as capacitive elements and resistors are mounted to form a predetermined electronic circuit is usually provided with tungsten inside and on the surface of an insulating substrate. A wiring board having a structure in which a wiring conductor made of a refractory metal powder such as molybdenum is formed is prepared, and then a semiconductor element, a capacitor element, a resistor, etc. are mounted on the surface of the wiring board, and the semiconductor element, etc. By connecting these electrodes to the wiring conductor, a hybrid integrated circuit device is obtained.
[0003]
Wiring boards used in such conventional hybrid integrated circuit devices are generally manufactured by employing a thick film technology such as a ceramic lamination technique and a screen printing method. Specifically, the wiring board is manufactured by the following method. Yes.
[0004]
That is,
(1) First, a plurality of ceramic raw sheets are obtained by adding and mixing an organic solvent and a solvent to ceramic raw material powder having excellent electrical insulation properties such as alumina, and tungsten, molybdenum, etc. are formed on the upper and lower surfaces of each ceramic raw sheet. A conductive paste made of a refractory metal powder is printed and applied in a predetermined pattern by employing a conventional thick film technique such as a screen printing method.
[0005]
(2) Next, the ceramic raw sheets are laminated to obtain a laminated body, which is fired at a temperature of about 1500 ° C., and has an internal and surface having a wiring conductor made of a refractory metal powder such as tungsten or molybdenum. Get the substrate.
[0006]
(3) Finally, among the wiring conductors, the surface exposed to the atmosphere has excellent corrosion resistance such as nickel and gold, is highly conductive, and has good conductivity and brazing material such as solder and good wettability (reactivity). Is deposited by a plating method, thereby completing a wiring board as a product.
[0007]
[Problems to be solved by the invention]
However, in this conventional wiring substrate, the wiring conductor is formed by printing and applying a conductive paste made of a refractory metal powder such as tungsten or molybdenum to a predetermined pattern using a thick film technique such as screen printing. In addition, the wiring conductor is difficult to be miniaturized, and the wiring conductor cannot be formed at a high density.
[0008]
In addition, this conventional wiring board has a drawback in that a large number of active components such as semiconductor elements and passive components such as capacitors and resistors are mounted on the surface, and the size of the wiring board increases according to the number of components mounted.
[0009]
The present invention has been devised in view of the above-described drawbacks, and the object thereof is to increase the density of the wiring by making the wiring conductor a thin film wiring conductor formed by thin film technology, and to incorporate a capacitive element therein. An object of the present invention is to provide a multilayer wiring board capable of reducing the size of a hybrid integrated circuit device or the like.
[0010]
[Means for Solving the Problems]
The multilayer wiring board of the present invention has a through hole in which organic resin insulating layers and thin film wiring conductor layers are alternately arranged in multiple layers on the substrate, and thin film wiring conductor layers positioned above and below are provided in each organic resin insulating layer. A multilayer wiring board connected via a conductor, wherein a hole is provided in at least one layer of the organic resin insulating layer, a dielectric ceramic is inserted into the hole, and a thickness is formed on the upper and lower surfaces of the dielectric ceramic. A part of the thin film wiring conductor layer is disposed oppositely through an organic resin layer of 2 μm to 40 μm, and a capacitive element is electrically connected between the opposing thin film wiring conductor layers.
[0011]
In the present invention, the organic resin layer has a thickness of 2 μm to 40 μm.
[0012]
Furthermore, the present invention is characterized in that the organic resin layer contains 10 wt% to 95 wt% of a powder composed of at least one of silicon oxide, aluminum oxide, aluminum nitride, titanate compound, and zirconate compound. Is.
[0013]
According to the multilayer wiring board of the present invention, since the wiring conductor is formed by thin film technology, the wiring conductor can be miniaturized, and the wiring conductor can be formed at a very high density.
[0014]
Further, according to the multilayer wiring board of the present invention, a hole is provided in the organic resin insulating layer, a dielectric ceramic is inserted into the hole, and a part of the thin film wiring conductor layer is disposed opposite to the upper and lower surfaces of the dielectric ceramic. Therefore, by adjusting the relative permittivity, thickness, width, and length of the dielectric ceramic, an arbitrary number of capacitive elements having a predetermined capacitance value can be incorporated, and the multilayer wiring board can be equipped with semiconductor elements and capacitors. When a component such as an element or a resistor is mounted to form a hybrid integrated circuit device, it is not necessary to mount a large number of additional capacitive elements on the multilayer wiring board, and as a result, the number of components mounted on the multilayer wiring board is reduced. A hybrid integrated circuit device or the like can be downsized.
[0015]
Further, according to the multilayer wiring board of the present invention, since the organic resin layer is interposed between the upper and lower surfaces of the dielectric ceramic and the thin film wiring conductor layer, the bonding of the dielectric ceramic and the thin film wiring conductor layer by the organic resin layer is performed. This makes it possible to electrically connect a capacitive element having a predetermined capacitance value to a predetermined position of the thin-film wiring conductor layer with high reliability, and a hole provided in the organic resin insulating layer includes a dielectric ceramic and an organic resin. It is possible to form the thin film wiring conductor layer in a predetermined pattern without incurring disconnection or the like with the organic resin insulating layer located on the upper part being flat and flattened by the layer.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described in detail with reference to the accompanying drawings.
1 and 2 show an embodiment of a multilayer wiring board according to the present invention, where 1 is a substrate and 2 is a multilayer wiring portion.
[0017]
The substrate 1 has a multilayer wiring portion 2 formed by alternately arranging three organic resin insulating layers 3a, 3b, and 3c and three thin film wiring conductor layers 4a, 4b, and 4c on the upper surface thereof, Acts as a support member for supporting the multilayer wiring portion 2.
[0018]
The substrate 1 is an oxide ceramic such as an aluminum oxide sintered body or a mullite sintered body, or a non-oxide type such as an aluminum nitride sintered body or a silicon carbide sintered body having an oxide film on the surface. It is made of an electrically insulating material such as a glass epoxy resin substrate or a bismaleimide triazine substrate obtained by impregnating a ceramic or glass fiber woven cloth with an epoxy resin or a bismaleimide triazine resin. For example, an aluminum oxide sintered body If it is formed by a material powder such as alumina, silica, calcia, magnesia, etc., an appropriate organic solvent and solvent are added and mixed to form a mud, and this is treated with a conventionally known doctor blade method or calender roll method. A ceramic green sheet (ceramic green sheet) is formed by adopting the ceramic ceramic sheet. The green powder is appropriately punched and processed into a predetermined shape and fired at a high temperature (about 1600 ° C), or an appropriate organic solvent and solvent are added to the raw material powder such as alumina to adjust the raw material powder. At the same time, the raw material powder is formed into a predetermined shape by a press molding machine, and finally the molded body is manufactured by firing at a temperature of about 1600 ° C., and is formed of a glass epoxy resin substrate, a bismaleimide triazine substrate, or the like. If a glass fiber woven cloth is impregnated with a plurality of epoxy resin or bismaleimide triazine resin precursors, then the epoxy resin or bismaleimide triazine resin precursor is added at a predetermined temperature. It is manufactured by thermosetting at (100 ° C. to 200 ° C.).
[0019]
Further, the substrate 1 is formed with through holes 5 having a diameter of 300 μm to 500 μm, for example, penetrating through both upper and lower main surfaces. Both ends of the through hole 5 are led out to both upper and lower surfaces of the substrate 1. Layer 6 is applied.
[0020]
The through hole 5 electrically connects a thin film wiring conductor layer 4a of a multilayer wiring portion 2 formed on the upper surface of the substrate 1 to be described later and an external electric circuit, or the multilayer wiring portion 2 on both upper and lower main surfaces of the substrate 1. Is provided as a formation hole for forming the conductive layer 6 for electrically connecting the thin film wiring conductor layers of the multilayer wiring portion 2 on both main surfaces, and a drilling method is applied to the substrate 1. By applying, a predetermined shape is formed at a predetermined position of the substrate 1.
[0021]
Further, the conductive layer 6 deposited on both the inner wall of the through hole 5 and the upper and lower surfaces of the substrate 1 is made of a metal material such as copper or nickel, and penetrates by employing a conventionally known plating method and etching method. It is deposited on the inner wall of the hole 5 with both ends led out to the upper and lower surfaces of the substrate 1.
[0022]
The conductive layer 6 electrically connects the thin film wiring conductor layer 3a of the multilayer wiring portion 2 disposed on the main surface of the substrate 1 to an external electric circuit, or is disposed on both the upper and lower main surfaces of the substrate 1. The thin film wiring conductor layers of the multilayer wiring portion 2 are electrically connected to each other.
[0023]
The through hole 5 formed in the substrate 1 is filled with an organic resin filler 7 made of an epoxy resin, and the through hole 5 is completely filled with the organic resin filler 7, and at the same time, the organic resin filler 7, both end surfaces are flush with the surface of the conductive layer 6 deposited on the upper and lower main surfaces of the substrate 1.
[0024]
The organic resin filler 7 forms a multilayer wiring portion 2 composed of a plurality of organic resin insulating layers 3a, 3b and 3c, which will be described later, and a plurality of thin film wiring conductor layers 4a, 4b and 4c on the upper surface and / or the lower surface of the substrate 1. In this case, the organic resin insulating layers 3a, 3b, and 3c of the multilayer wiring portion 2 and the thin film wiring conductor layers 4a, 4b, and 4c are maintained flat.
[0025]
The organic resin filler 7 is filled with a precursor of epoxy resin in the through-hole 5 of the substrate 1, and then a temperature of 80 ° C. to 200 ° C. is applied to this for 0.5 to 3 hours to completely The through holes 5 of the substrate 1 are filled by thermosetting.
[0026]
Further, the substrate 1 is provided with a multilayer wiring part 2 in which three organic resin insulating layers 3a, 3b, 3c and three thin film wiring conductor layers 4a, 4b, 4c are alternately arranged in multiple layers on the upper surface. The thin-film wiring conductor layer 4a is electrically connected to the conductive layer 6.
[0027]
The organic resin insulating layers 3a, 3b, 3c constituting the multilayer wiring portion 2 serve to electrically insulate the thin film wiring conductor layers 4a, 4b, 4c located above and below, and the thin film wiring conductor layers 4a, 4b, 4c acts as a transmission path for transmitting electrical signals.
[0028]
Each of the organic resin insulating layers 3a, 3b, 3c of the multilayer wiring portion 2 is made of an organic resin such as an epoxy resin, a bismaleimide polyazide resin, a polyphenylene ether resin, or a fluorine resin. Type epoxy resin, novolac type epoxy resin, glycidyl ester type epoxy resin, etc., and adding a curing agent such as amine curing agent, imidazole curing agent, acid anhydride curing agent, etc. to obtain a pasty epoxy resin precursor At the same time, the epoxy resin precursor is deposited on the upper portion of the substrate 1 by a spin coating method, and thereafter, this is heat-treated at 80 to 200 ° C. for 0.5 to 3 hours and thermally cured.
[0029]
Each of the organic resin insulation layers 3a, 3b, 3c has a through hole 8 having a minimum diameter of about 1.5 times the thickness of the organic resin insulation layer 2 at a predetermined position. The hole 8 functions as a formation hole for forming a through-hole conductor 9 that electrically connects each of the thin film wiring conductor layers 3 positioned above and below via the organic resin insulating layer 2 described later.
[0030]
The through holes 8 provided in each of the organic resin insulating layers 3a, 3b, 3c are, for example, photolithography technology, specifically, applying a resist material on each of the organic resin insulating layers 3a, 3b, 3c, and exposing and developing the resist material. To form a window portion having a predetermined shape at a predetermined position, and then an etching solution is disposed on the window portion of the resist material to remove the organic resin insulating layers 3a, 3b, and 3c located at the window portion of the resist material. Then, holes (through holes) are formed in the organic resin insulating layers 3a, 3b, and 3c, and finally, the resist material is peeled off and removed from the organic resin insulating layers 3a, 3b, and 3c.
[0031]
Furthermore, thin film wiring conductor layers 4a, 4b, and 4c having a predetermined pattern are formed on the upper surfaces of the organic resin insulating layers 3a, 3b, and 3c, and through holes 8 provided in the organic resin insulating layers 3a, 3b, and 3c. Through-hole conductors 9 are respectively disposed on the inner wall, and the thin-film wiring conductor layers 4a, 4b, and 4c positioned above and below with the through-hole conductors 9 sandwiching the organic resin insulating layers 3a, 3b, and 3c. Connected.
[0032]
The thin film wiring conductor layers 4a, 4b, 4c and the through-hole conductor 9 disposed on the upper surfaces of the organic resin insulating layers 3a, 3b, 3c and the inner wall of the through-hole 8 are made of a metal material such as copper, nickel, gold, aluminum, etc. Is formed by employing thin film technology such as electroless plating, vapor deposition, sputtering, etc., and photolithography technology, for example, when formed of copper, the upper surfaces of the organic resin insulating layers 3a, 3b, 3c And electroless copper comprising 0.06 mol / liter of copper sulfate, 0.3 mol / liter of formalin, 0.35 mol / liter of sodium hydroxide and 0.35 mol / liter of ethylenediaminetetraacetic acid on the inner surface of the through hole 8 A copper layer having a thickness of 1 μm to 40 μm is deposited using a plating bath, and then the copper layer is subjected to a predetermined pattern by a photolithography technique. Are processed between the organic resin insulating layers 3a, 3b, 3c and the inner wall of the through hole 8. In this case, since the thin-film wiring conductor layers 4a, 4b, 4c and the through-hole conductor 9 are formed by thin film technology, the wiring can be miniaturized. Can be formed.
[0033]
When the thickness of each organic resin insulating layer 3a, 3b, 3c exceeds 100 μm, the multilayer wiring part 2 forms a through hole 8 by adopting a photolithography technique in each organic resin insulating layer 3a, 3b, 3c. At this time, it becomes difficult to form the through-hole 8 in a desired clear shape due to a long etching processing time, and when the thickness is less than 5 μm, the organic layers positioned above and below the organic resin insulating layers 3a, 3b, and 3c. When roughening the surface to increase the bonding strength of the resin insulation layer, unnecessary holes are formed in the organic resin insulation layers 3a, 3b, and 3c, and unnecessary for the thin film wiring conductor layers 4a, 4b, and 4c positioned above and below. There is a risk of causing an electrical short circuit. Therefore, it is important that the thickness of each of the organic resin insulating layers 3a, 3b, and 3c is in the range of 5 μm to 100 μm.
[0034]
Further, when the thickness of each thin film wiring conductor layer 4a, 4b, 4c of the multilayer wiring portion 2 is less than 1 μm, the electric resistance value of each thin film wiring conductor layer 4a, 4b, 4c becomes large, and each thin film wiring conductor layer. It becomes difficult to transmit a predetermined electrical signal to 4a, 4b, 4c, and when it exceeds 40 μm, the thin film wiring conductor layers 4a, 4b, 4c are deposited on the organic resin insulating layers 3a, 3b, 3c. A large stress is present inside the conductor layers 4a, 4b, and 4c, and the thin internal wiring conductor layers 4a, 4b, and 4c are easily peeled off from the organic resin insulating layers 3a, 3b, and 3c due to the large inherent stress. Therefore, it is preferable that the thickness of each thin-film wiring conductor layer 4a, 4b, 4c of the multilayer wiring portion 2 is in the range of 1 μm to 40 μm.
[0035]
Furthermore, the multilayer wiring portion 2 formed by the organic resin insulating layers 3a, 3b, 3c and the thin film wiring conductor layers 4a, 4b, 4c has a hole H in the organic resin insulating layer 3b and the hole. The dielectric ceramic 10 is inserted into the portion H, and the capacitive element A is formed by sandwiching the dielectric ceramic 10 with a part of the thin-film wiring conductor layers 4a and 4b disposed on both upper and lower surfaces thereof. The capacitive element A is electrically connected to the thin film wiring conductor layers 4a and 4b.
[0036]
The hole H formed in the organic resin insulating layer 3b functions as a space for accommodating the dielectric ceramic 10, and a method similar to that for forming the through hole 8 in the organic resin insulating layer 3b, specifically, In this case, a resist material is applied onto the organic resin insulating layer 3b, and a window portion having a predetermined shape is formed at a predetermined position by exposing and developing the resist material. Next, an etching solution is disposed on the window portion of the resist material. Then, the organic resin insulating layer 3b located in the window portion of the resist material is removed to form a hole H in the organic resin insulating layer 3b, and finally the resist material is peeled off from the organic resin insulating layer 3b and removed. Is done by.
[0037]
The dielectric ceramic 10 inserted into the hole H of the organic resin insulating layer 3b is made of a ceramic having a high relative dielectric constant such as barium titanate, strontium titanate, calcium titanate, magnesium titanate, etc. When it is made of barium acid, raw powders such as barium carbonate, titanium oxide, and magnesium titanate are calcined and reacted to obtain barium titanate, which is then pulverized into fine powder and mixed with an appropriate organic solvent and solvent. The slurry is made into a green sheet, and finally, the slurry is made into a green sheet by a doctor blade method, a calender roll method, or the like, and fired at a high temperature.
[0038]
Capacitor element A formed by sandwiching the upper and lower surfaces of dielectric ceramic 10 inserted into hole H of organic resin insulating layer 3b with a portion of thin-film wiring conductor layers 4a and 4b has a capacitance value of dielectric. The relative dielectric constant of the dielectric ceramic 10, the thickness of the dielectric ceramic 10, and the facing area of the thin film wiring conductor layers 4a and 4b across the dielectric ceramic 10, are determined by the relative dielectric constant of the dielectric ceramic 10 and the dielectric ceramic 10. A predetermined capacitance value can be obtained by adjusting the thickness or the like.
[0039]
The capacitive element A is built in the multilayer wiring portion 2 provided on the substrate 1, and therefore, components such as a semiconductor element, a capacitive element, a resistor, etc. are mounted on the multilayer wiring board, and a hybrid integrated circuit device or the like. In this case, it is not necessary to separately mount and mount a large number of capacitive elements on the multilayer wiring board. As a result, the number of components mounted on the multilayer wiring board is reduced, and the hybrid integrated circuit device and the like can be reduced in size. Become.
[0040]
Further, the capacitive element A formed by opposingly sandwiching the upper and lower surfaces of the dielectric ceramic 10 with a part of the thin film wiring conductor layers 4a and 4b, as shown in FIG. 2, includes the upper and lower surfaces of the dielectric ceramic 10 and the thin film wiring conductor layer 4a, The organic resin layer 11 is arranged between 4b.
[0041]
The organic resin layer 11 has a function of firmly bonding the thin film wiring conductor layers 4 a and 4 b to the upper and lower surfaces of the dielectric ceramic 10 and completely filling the hole H provided in the organic resin insulating layer 3 b with the dielectric ceramic 10. None. This makes it possible to electrically connect the capacitive element A having a predetermined capacitance value to a predetermined position of the thin-film wiring conductor layers 4a and 4b with high reliability, and organically positioned above the organic resin insulating layer 3b. The resin insulating layer 3c is flat, and the thin-film wiring conductor layers 4b, 4c and the like can be formed in a predetermined pattern without causing disconnection or the like.
[0042]
The organic resin layer 11 is made of the same material as the organic resin insulating layer 3b, specifically, an organic resin such as an epoxy resin, a bismaleimide polyazide resin, a polyphenylene ether resin, or a fluorine resin. Paste epoxy resin precursor by adding and mixing curing agents such as amine curing agent, imidazole curing agent, acid anhydride curing agent to bisphenol A type epoxy resin, novolak type epoxy resin, glycidyl ester type epoxy resin, etc. And the epoxy resin precursor is filled into the hole H of the organic resin insulating layer 3b, and then the dielectric ceramic 10 is inserted into the hole H of the organic resin insulating layer 3b. An appropriate amount of the epoxy resin precursor is filled again at the top, and finally the epoxy resin precursor is heated at a temperature of 80 to 200 ° C. And management, upper and lower surfaces and thin-film wiring conductor layer 4a of the dielectric ceramic 10 by thermally curing, disposed between the 4b.
[0043]
The organic resin layer 11 has a thickness of 2 μm to 40 μm. If the thickness is less than 2 μm, the bonding between the upper and lower surfaces of the dielectric ceramic 10 and the thin film wiring conductor layers 4a and 4b tends to be weakened. If it exceeds 40 μm, the capacitance value of the capacitive element A connected between the thin-film wiring conductor layers 4a and 4b becomes small, and there is a risk that it is difficult to incorporate the capacitive element A having a large capacitance value. . Therefore, the organic resin layer 11 preferably has a thickness in the range of 2 μm to 40 μm.
[0044]
Furthermore, when the organic resin layer 11 contains 10 wt% to 95 wt% of a powder composed of at least one of silicon oxide, aluminum oxide, aluminum nitride, titanate compound, and zirconate compound, the organic resin layer A large amount of minute irregularities are formed on the surface of the substrate 11 to increase the bonding area between the thin-film wiring conductor layers 4a and 4b and the organic resin layer 11, thereby greatly improving the bonding strength between the two and the organic resin. The thermal expansion coefficient of the layer 11 is adjusted, and when heat is applied, the organic resin layer 11 expands and protrudes from the hole H and presses the thin film wiring conductor layers 4a and 4b positioned above and below the thin film wiring conductor layer 4a. It is possible to effectively prevent 4b from causing a disconnection or the like. Therefore, it is preferable that the organic resin layer 11 is added and mixed with powder composed of at least one of silicon oxide, aluminum oxide, aluminum nitride, titanate compound, and zirconate compound.
[0045]
Furthermore, when powders made of silicon oxide, aluminum oxide, aluminum nitride, titanate compound, zirconate compound, etc. are added and mixed in the organic resin layer 11, it is organic if the added amount is less than 10% by weight. The coefficient of thermal expansion of the resin layer 11 cannot be adjusted sufficiently, and part of the organic resin layer 11 expands and protrudes above and below the hole H by the application of heat, and the thin film wiring conductor layers 4a and 4b are disconnected. There is a risk of inviting it, and when it exceeds 95% by weight, the strength of the organic resin layer 11 may be deteriorated. Therefore, when the powder made of silicon oxide, aluminum oxide, aluminum nitride, titanate compound, zirconate compound or the like is added and mixed in the organic resin layer 11, the added amount of the powder is 10 wt% to 95 wt%. The range of is preferable.
[0046]
Thus, according to the multilayer wiring board described above, the electrodes of the electronic component A such as a semiconductor element or a capacitive element are connected to the bonding pad 10 provided on the upper surface of the uppermost organic resin insulating layer 2 by thermocompression bonding or the like. When the electrode is electrically connected to the thin film wiring conductor layer 3 through the bonding pad 10, a semiconductor device or a hybrid integrated circuit device is obtained. When a part of the thin film wiring conductor layer 3 is connected to an external electric circuit, the electronic component A is obtained. Will be connected to the external electric circuit.
[0047]
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment, only the upper surface side of the substrate 1 is possible. A multilayer wiring portion 2 formed by alternately laminating a plurality of organic resin insulating layers 3a, 3b, and 3c and a plurality of thin film wiring conductor layers 4a, 4b, and 4c is attached. It may be provided only on the lower surface side of the substrate 1 or may be provided on both upper and lower main surfaces.
[0048]
Further, in the above-described embodiment, the multilayer wiring portion 2 formed by alternately arranging the organic resin insulating layers 3a, 3b, and 3c and the thin film wiring conductor layers 4a, 4b, and 4c in the multilayer is provided in each organic resin insulating layer 3a. If the top surfaces of 3b and 3c are rough surfaces with a center line average roughness (Ra) of 0.05 μm ≦ Ra ≦ 5 μm, the organic resin insulating layers 3a, 3b and 3c and the thin-film wiring conductor layers 4a, 4b and 4c Bonding and bonding between the organic resin insulating layers 3a, 3b, and 3c positioned above and below can be strengthened. Accordingly, the upper surfaces of the organic resin insulating layers 3a, 3b, and 3c of the multilayer wiring portion 2 are roughened by an etching method or the like so that the centerline average roughness (Ra) is 0.05 μm ≦ Ra ≦ 5 μm. It is preferable to keep it.
[0049]
Further, the organic resin insulating layers 3a, 3b, 3c have a count value of the height of unevenness (Pc) in the length of 2.5 mm on the surface thereof, 1 μm ≦ Pc ≦ 10 μm is 500 or more, 0.1 μm ≦ Pc ≦ When 1 μm is 2500 or more, and 0.01 μm ≦ Pc ≦ 0.1 μm is 12500 or more, the organic resin insulating layers 3a, 3b, 3c and the thin film wiring conductor layers 4a, 4b, 4c are joined and the organic resin positioned above and below The bonding between the insulating layers 3a, 3b, and 3c becomes stronger. Accordingly, the organic resin insulating layers 3a, 3b, 3c have a count value of the height of the unevenness (Pc) at a length of 2.5 mm on the surface thereof, 1 μm ≦ Pc ≦ 10 μm is 500 or more, 0.1 μm ≦ Pc It is preferable that ≦ 1 μm is 2500 or more, and 0.01 μm ≦ Pc ≦ 0.1 μm is 12500 or more.
[0050]
The center line average roughness (Ra) is 0.05 μm ≦ Ra ≦ 5 μm, and the count value of the height of irregularities (Pc) at a length of 2.5 mm is 500 μm or more when 1 μm ≦ Pc ≦ 10 μm, 0.1 μm ≦ Pc ≦ 1 μm is 2500 or more, and 0.01 μm ≦ Pc ≦ 0.1 μm is 12500 or more. The organic resin insulation layers 3a, 3b, and 3c are formed on the top surface of the organic resin insulation layers 3a, 3b, and 3c with CHF. Three , CF Four The surface is roughened to a predetermined roughness by performing a reactive ion etching process by blowing a gas such as Ar.
[0051]
The count values of the center line average roughness (Ra) on the top surfaces of the organic resin insulating layers 3a, 3b, 3c and the unevenness height (Pc) at a length of 2.5 mm are the organic resin insulating layers 3a, 3b, The surface of 3c is scanned with a 50 μm square diagonal (70 μm) with an atomic force microscope (Dimension 3000-Nano Scope III manufactured by Digital Instruments Inc.), and the surface state is inspected and measured. Issued.
[0052]
【The invention's effect】
According to the multilayer wiring board of the present invention, since the wiring is formed on the substrate by the thin film technique, the wiring can be miniaturized and the wiring can be formed at a very high density.
[0053]
Further, according to the multilayer wiring board of the present invention, a hole is provided in the organic resin insulating layer, a dielectric ceramic is inserted into the hole, and a part of the thin film wiring conductor layer is disposed opposite to the upper and lower surfaces of the dielectric ceramic. Therefore, by adjusting the relative permittivity, thickness, width, and length of the dielectric ceramic, an arbitrary number of capacitive elements having a predetermined capacitance value can be incorporated, and the multilayer wiring board can be equipped with semiconductor elements and capacitors. When a component such as an element or a resistor is mounted to form a hybrid integrated circuit device, it is not necessary to mount a large number of additional capacitive elements on the multilayer wiring board, and as a result, the number of components mounted on the multilayer wiring board is reduced. A hybrid integrated circuit device or the like can be downsized.
[0054]
Further, according to the multilayer wiring board of the present invention, since the organic resin layer is interposed between the upper and lower surfaces of the dielectric ceramic and the thin film wiring conductor layer, the bonding of the dielectric ceramic and the thin film wiring conductor layer by the organic resin layer is performed. This makes it possible to electrically connect a capacitive element having a predetermined capacitance value to a predetermined position of the thin-film wiring conductor layer with high reliability, and a hole provided in the organic resin insulating layer includes a dielectric ceramic and an organic resin. It is possible to form the thin film wiring conductor layer in a predetermined pattern without incurring disconnection or the like by completely filling the organic resin insulating layer located on the upper layer and flattening the organic resin insulating layer located above.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment of a multilayer wiring board according to the present invention.
FIG. 2 is an enlarged cross-sectional view of a main part of the multilayer wiring board shown in FIG.
[Explanation of symbols]
1 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Board
2 ..... multilayer wiring part
3a, 3b, 3c ... Organic resin insulation layer
4a, 4b, 4c... Thin film wiring conductor layer
8 ... through hole
9 .... Through-hole conductor
10 ... Dielectric porcelain
11 ... Organic resin layer
A ... Capacitance element
H ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Hole

Claims (3)

基板上に、有機樹脂絶縁層と薄膜配線導体層とを交互に多層に配設するとともに上下に位置する薄膜配線導体層を各有機樹脂絶縁層に設けたスルーホール導体を介して接続してなる多層配線基板であって、前記有機樹脂絶縁層の少なくとも1層に穴部を設け、該穴部内に誘電体磁器を挿入させるとともに該誘電体磁器の上下面に厚み2μm〜40μmの有機樹脂層を介し薄膜配線導体層の一部を対向配置させて該対向する薄膜配線導体層間に容量素子を電気的に接続したことを特徴とする多層配線基板。On the substrate, organic resin insulation layers and thin film wiring conductor layers are alternately arranged in multiple layers, and upper and lower thin film wiring conductor layers are connected via through-hole conductors provided in each organic resin insulation layer. a multilayer wiring board, the organic resin a hole portion is provided in at least one layer of the insulating layer, an organic resin 2μm~40μm thickness on the upper and lower surfaces of the dielectric porcelain together when inserting the dielectric ceramic in the hole portion multi-layer wiring board, wherein a portion of and through a layer thin film wiring conductor layer was opposed to electrically connect the capacitive element to the thin film wiring conductor layers of the facing. 前記有機樹脂層の厚みが2μm乃至40μmであることを特徴とする請求項1記載の多層配線基板。The multilayer wiring board according to claim 1, wherein the organic resin layer has a thickness of 2 μm to 40 μm. 前記有機樹脂層に、酸化珪素、酸化アルミニウム、窒化アルミニウム、チタン酸化合物、ジルコン酸化合物の少なくとも1種から成る粉末を10重量%乃至95重量%含有させたことを特徴とする請求項1記載の多層配線基板。2. The organic resin layer according to claim 1, wherein the organic resin layer contains 10 wt% to 95 wt% of a powder composed of at least one of silicon oxide, aluminum oxide, aluminum nitride, titanate compound, and zirconate compound. Multilayer wiring board.
JP04367797A 1997-02-27 1997-02-27 Multilayer wiring board Expired - Fee Related JP3688844B2 (en)

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JP04367797A JP3688844B2 (en) 1997-02-27 1997-02-27 Multilayer wiring board

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JP3688844B2 true JP3688844B2 (en) 2005-08-31

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US7132743B2 (en) * 2003-12-23 2006-11-07 Intel Corporation Integrated circuit package substrate having a thin film capacitor structure

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